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gEDA-cvs: gaf.git: branch: master updated (1.6.1-20100214-189-g1e93f7b)
The branch, master has been updated
via 1e93f7bea2cbe0fa8887337c261093b55c31dd6d (commit)
from f5ada1de1372bd3772b4f4bd33afa59803c1dade (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
=========
Summary
=========
docs/scripts/Makefile.am | 3 +++
gnetlist/scheme/Makefile.am | 3 +++
gnetlist/scheme/gnet-verilog.scm | 4 ++++
.../tests/common/outputs/verilog/JD-output.net | 4 ++++
.../common/outputs/verilog/JD_Include-output.net | 4 ++++
.../outputs/verilog/JD_Include_nomunge-output.net | 4 ++++
.../common/outputs/verilog/JD_Sort-output.net | 4 ++++
.../outputs/verilog/JD_Sort_nomunge-output.net | 4 ++++
.../common/outputs/verilog/JD_nomunge-output.net | 4 ++++
.../outputs/verilog/SlottedOpamps-output.net | 4 ++++
.../common/outputs/verilog/TwoStageAmp-output.net | 4 ++++
.../outputs/verilog/TwoStageAmp_Include-output.net | 4 ++++
.../outputs/verilog/TwoStageAmp_Sort-output.net | 4 ++++
.../common/outputs/verilog/cascade-output.net | 4 ++++
.../common/outputs/verilog/multiequal-output.net | 4 ++++
.../common/outputs/verilog/netattrib-output.net | 4 ++++
.../common/outputs/verilog/powersupply-output.net | 4 ++++
.../common/outputs/verilog/singlenet-output.net | 4 ++++
.../outputs/verilog/stack-torture-output.net | 4 ++++
gschem/include/Makefile.am | 2 ++
gschem/include/prototype.h | 2 ++
gschem/scheme/pcb.scm | 2 ++
gschem/scripts/gschemdoc.sh | 2 ++
gschem/scripts/image.scm | 2 ++
gschem/scripts/makeimages | 1 +
gschem/scripts/print.scm | 2 ++
libgeda/share/Makefile.am | 3 +++
symbols/documentation/nc.doc | 2 ++
utils/examples/gsch2pcb/project.sample | 2 ++
utils/scripts/Makefile.am | 2 ++
utils/scripts/convert_sym.awk | 2 ++
utils/scripts/pads_backannotate | 2 ++
utils/scripts/pcb_backannotate | 2 ++
utils/scripts/refdes_renum | 2 ++
utils/src/convert_sym.c | 1 +
utils/src/grenum.c | 1 +
utils/src/grenum.h | 1 +
utils/src/gsch2pcb.c | 2 ++
utils/src/olib.l | 4 +++-
utils/src/smash_megafile.c | 2 ++
utils/tests/gxyrs/README.txt | 3 +++
utils/tests/gxyrs/inputs/pcb_example1.xy | 1 +
utils/tests/gxyrs/inputs/pcb_example2.xy | 1 +
.../outputs/chunits_bad_col_num1-pcb_example1.xy | 1 +
.../outputs/chunits_bad_col_num2-pcb_example1.xy | 1 +
.../chunits_col_num_too_high-pcb_example1.xy | 1 +
.../chunits_negative_col_num-pcb_example1.xy | 1 +
.../gxyrs/outputs/chunits_no_units-pcb_example1.xy | 1 +
.../gxyrs/outputs/del_case_insens1-pcb_example1.xy | 1 +
.../gxyrs/outputs/del_case_insens2-pcb_example2.xy | 1 +
.../gxyrs/outputs/del_case_sens1-pcb_example1.xy | 1 +
.../gxyrs/outputs/del_case_sens2-pcb_example2.xy | 1 +
.../gxyrs/outputs/del_case_sens3-pcb_example1.xy | 1 +
.../gxyrs/outputs/del_case_sens4-pcb_example2.xy | 1 +
.../del_check_cols_no_match-pcb_example1.xy | 1 +
.../del_check_cols_return_minus1-pcb_example1.xy | 1 +
.../tests/gxyrs/outputs/do_nothing-pcb_example1.xy | 1 +
.../outputs/do_nothing_tabulated-pcb_example1.xy | 1 +
.../gxyrs/outputs/footprint_pcb1-pcb_example1.xy | 1 +
.../insert_col_bad_col_num1-pcb_example1.xy | 1 +
.../insert_col_bad_col_num2-pcb_example1.xy | 1 +
.../insert_col_col_num_too_high-pcb_example1.xy | 1 +
utils/tests/refdes_renum/README.txt | 3 +++
utils/tests/refdes_renum/run_tests.sh | 2 ++
utils/tests/refdes_renum/tests.list | 2 ++
65 files changed, 145 insertions(+), 1 deletions(-)
=================
Commit Messages
=================
commit 1e93f7bea2cbe0fa8887337c261093b55c31dd6d
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Revert "Remove some CVS keywords."
This reverts commit f5ada1de1372bd3772b4f4bd33afa59803c1dade, which
was pushed to the repository in error.
:100644 100644 4a40a7f... 2a9ed40... M docs/scripts/Makefile.am
:100644 100644 92e707a... dcbc582... M gnetlist/scheme/Makefile.am
:100644 100644 e006a1e... f0f5b8c... M gnetlist/scheme/gnet-verilog.scm
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD-output.net
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Include-output.net
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
:100644 100644 7bafd8f... d6e3814... M gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
:100644 100644 e420a9a... 4522bca... M gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
:100644 100644 ff6c48a... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
:100644 100644 ff6c48a... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
:100644 100644 ff6c48a... 2fd2eb3... M gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
:100644 100644 587a11a... 5af04ac... M gnetlist/tests/common/outputs/verilog/cascade-output.net
:100644 100644 37d6e9f... 5a2fe51... M gnetlist/tests/common/outputs/verilog/multiequal-output.net
:100644 100644 495fe68... dba917e... M gnetlist/tests/common/outputs/verilog/netattrib-output.net
:100644 100644 e9a27a9... 3611994... M gnetlist/tests/common/outputs/verilog/powersupply-output.net
:100644 100644 e1beddd... 3790cab... M gnetlist/tests/common/outputs/verilog/singlenet-output.net
:100644 100644 cfde1f8... 8d1bed4... M gnetlist/tests/common/outputs/verilog/stack-torture-output.net
:100644 100644 baa74ea... 00b553d... M gschem/include/Makefile.am
:100644 100644 4c80281... d0439a3... M gschem/include/prototype.h
:100644 100644 97231bb... ef615c2... M gschem/scheme/pcb.scm
:100644 100644 52aa080... c24cde8... M gschem/scripts/gschemdoc.sh
:100644 100644 f5e1c63... e2bd3e0... M gschem/scripts/image.scm
:100755 100755 41e580c... 1790f46... M gschem/scripts/makeimages
:100644 100644 200a159... b2c5d3f... M gschem/scripts/print.scm
:100644 100644 e2fb92c... 8f1f08f... M libgeda/share/Makefile.am
:100644 100644 196b7ac... cef6cd4... M symbols/documentation/nc.doc
:100644 100644 38078d0... 8a1d134... M utils/examples/gsch2pcb/project.sample
:100644 100644 5636420... 5ab4527... M utils/scripts/Makefile.am
:100644 100644 723c919... 1877f6a... M utils/scripts/convert_sym.awk
:100755 100755 c7038f0... 84fe2be... M utils/scripts/pads_backannotate
:100755 100755 a994c42... 10042e4... M utils/scripts/pcb_backannotate
:100755 100755 da6dbba... 88e1876... M utils/scripts/refdes_renum
:100644 100644 1b122b5... fa61810... M utils/src/convert_sym.c
:100644 100644 9d9b11c... 086aef2... M utils/src/grenum.c
:100644 100644 0978e60... f729825... M utils/src/grenum.h
:100644 100644 5ed70b4... 4d3a825... M utils/src/gsch2pcb.c
:100644 100644 2cbc2f5... 9a24376... M utils/src/olib.l
:100644 100644 519692d... d2910bd... M utils/src/smash_megafile.c
:100644 100644 11177a8... 1c325bb... M utils/tests/gxyrs/README.txt
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/inputs/pcb_example1.xy
:100644 100644 2a946d0... c1bda42... M utils/tests/gxyrs/inputs/pcb_example2.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/chunits_bad_col_num1-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/chunits_bad_col_num2-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/chunits_col_num_too_high-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/chunits_negative_col_num-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/chunits_no_units-pcb_example1.xy
:100644 100644 6bda2c6... 3d383f4... M utils/tests/gxyrs/outputs/del_case_insens1-pcb_example1.xy
:100644 100644 6bda2c6... 3d383f4... M utils/tests/gxyrs/outputs/del_case_insens2-pcb_example2.xy
:100644 100644 6bda2c6... 3d383f4... M utils/tests/gxyrs/outputs/del_case_sens1-pcb_example1.xy
:100644 100644 2a946d0... c1bda42... M utils/tests/gxyrs/outputs/del_case_sens2-pcb_example2.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/del_case_sens3-pcb_example1.xy
:100644 100644 6bda2c6... 3d383f4... M utils/tests/gxyrs/outputs/del_case_sens4-pcb_example2.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/del_check_cols_no_match-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/del_check_cols_return_minus1-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/do_nothing-pcb_example1.xy
:100644 100644 5d5215c... a47d267... M utils/tests/gxyrs/outputs/do_nothing_tabulated-pcb_example1.xy
:100644 100644 063e266... 8d7d3c1... M utils/tests/gxyrs/outputs/footprint_pcb1-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/insert_col_bad_col_num1-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/insert_col_bad_col_num2-pcb_example1.xy
:100644 100644 a00ad3a... ee9854b... M utils/tests/gxyrs/outputs/insert_col_col_num_too_high-pcb_example1.xy
:100644 100644 0fe875c... 9bb960b... M utils/tests/refdes_renum/README.txt
:100755 100755 873fa41... 9bcfab2... M utils/tests/refdes_renum/run_tests.sh
:100644 100644 e6fdcd7... c2c6bf0... M utils/tests/refdes_renum/tests.list
=========
Changes
=========
commit 1e93f7bea2cbe0fa8887337c261093b55c31dd6d
Author: Peter TB Brett <peter@xxxxxxxxxxxxx>
Commit: Peter TB Brett <peter@xxxxxxxxxxxxx>
Revert "Remove some CVS keywords."
This reverts commit f5ada1de1372bd3772b4f4bd33afa59803c1dade, which
was pushed to the repository in error.
diff --git a/docs/scripts/Makefile.am b/docs/scripts/Makefile.am
index 4a40a7f..2a9ed40 100644
--- a/docs/scripts/Makefile.am
+++ b/docs/scripts/Makefile.am
@@ -1,3 +1,6 @@
+## $Id$
+##
+
EXTRA_DIST = populatemkfiles.sh copygitignores.sh
MOSTLYCLEANFILES = *.log *~
diff --git a/gnetlist/scheme/Makefile.am b/gnetlist/scheme/Makefile.am
index 92e707a..dcbc582 100644
--- a/gnetlist/scheme/Makefile.am
+++ b/gnetlist/scheme/Makefile.am
@@ -1,3 +1,6 @@
+## $Id$
+##
+
M4= @M4@
PCBM4DIR= @PCBM4DIR@
PCBCONFDIR= @PCBCONFDIR@
diff --git a/gnetlist/scheme/gnet-verilog.scm b/gnetlist/scheme/gnet-verilog.scm
index e006a1e..f0f5b8c 100644
--- a/gnetlist/scheme/gnet-verilog.scm
+++ b/gnetlist/scheme/gnet-verilog.scm
@@ -179,6 +179,10 @@
(display "/* WARNING: This is a generated file, edits */\n" p)
(display "/* made here will be lost next time */\n" p)
(display "/* you run gnetlist! */\n" p)
+ (display "/* Id ..........$Id$ */\n" p)
+ (display "/* Source.......$Source$ */\n" p)
+ (display "/* Revision.....$Revision$ */\n" p)
+ (display "/* Author.......$Author$ */\n" p)
(newline p)
(verilog:write-module-declaration verilog:get-module-name
port-list p)
diff --git a/gnetlist/tests/common/outputs/verilog/JD-output.net b/gnetlist/tests/common/outputs/verilog/JD-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
index 7bafd8f..d6e3814 100644
--- a/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
index e420a9a..4522bca 100644
--- a/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
index ff6c48a..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
index ff6c48a..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
index ff6c48a..2fd2eb3 100644
--- a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/cascade-output.net b/gnetlist/tests/common/outputs/verilog/cascade-output.net
index 587a11a..5af04ac 100644
--- a/gnetlist/tests/common/outputs/verilog/cascade-output.net
+++ b/gnetlist/tests/common/outputs/verilog/cascade-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/multiequal-output.net b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
index 37d6e9f..5a2fe51 100644
--- a/gnetlist/tests/common/outputs/verilog/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/netattrib-output.net b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
index 495fe68..dba917e 100644
--- a/gnetlist/tests/common/outputs/verilog/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/powersupply-output.net b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
index e9a27a9..3611994 100644
--- a/gnetlist/tests/common/outputs/verilog/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/singlenet-output.net b/gnetlist/tests/common/outputs/verilog/singlenet-output.net
index e1beddd..3790cab 100644
--- a/gnetlist/tests/common/outputs/verilog/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/verilog/singlenet-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gnetlist/tests/common/outputs/verilog/stack-torture-output.net b/gnetlist/tests/common/outputs/verilog/stack-torture-output.net
index cfde1f8..8d1bed4 100644
--- a/gnetlist/tests/common/outputs/verilog/stack-torture-output.net
+++ b/gnetlist/tests/common/outputs/verilog/stack-torture-output.net
@@ -2,6 +2,10 @@
/* WARNING: This is a generated file, edits */
/* made here will be lost next time */
/* you run gnetlist! */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
module \not found (
diff --git a/gschem/include/Makefile.am b/gschem/include/Makefile.am
index baa74ea..00b553d 100644
--- a/gschem/include/Makefile.am
+++ b/gschem/include/Makefile.am
@@ -1,3 +1,5 @@
+## $Id$
+##
## Process this file with automake to produce Makefile.in
noinst_HEADERS = \
diff --git a/gschem/include/prototype.h b/gschem/include/prototype.h
index 4c80281..d0439a3 100644
--- a/gschem/include/prototype.h
+++ b/gschem/include/prototype.h
@@ -1,3 +1,5 @@
+/* $Id$ */
+
/* gschem_toplevel.c */
GSCHEM_TOPLEVEL *gschem_toplevel_new();
/* a_pan.c */
diff --git a/gschem/scheme/pcb.scm b/gschem/scheme/pcb.scm
index 97231bb..ef615c2 100644
--- a/gschem/scheme/pcb.scm
+++ b/gschem/scheme/pcb.scm
@@ -53,6 +53,7 @@
(use-modules (ice-9 popen))
(gschem-log "Loading the PCB major mode\n")
+(gschem-log "PCB-mode version $Id$\n")
(gschem-log "The PCB major mode is incomplete and considered experimental at this time\n")
;; These may be changed by the user in their gafrc files (FIXME -- make this
@@ -213,6 +214,7 @@
(define (pcb:about)
(gschem-msg (string-append
"This is the pcb major mode for gschem\n"
+ "pcb.scm version $Id$\n"
"***** WARNING *****\n"
"This is highly experimental\n"
"You should save your work often\n"
diff --git a/gschem/scripts/gschemdoc.sh b/gschem/scripts/gschemdoc.sh
index 52aa080..c24cde8 100644
--- a/gschem/scripts/gschemdoc.sh
+++ b/gschem/scripts/gschemdoc.sh
@@ -1,4 +1,6 @@
#!/bin/sh
+# $Id$
+#
# NOTE: built from gschemdoc.sh
#
# Present as relevant documentation as possible wrt a component
diff --git a/gschem/scripts/image.scm b/gschem/scripts/image.scm
index f5e1c63..e2bd3e0 100644
--- a/gschem/scripts/image.scm
+++ b/gschem/scripts/image.scm
@@ -1,3 +1,5 @@
+;; $Id$
+;;
;; This file may be used to produce png files from gschem schematics from the
;; command line. Typical usage is:
;;
diff --git a/gschem/scripts/makeimages b/gschem/scripts/makeimages
index 41e580c..1790f46 100755
--- a/gschem/scripts/makeimages
+++ b/gschem/scripts/makeimages
@@ -1,5 +1,6 @@
#!/bin/sh
#
+# $Id$
# This script requires the following packages :
# - gschem (located the your PATH )
diff --git a/gschem/scripts/print.scm b/gschem/scripts/print.scm
index 200a159..b2c5d3f 100644
--- a/gschem/scripts/print.scm
+++ b/gschem/scripts/print.scm
@@ -1,3 +1,5 @@
+;; $Id$
+;;
;; This file may be used to print gschem schematics from the
;; command line. Typical usage is:
;;
diff --git a/libgeda/share/Makefile.am b/libgeda/share/Makefile.am
index e2fb92c..8f1f08f 100644
--- a/libgeda/share/Makefile.am
+++ b/libgeda/share/Makefile.am
@@ -1,3 +1,6 @@
+# $Id$
+#
+
prologdatadir = $(GEDADATADIR)
prologdata_DATA = prolog.ps
diff --git a/symbols/documentation/nc.doc b/symbols/documentation/nc.doc
index 196b7ac..cef6cd4 100644
--- a/symbols/documentation/nc.doc
+++ b/symbols/documentation/nc.doc
@@ -1,3 +1,5 @@
+.\" $Id$
+.\"
.\" Example documentation for "No connection"
.\" don't take it too seriously ;-)"
.\"
diff --git a/utils/examples/gsch2pcb/project.sample b/utils/examples/gsch2pcb/project.sample
index 38078d0..8a1d134 100644
--- a/utils/examples/gsch2pcb/project.sample
+++ b/utils/examples/gsch2pcb/project.sample
@@ -1,3 +1,5 @@
+# $Id$
+#
# Sample poject file for gsch2pcb versions >= 1.0
#
# A project file may be named anything that does not end in ".sch" and placed
diff --git a/utils/scripts/Makefile.am b/utils/scripts/Makefile.am
index 5636420..5ab4527 100644
--- a/utils/scripts/Makefile.am
+++ b/utils/scripts/Makefile.am
@@ -1,3 +1,5 @@
+## $Id$
+##
## Process this file with automake to produce Makefile.in
bin_SCRIPTS = sarlacc_sym gschupdate gsymupdate refdes_renum \
diff --git a/utils/scripts/convert_sym.awk b/utils/scripts/convert_sym.awk
index 723c919..1877f6a 100644
--- a/utils/scripts/convert_sym.awk
+++ b/utils/scripts/convert_sym.awk
@@ -1,4 +1,6 @@
#!/usr/bin/awk -f
+# $Id$
+# $Author$
# awk script to convert viewlogic symbol files to geda files
#
#
diff --git a/utils/scripts/pads_backannotate b/utils/scripts/pads_backannotate
index c7038f0..84fe2be 100755
--- a/utils/scripts/pads_backannotate
+++ b/utils/scripts/pads_backannotate
@@ -1,5 +1,7 @@
#!/usr/bin/perl -w
#
+# $Id$
+#
# Copyright (C) 2003 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
diff --git a/utils/scripts/pcb_backannotate b/utils/scripts/pcb_backannotate
index a994c42..10042e4 100755
--- a/utils/scripts/pcb_backannotate
+++ b/utils/scripts/pcb_backannotate
@@ -1,5 +1,7 @@
#!/usr/bin/perl -w
#
+# $Id$
+#
# Copyright (C) 2003, 2006 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
diff --git a/utils/scripts/refdes_renum b/utils/scripts/refdes_renum
index da6dbba..88e1876 100755
--- a/utils/scripts/refdes_renum
+++ b/utils/scripts/refdes_renum
@@ -1,5 +1,7 @@
#!/usr/bin/perl -w
#
+# $Id$
+#
# Copyright (C) 2003 Dan McMahill
#
# This program is free software; you can redistribute it and/or modify
diff --git a/utils/src/convert_sym.c b/utils/src/convert_sym.c
index 1b122b5..fa61810 100644
--- a/utils/src/convert_sym.c
+++ b/utils/src/convert_sym.c
@@ -33,6 +33,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA
*
+ * $Id$
*/
#include <stdio.h>
diff --git a/utils/src/grenum.c b/utils/src/grenum.c
index 9d9b11c..086aef2 100644
--- a/utils/src/grenum.c
+++ b/utils/src/grenum.c
@@ -1,3 +1,4 @@
+/* $Id$ */
/* This is grenum, an advanced refdes renumber utility for gEDA's gschem.
*
* Copyright (C) 2005-2010 Levente Kovacs
diff --git a/utils/src/grenum.h b/utils/src/grenum.h
index 0978e60..f729825 100644
--- a/utils/src/grenum.h
+++ b/utils/src/grenum.h
@@ -1,3 +1,4 @@
+/* $Id$ */
#include <stdio.h>
#define GRVERSION "24052006"
#define COMP_DATE __DATE__
diff --git a/utils/src/gsch2pcb.c b/utils/src/gsch2pcb.c
index 5ed70b4..4d3a825 100644
--- a/utils/src/gsch2pcb.c
+++ b/utils/src/gsch2pcb.c
@@ -1,3 +1,5 @@
+/* $Id$ */
+
/* gsch2pcb
|
| Bill Wilson billw@xxxxxx
diff --git a/utils/src/olib.l b/utils/src/olib.l
index 2cbc2f5..9a24376 100644
--- a/utils/src/olib.l
+++ b/utils/src/olib.l
@@ -1,5 +1,7 @@
%{
-/* olib.lex - Orcad to gEDA lib converter
+/* $Id$
+
+ olib.lex - Orcad to gEDA lib converter
Copyright (C) 2002 Mario Pascucci <m.pas@xxxxxxxxx>
This program is free software; you can redistribute it and/or modify
diff --git a/utils/src/smash_megafile.c b/utils/src/smash_megafile.c
index 519692d..d2910bd 100644
--- a/utils/src/smash_megafile.c
+++ b/utils/src/smash_megafile.c
@@ -19,6 +19,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111 USA
*
+ * $Id$
+ *
*/
#ifdef HAVE_CONFIG_H
diff --git a/utils/tests/gxyrs/README.txt b/utils/tests/gxyrs/README.txt
index 11177a8..1c325bb 100644
--- a/utils/tests/gxyrs/README.txt
+++ b/utils/tests/gxyrs/README.txt
@@ -1,3 +1,6 @@
+# $Id$
+#
+
This directory contains the testsuite for the "gxyrs" script.
No modifications to this script are allowed without adding tests here.
If a bug report is filed, a test must be added to show the bug before
diff --git a/utils/tests/gxyrs/inputs/pcb_example1.xy b/utils/tests/gxyrs/inputs/pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/inputs/pcb_example1.xy
+++ b/utils/tests/gxyrs/inputs/pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/inputs/pcb_example2.xy b/utils/tests/gxyrs/inputs/pcb_example2.xy
index 2a946d0..c1bda42 100644
--- a/utils/tests/gxyrs/inputs/pcb_example2.xy
+++ b/utils/tests/gxyrs/inputs/pcb_example2.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/chunits_bad_col_num1-pcb_example1.xy b/utils/tests/gxyrs/outputs/chunits_bad_col_num1-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/chunits_bad_col_num1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/chunits_bad_col_num1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/chunits_bad_col_num2-pcb_example1.xy b/utils/tests/gxyrs/outputs/chunits_bad_col_num2-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/chunits_bad_col_num2-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/chunits_bad_col_num2-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/chunits_col_num_too_high-pcb_example1.xy b/utils/tests/gxyrs/outputs/chunits_col_num_too_high-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/chunits_col_num_too_high-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/chunits_col_num_too_high-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/chunits_negative_col_num-pcb_example1.xy b/utils/tests/gxyrs/outputs/chunits_negative_col_num-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/chunits_negative_col_num-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/chunits_negative_col_num-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/chunits_no_units-pcb_example1.xy b/utils/tests/gxyrs/outputs/chunits_no_units-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/chunits_no_units-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/chunits_no_units-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_insens1-pcb_example1.xy b/utils/tests/gxyrs/outputs/del_case_insens1-pcb_example1.xy
index 6bda2c6..3d383f4 100644
--- a/utils/tests/gxyrs/outputs/del_case_insens1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/del_case_insens1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_insens2-pcb_example2.xy b/utils/tests/gxyrs/outputs/del_case_insens2-pcb_example2.xy
index 6bda2c6..3d383f4 100644
--- a/utils/tests/gxyrs/outputs/del_case_insens2-pcb_example2.xy
+++ b/utils/tests/gxyrs/outputs/del_case_insens2-pcb_example2.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_sens1-pcb_example1.xy b/utils/tests/gxyrs/outputs/del_case_sens1-pcb_example1.xy
index 6bda2c6..3d383f4 100644
--- a/utils/tests/gxyrs/outputs/del_case_sens1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/del_case_sens1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_sens2-pcb_example2.xy b/utils/tests/gxyrs/outputs/del_case_sens2-pcb_example2.xy
index 2a946d0..c1bda42 100644
--- a/utils/tests/gxyrs/outputs/del_case_sens2-pcb_example2.xy
+++ b/utils/tests/gxyrs/outputs/del_case_sens2-pcb_example2.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_sens3-pcb_example1.xy b/utils/tests/gxyrs/outputs/del_case_sens3-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/del_case_sens3-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/del_case_sens3-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_case_sens4-pcb_example2.xy b/utils/tests/gxyrs/outputs/del_case_sens4-pcb_example2.xy
index 6bda2c6..3d383f4 100644
--- a/utils/tests/gxyrs/outputs/del_case_sens4-pcb_example2.xy
+++ b/utils/tests/gxyrs/outputs/del_case_sens4-pcb_example2.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_check_cols_no_match-pcb_example1.xy b/utils/tests/gxyrs/outputs/del_check_cols_no_match-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/del_check_cols_no_match-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/del_check_cols_no_match-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/del_check_cols_return_minus1-pcb_example1.xy b/utils/tests/gxyrs/outputs/del_check_cols_return_minus1-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/del_check_cols_return_minus1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/del_check_cols_return_minus1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/do_nothing-pcb_example1.xy b/utils/tests/gxyrs/outputs/do_nothing-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/do_nothing-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/do_nothing-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/do_nothing_tabulated-pcb_example1.xy b/utils/tests/gxyrs/outputs/do_nothing_tabulated-pcb_example1.xy
index 5d5215c..a47d267 100644
--- a/utils/tests/gxyrs/outputs/do_nothing_tabulated-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/do_nothing_tabulated-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/footprint_pcb1-pcb_example1.xy b/utils/tests/gxyrs/outputs/footprint_pcb1-pcb_example1.xy
index 063e266..8d7d3c1 100644
--- a/utils/tests/gxyrs/outputs/footprint_pcb1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/footprint_pcb1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/insert_col_bad_col_num1-pcb_example1.xy b/utils/tests/gxyrs/outputs/insert_col_bad_col_num1-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/insert_col_bad_col_num1-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/insert_col_bad_col_num1-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/insert_col_bad_col_num2-pcb_example1.xy b/utils/tests/gxyrs/outputs/insert_col_bad_col_num2-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/insert_col_bad_col_num2-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/insert_col_bad_col_num2-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/gxyrs/outputs/insert_col_col_num_too_high-pcb_example1.xy b/utils/tests/gxyrs/outputs/insert_col_col_num_too_high-pcb_example1.xy
index a00ad3a..ee9854b 100644
--- a/utils/tests/gxyrs/outputs/insert_col_col_num_too_high-pcb_example1.xy
+++ b/utils/tests/gxyrs/outputs/insert_col_col_num_too_high-pcb_example1.xy
@@ -1,3 +1,4 @@
+# $Id$
# PcbXY Version 1.0
# Date: Sat Sep 6 14:29:26 2008 UTC
# Author:
diff --git a/utils/tests/refdes_renum/README.txt b/utils/tests/refdes_renum/README.txt
index 0fe875c..9bb960b 100644
--- a/utils/tests/refdes_renum/README.txt
+++ b/utils/tests/refdes_renum/README.txt
@@ -1,3 +1,6 @@
+# $Id$
+#
+
This directory contains the testsuite for the "refdes_renum" script.
No modifications to refdes_renum are allowed without adding tests here.
If a bug report is filed, a test must be added to show the bug before
diff --git a/utils/tests/refdes_renum/run_tests.sh b/utils/tests/refdes_renum/run_tests.sh
index 873fa41..9bcfab2 100755
--- a/utils/tests/refdes_renum/run_tests.sh
+++ b/utils/tests/refdes_renum/run_tests.sh
@@ -1,5 +1,7 @@
#!/bin/sh
#
+# $Id$
+#
# Copyright (C) 2007-2008 Dan McMahill
diff --git a/utils/tests/refdes_renum/tests.list b/utils/tests/refdes_renum/tests.list
index e6fdcd7..c2c6bf0 100644
--- a/utils/tests/refdes_renum/tests.list
+++ b/utils/tests/refdes_renum/tests.list
@@ -1,3 +1,5 @@
+# $Id$
+#
#
# Format:
#
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