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gEDA-cvs: branch: master updated (1.4.0-20080127-96-gaaa1abb)

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Subject: gEDA-cvs: branch: master updated (1.4.0-20080127-96-gaaa1abb)
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Date: Sat, 31 May 2008 10:06:26 -0700
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The branch, master has been updated
       via  aaa1abbcfac8e67901c5b2a279e0a13f88d774b0 (commit)
       via  ae9d82b1fdcd14acde5cbf4d54718ef3566aec80 (commit)
       via  850a80faa3038f688ef3630aff61a05c64904abc (commit)
       via  345cd09f3517380a466a3254b1f6dc16ef2ce896 (commit)
       via  8a0e4e649e0aab8820fcca32214f99322788bc31 (commit)
       via  dc5a2e6b352ac4e5833ec86c0685da747362e04a (commit)
      from  55b378f5eddc78f0f3f48c83f401e454323d9bd9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.


=========
 Summary
=========

 gnetlist/configure.ac                              |   44 +-
 gnetlist/tests/Makefile.am                         |    2 +-
 .../examples => gnetlist/tests/common}/.gitignore  |    1 +
 gnetlist/tests/common/Makefile.am                  |   15 +
 gnetlist/tests/common/always-copy.list             |    1 +
 gnetlist/tests/common/backends.list                |   34 +
 .../tests/common/inputs}/.gitignore                |    0 
 .../tests/{spice-sdb => common}/inputs/LVDfoo.sch  |    0 
 gnetlist/tests/common/inputs/Makefile.am           |   14 +
 .../tests/common/inputs}/Simulation.cmd            |    0 
 .../{spice-sdb => common}/inputs/SlottedOpamps.sch |    0 
 .../{spice-sdb => common}/inputs/TwoStageAmp.sch   |    0 
 gnetlist/tests/common/inputs/attribs               |    3 +
 gnetlist/tests/{ => common/inputs}/cascade.sch     |    0 
 .../tests/common/inputs}/gafrc                     |    0 
 .../tests/common/inputs/models}/.gitignore         |    0 
 .../{spice-sdb => common}/inputs/models/2N3904.mod |    0 
 .../inputs/models/Makefile.am                      |    0 
 .../inputs/models/openIP_5.cir                     |    0 
 gnetlist/tests/{ => common/inputs}/multiequal.sch  |    0 
 gnetlist/tests/{ => common/inputs}/netattrib.sch   |    0 
 gnetlist/tests/{ => common/inputs}/powersupply.sch |    0 
 gnetlist/tests/{ => common/inputs}/singlenet.sch   |   28 +-
 .../tests/common/inputs/sym}/.gitignore            |    0 
 .../inputs/sym/LM324_slotted-1.sym                 |    0 
 .../tests/{spice-sdb => common}/inputs/sym/LVD.sym |    0 
 .../{spice-sdb => common}/inputs/sym/Makefile.am   |    0 
 .../tests/common/inputs}/sym/transistor.sym        |    0 
 .../tests/common/outputs}/.gitignore               |    0 
 gnetlist/tests/common/outputs/Makefile.am          |   37 +
 .../tests/common/outputs/PCB}/.gitignore           |    0 
 gnetlist/tests/common/outputs/PCB/JD-output.net    |    6 +
 gnetlist/tests/common/outputs/PCB/JD.retcode       |    1 +
 .../tests/common/outputs/PCB/JD_Include-output.net |    6 +
 .../tests/common/outputs/PCB/JD_Include.retcode    |    1 +
 .../outputs/PCB/JD_Include_nomunge-output.net      |    6 +
 .../common/outputs/PCB/JD_Include_nomunge.retcode  |    1 +
 .../tests/common/outputs/PCB/JD_Sort-output.net    |    6 +
 gnetlist/tests/common/outputs/PCB/JD_Sort.retcode  |    1 +
 .../common/outputs/PCB/JD_Sort_nomunge-output.net  |    6 +
 .../common/outputs/PCB/JD_Sort_nomunge.retcode     |    1 +
 .../tests/common/outputs/PCB/JD_nomunge-output.net |    6 +
 gnetlist/tests/common/outputs/PCB/Makefile.am      |   30 +
 .../common/outputs/PCB/SlottedOpamps-output.net    |    9 +
 .../tests/common/outputs/PCB/SlottedOpamps.retcode |    1 +
 .../common/outputs/PCB/TwoStageAmp-output.net      |   12 +
 .../tests/common/outputs/PCB/TwoStageAmp.retcode   |    1 +
 .../outputs/PCB/TwoStageAmp_Include-output.net     |   12 +
 .../common/outputs/PCB/TwoStageAmp_Include.retcode |    1 +
 .../common/outputs/PCB/TwoStageAmp_Sort-output.net |   12 +
 .../common/outputs/PCB/TwoStageAmp_Sort.retcode    |    1 +
 .../tests/common/outputs/PCB/cascade-output.net    |    7 +
 gnetlist/tests/common/outputs/PCB/cascade.retcode  |    1 +
 .../tests/common/outputs/PCB/multiequal-output.net |    2 +
 .../tests/common/outputs/PCB/multiequal.retcode    |    1 +
 .../tests/common/outputs/PCB/netattrib-output.net  |    5 +
 .../tests/common/outputs/PCB/netattrib.retcode     |    1 +
 .../outputs/PCB/powersupply-output.net}            |    0 
 .../tests/common/outputs/PCB/powersupply.retcode   |    1 +
 .../tests/common/outputs/PCB/singlenet-output.net  |    4 +
 .../tests/common/outputs/PCB/singlenet.retcode     |    1 +
 .../tests/common/outputs/PCBboard}/.gitignore      |    0 
 .../tests/common/outputs/PCBboard/JD-output.net    |   31 +
 gnetlist/tests/common/outputs/PCBboard/JD.retcode  |    1 +
 .../common/outputs/PCBboard/JD_Include-output.net  |   31 +
 .../common/outputs/PCBboard/JD_Include.retcode     |    1 +
 .../outputs/PCBboard/JD_Include_nomunge-output.net |   31 +
 .../outputs/PCBboard/JD_Include_nomunge.retcode    |    1 +
 .../common/outputs/PCBboard/JD_Sort-output.net     |   31 +
 .../tests/common/outputs/PCBboard/JD_Sort.retcode  |    1 +
 .../outputs/PCBboard/JD_Sort_nomunge-output.net    |   31 +
 .../outputs/PCBboard/JD_Sort_nomunge.retcode       |    1 +
 .../common/outputs/PCBboard/JD_nomunge-output.net  |   31 +
 gnetlist/tests/common/outputs/PCBboard/Makefile.am |   30 +
 .../outputs/PCBboard/SlottedOpamps-output.net      |   31 +
 .../common/outputs/PCBboard/SlottedOpamps.retcode  |    1 +
 .../common/outputs/PCBboard/TwoStageAmp-output.net |   31 +
 .../common/outputs/PCBboard/TwoStageAmp.retcode    |    1 +
 .../PCBboard/TwoStageAmp_Include-output.net        |   31 +
 .../outputs/PCBboard/TwoStageAmp_Include.retcode   |    1 +
 .../outputs/PCBboard/TwoStageAmp_Sort-output.net   |   31 +
 .../outputs/PCBboard/TwoStageAmp_Sort.retcode      |    1 +
 .../common/outputs/PCBboard/cascade-output.net     |   34 +
 .../tests/common/outputs/PCBboard/cascade.retcode  |    1 +
 .../common/outputs/PCBboard/multiequal-output.net  |   31 +
 .../common/outputs/PCBboard/multiequal.retcode     |    1 +
 .../common/outputs/PCBboard/netattrib-output.net   |   31 +
 .../common/outputs/PCBboard/netattrib.retcode      |    1 +
 .../common/outputs/PCBboard/powersupply-output.net |   31 +
 .../common/outputs/PCBboard/powersupply.retcode    |    1 +
 .../common/outputs/PCBboard/singlenet-output.net   |   71 +
 .../common/outputs/PCBboard/singlenet.retcode      |    1 +
 .../tests/common/outputs/allegro}/.gitignore       |    0 
 .../tests/common/outputs/allegro/JD-output.net     |   42 +
 gnetlist/tests/common/outputs/allegro/JD.retcode   |    1 +
 .../common/outputs/allegro/JD_Include-output.net   |   42 +
 .../common/outputs/allegro/JD_Include.retcode      |    1 +
 .../outputs/allegro/JD_Include_nomunge-output.net  |   42 +
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 .../outputs/allegro/JD_Sort_nomunge-output.net     |   42 +
 .../common/outputs/allegro/JD_Sort_nomunge.retcode |    1 +
 .../common/outputs/allegro/JD_nomunge-output.net   |   42 +
 gnetlist/tests/common/outputs/allegro/Makefile.am  |   30 +
 .../outputs/allegro/SlottedOpamps-output.net       |   17 +
 .../common/outputs/allegro/SlottedOpamps.retcode   |    1 +
 .../common/outputs/allegro/TwoStageAmp-output.net  |   69 +
 .../common/outputs/allegro/TwoStageAmp.retcode     |    1 +
 .../outputs/allegro/TwoStageAmp_Include-output.net |   69 +
 .../outputs/allegro/TwoStageAmp_Include.retcode    |    1 +
 .../outputs/allegro/TwoStageAmp_Sort-output.net    |   69 +
 .../outputs/allegro/TwoStageAmp_Sort.retcode       |    1 +
 .../common/outputs/allegro/cascade-output.net      |   25 +
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 .../common/outputs/allegro/multiequal.retcode      |    1 +
 .../common/outputs/allegro/netattrib-output.net    |   21 +
 .../tests/common/outputs/allegro/netattrib.retcode |    1 +
 .../outputs/allegro/powersupply-output.net}        |    0 
 .../common/outputs/allegro/powersupply.retcode     |    1 +
 .../common/outputs/allegro/singlenet-output.net    |   15 +
 .../tests/common/outputs/allegro/singlenet.retcode |    1 +
 .../tests/common/outputs/bae}/.gitignore           |    0 
 gnetlist/tests/common/outputs/bae/JD-output.net    |   21 +
 gnetlist/tests/common/outputs/bae/JD.retcode       |    1 +
 .../tests/common/outputs/bae/JD_Include-output.net |   21 +
 .../tests/common/outputs/bae/JD_Include.retcode    |    1 +
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 .../common/outputs/bae/JD_Include_nomunge.retcode  |    1 +
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 gnetlist/tests/common/outputs/bae/JD_Sort.retcode  |    1 +
 .../common/outputs/bae/JD_Sort_nomunge-output.net  |   21 +
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 .../tests/common/outputs/bae/JD_nomunge-output.net |   21 +
 gnetlist/tests/common/outputs/bae/Makefile.am      |   30 +
 .../common/outputs/bae/SlottedOpamps-output.net    |   14 +
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 .../common/outputs/bae/TwoStageAmp-output.net      |   39 +
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 .../tests/common/outputs/bae/cascade-output.net    |   19 +
 gnetlist/tests/common/outputs/bae/cascade.retcode  |    1 +
 .../tests/common/outputs/bae/multiequal-output.net |    9 +
 .../tests/common/outputs/bae/multiequal.retcode    |    1 +
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 .../tests/common/outputs/bae/powersupply.retcode   |    1 +
 .../tests/common/outputs/bae/singlenet-output.net  |    9 +
 .../tests/common/outputs/bae/singlenet.retcode     |    1 +
 .../tests/common/outputs/bom}/.gitignore           |    0 
 gnetlist/tests/common/outputs/bom/JD-output.net    |   12 +
 gnetlist/tests/common/outputs/bom/JD.retcode       |    1 +
 .../tests/common/outputs/bom/JD_Include-output.net |   12 +
 .../tests/common/outputs/bom/JD_Include.retcode    |    1 +
 .../outputs/bom/JD_Include_nomunge-output.net      |   12 +
 .../common/outputs/bom/JD_Include_nomunge.retcode  |    1 +
 .../tests/common/outputs/bom/JD_Sort-output.net    |   12 +
 gnetlist/tests/common/outputs/bom/JD_Sort.retcode  |    1 +
 .../common/outputs/bom/JD_Sort_nomunge-output.net  |   12 +
 .../common/outputs/bom/JD_Sort_nomunge.retcode     |    1 +
 .../tests/common/outputs/bom/JD_nomunge-output.net |   12 +
 gnetlist/tests/common/outputs/bom/Makefile.am      |   30 +
 .../common/outputs/bom/SlottedOpamps-output.net    |    2 +
 .../tests/common/outputs/bom/SlottedOpamps.retcode |    1 +
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 .../outputs/bom/TwoStageAmp_Include-output.net     |   24 +
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 .../common/outputs/bom/TwoStageAmp_Sort-output.net |   24 +
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 .../tests/common/outputs/bom/cascade-output.net    |    9 +
 gnetlist/tests/common/outputs/bom/cascade.retcode  |    1 +
 .../tests/common/outputs/bom/multiequal-output.net |    4 +
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 .../tests/common/outputs/bom2}/.gitignore          |    0 
 gnetlist/tests/common/outputs/bom2/JD-output.net   |   12 +
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 gnetlist/tests/common/outputs/calay/JD-output.net  |    6 +
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 gnetlist/tests/common/outputs/drc2/JD_Sort.retcode |    1 +
 .../outputs/drc2/JD_Sort_nomunge-output.net}       |    0 
 .../common/outputs/drc2/JD_Sort_nomunge.retcode    |    1 +
 .../outputs/drc2/JD_nomunge-output.net}            |    0 
 gnetlist/tests/common/outputs/drc2/Makefile.am     |   30 +
 .../common/outputs/drc2/SlottedOpamps-output.net   |   28 +
 .../common/outputs/drc2/SlottedOpamps.retcode      |    1 +
 .../outputs/drc2/TwoStageAmp-output.net}           |    2 +-
 .../tests/common/outputs/drc2/TwoStageAmp.retcode  |    1 +
 .../outputs/drc2/TwoStageAmp_Include-output.net}   |    2 +-
 .../outputs/drc2/TwoStageAmp_Include.retcode       |    1 +
 .../outputs/drc2/TwoStageAmp_Sort-output.net}      |    2 +-
 .../common/outputs/drc2/TwoStageAmp_Sort.retcode   |    1 +
 .../outputs/drc2/cascade-output.net}               |    4 +-
 gnetlist/tests/common/outputs/drc2/cascade.retcode |    1 +
 .../outputs/drc2/multiequal-output.net}            |    0 
 .../tests/common/outputs/drc2/multiequal.retcode   |    1 +
 .../tests/common/outputs/drc2/netattrib-output.net |   40 +
 .../tests/common/outputs/drc2/netattrib.retcode    |    1 +
 .../outputs/drc2/powersupply-output.net}           |    4 +-
 .../tests/common/outputs/drc2/powersupply.retcode  |    1 +
 .../outputs/drc2/singlenet-output.net}             |   13 +-
 .../tests/common/outputs/drc2/singlenet.retcode    |    1 +
 .../tests/common/outputs/eagle}/.gitignore         |    0 
 gnetlist/tests/common/outputs/eagle/JD-output.net  |   62 +
 gnetlist/tests/common/outputs/eagle/JD.retcode     |    1 +
 .../common/outputs/eagle/JD_Include-output.net     |   62 +
 .../tests/common/outputs/eagle/JD_Include.retcode  |    1 +
 .../outputs/eagle/JD_Include_nomunge-output.net    |   62 +
 .../outputs/eagle/JD_Include_nomunge.retcode       |    1 +
 .../tests/common/outputs/eagle/JD_Sort-output.net  |   62 +
 .../tests/common/outputs/eagle/JD_Sort.retcode     |    1 +
 .../outputs/eagle/JD_Sort_nomunge-output.net       |   62 +
 .../common/outputs/eagle/JD_Sort_nomunge.retcode   |    1 +
 .../common/outputs/eagle/JD_nomunge-output.net     |   62 +
 gnetlist/tests/common/outputs/eagle/Makefile.am    |   30 +
 .../common/outputs/eagle/SlottedOpamps-output.net  |   33 +
 .../common/outputs/eagle/SlottedOpamps.retcode     |    1 +
 .../common/outputs/eagle/TwoStageAmp-output.net    |  113 ++
 .../tests/common/outputs/eagle/TwoStageAmp.retcode |    1 +
 .../outputs/eagle/TwoStageAmp_Include-output.net   |  113 ++
 .../outputs/eagle/TwoStageAmp_Include.retcode      |    1 +
 .../outputs/eagle/TwoStageAmp_Sort-output.net      |  113 ++
 .../common/outputs/eagle/TwoStageAmp_Sort.retcode  |    1 +
 .../tests/common/outputs/eagle/cascade-output.net  |   44 +
 .../tests/common/outputs/eagle/cascade.retcode     |    1 +
 .../common/outputs/eagle/multiequal-output.net     |   15 +
 .../tests/common/outputs/eagle/multiequal.retcode  |    1 +
 .../common/outputs/eagle/netattrib-output.net      |   32 +
 .../tests/common/outputs/eagle/netattrib.retcode   |    1 +
 .../common/outputs/eagle/powersupply-output.net    |   78 ++
 .../tests/common/outputs/eagle/powersupply.retcode |    1 +
 .../common/outputs/eagle/singlenet-output.net      |   21 +
 .../tests/common/outputs/eagle/singlenet.retcode   |    1 +
 .../tests/common/outputs/futurenet2}/.gitignore    |    0 
 .../tests/common/outputs/futurenet2/JD-output.net  |   92 ++
 .../tests/common/outputs/futurenet2/JD.retcode     |    1 +
 .../outputs/futurenet2/JD_Include-output.net       |   92 ++
 .../common/outputs/futurenet2/JD_Include.retcode   |    1 +
 .../futurenet2/JD_Include_nomunge-output.net       |   92 ++
 .../outputs/futurenet2/JD_Include_nomunge.retcode  |    1 +
 .../common/outputs/futurenet2/JD_Sort-output.net   |   92 ++
 .../common/outputs/futurenet2/JD_Sort.retcode      |    1 +
 .../outputs/futurenet2/JD_Sort_nomunge-output.net  |   92 ++
 .../outputs/futurenet2/JD_Sort_nomunge.retcode     |    1 +
 .../outputs/futurenet2/JD_nomunge-output.net       |   92 ++
 .../tests/common/outputs/futurenet2/Makefile.am    |   30 +
 .../outputs/futurenet2/SlottedOpamps-output.net    |    0 
 .../outputs/futurenet2/SlottedOpamps.retcode       |    1 +
 .../outputs/futurenet2/TwoStageAmp-output.net      |  173 +++
 .../common/outputs/futurenet2/TwoStageAmp.retcode  |    1 +
 .../futurenet2/TwoStageAmp_Include-output.net      |  173 +++
 .../outputs/futurenet2/TwoStageAmp_Include.retcode |    1 +
 .../outputs/futurenet2/TwoStageAmp_Sort-output.net |  173 +++
 .../outputs/futurenet2/TwoStageAmp_Sort.retcode    |    1 +
 .../common/outputs/futurenet2/cascade-output.net   |   65 +
 .../common/outputs/futurenet2/cascade.retcode      |    1 +
 .../outputs/futurenet2/multiequal-output.net       |   25 +
 .../common/outputs/futurenet2/multiequal.retcode   |    1 +
 .../common/outputs/futurenet2/netattrib-output.net |   45 +
 .../common/outputs/futurenet2/netattrib.retcode    |    1 +
 .../outputs/futurenet2/powersupply-output.net      |  106 ++
 .../common/outputs/futurenet2/powersupply.retcode  |    1 +
 .../common/outputs/futurenet2/singlenet-output.net |   28 +
 .../common/outputs/futurenet2/singlenet.retcode    |    1 +
 .../tests/common/outputs/geda}/.gitignore          |    0 
 gnetlist/tests/common/outputs/geda/JD-output.net   |   39 +
 gnetlist/tests/common/outputs/geda/JD.retcode      |    1 +
 .../common/outputs/geda/JD_Include-output.net      |   39 +
 .../tests/common/outputs/geda/JD_Include.retcode   |    1 +
 .../outputs/geda/JD_Include_nomunge-output.net     |   39 +
 .../common/outputs/geda/JD_Include_nomunge.retcode |    1 +
 .../tests/common/outputs/geda/JD_Sort-output.net   |   39 +
 gnetlist/tests/common/outputs/geda/JD_Sort.retcode |    1 +
 .../common/outputs/geda/JD_Sort_nomunge-output.net |   39 +
 .../common/outputs/geda/JD_Sort_nomunge.retcode    |    1 +
 .../common/outputs/geda/JD_nomunge-output.net      |   39 +
 gnetlist/tests/common/outputs/geda/Makefile.am     |   30 +
 .../common/outputs/geda/SlottedOpamps-output.net   |   32 +
 .../common/outputs/geda/SlottedOpamps.retcode      |    1 +
 .../common/outputs/geda/TwoStageAmp-output.net     |   57 +
 .../tests/common/outputs/geda/TwoStageAmp.retcode  |    1 +
 .../outputs/geda/TwoStageAmp_Include-output.net    |   57 +
 .../outputs/geda/TwoStageAmp_Include.retcode       |    1 +
 .../outputs/geda/TwoStageAmp_Sort-output.net       |   57 +
 .../common/outputs/geda/TwoStageAmp_Sort.retcode   |    1 +
 .../tests/common/outputs/geda/cascade-output.net   |   37 +
 gnetlist/tests/common/outputs/geda/cascade.retcode |    1 +
 .../outputs/geda/multiequal-output.net}            |   10 +-
 .../tests/common/outputs/geda/multiequal.retcode   |    1 +
 .../outputs/geda/netattrib-output.net}             |    0 
 .../tests/common/outputs/geda/netattrib.retcode    |    1 +
 .../outputs/geda/powersupply-output.net}           |    0 
 .../tests/common/outputs/geda/powersupply.retcode  |    1 +
 .../outputs/geda/singlenet-output.net}             |    4 +-
 .../tests/common/outputs/geda/singlenet.retcode    |    1 +
 .../tests/common/outputs/gossip}/.gitignore        |    0 
 gnetlist/tests/common/outputs/gossip/JD-output.net |   19 +
 gnetlist/tests/common/outputs/gossip/JD.retcode    |    1 +
 .../common/outputs/gossip/JD_Include-output.net    |   19 +
 .../tests/common/outputs/gossip/JD_Include.retcode |    1 +
 .../outputs/gossip/JD_Include_nomunge-output.net   |   19 +
 .../outputs/gossip/JD_Include_nomunge.retcode      |    1 +
 .../tests/common/outputs/gossip/JD_Sort-output.net |   19 +
 .../tests/common/outputs/gossip/JD_Sort.retcode    |    1 +
 .../outputs/gossip/JD_Sort_nomunge-output.net      |   19 +
 .../common/outputs/gossip/JD_Sort_nomunge.retcode  |    1 +
 .../common/outputs/gossip/JD_nomunge-output.net    |   19 +
 gnetlist/tests/common/outputs/gossip/Makefile.am   |   30 +
 .../common/outputs/gossip/SlottedOpamps-output.net |    9 +
 .../common/outputs/gossip/SlottedOpamps.retcode    |    1 +
 .../common/outputs/gossip/TwoStageAmp-output.net   |   31 +
 .../common/outputs/gossip/TwoStageAmp.retcode      |    1 +
 .../outputs/gossip/TwoStageAmp_Include-output.net  |   31 +
 .../outputs/gossip/TwoStageAmp_Include.retcode     |    1 +
 .../outputs/gossip/TwoStageAmp_Sort-output.net     |   31 +
 .../common/outputs/gossip/TwoStageAmp_Sort.retcode |    1 +
 .../tests/common/outputs/gossip/cascade-output.net |   16 +
 .../tests/common/outputs/gossip/cascade.retcode    |    1 +
 .../common/outputs/gossip/multiequal-output.net    |   11 +
 .../tests/common/outputs/gossip/multiequal.retcode |    1 +
 .../common/outputs/gossip/netattrib-output.net     |   12 +
 .../tests/common/outputs/gossip/netattrib.retcode  |    1 +
 .../common/outputs/gossip/powersupply-output.net   |   20 +
 .../common/outputs/gossip/powersupply.retcode      |    1 +
 .../common/outputs/gossip/singlenet-output.net     |    9 +
 .../tests/common/outputs/gossip/singlenet.retcode  |    1 +
 .../tests/common/outputs/gsch2pcb}/.gitignore      |    0 
 .../tests/common/outputs/gsch2pcb/JD-output.net    |   42 +
 gnetlist/tests/common/outputs/gsch2pcb/JD.retcode  |    1 +
 .../common/outputs/gsch2pcb/JD_Include-output.net  |   42 +
 .../common/outputs/gsch2pcb/JD_Include.retcode     |    1 +
 .../outputs/gsch2pcb/JD_Include_nomunge-output.net |   42 +
 .../outputs/gsch2pcb/JD_Include_nomunge.retcode    |    1 +
 .../common/outputs/gsch2pcb/JD_Sort-output.net     |   42 +
 .../tests/common/outputs/gsch2pcb/JD_Sort.retcode  |    1 +
 .../outputs/gsch2pcb/JD_Sort_nomunge-output.net    |   42 +
 .../outputs/gsch2pcb/JD_Sort_nomunge.retcode       |    1 +
 .../common/outputs/gsch2pcb/JD_nomunge-output.net  |   42 +
 gnetlist/tests/common/outputs/gsch2pcb/Makefile.am |   30 +
 .../outputs/gsch2pcb/SlottedOpamps-output.net      |   32 +
 .../common/outputs/gsch2pcb/SlottedOpamps.retcode  |    1 +
 .../common/outputs/gsch2pcb/TwoStageAmp-output.net |   54 +
 .../common/outputs/gsch2pcb/TwoStageAmp.retcode    |    1 +
 .../gsch2pcb/TwoStageAmp_Include-output.net        |   54 +
 .../outputs/gsch2pcb/TwoStageAmp_Include.retcode   |    1 +
 .../outputs/gsch2pcb/TwoStageAmp_Sort-output.net   |   54 +
 .../outputs/gsch2pcb/TwoStageAmp_Sort.retcode      |    1 +
 .../common/outputs/gsch2pcb/cascade-output.net     |   39 +
 .../tests/common/outputs/gsch2pcb/cascade.retcode  |    1 +
 .../common/outputs/gsch2pcb/multiequal-output.net  |   34 +
 .../common/outputs/gsch2pcb/multiequal.retcode     |    1 +
 .../common/outputs/gsch2pcb/netattrib-output.net   |   35 +
 .../common/outputs/gsch2pcb/netattrib.retcode      |    1 +
 .../common/outputs/gsch2pcb/powersupply-output.net |   43 +
 .../common/outputs/gsch2pcb/powersupply.retcode    |    1 +
 .../common/outputs/gsch2pcb/singlenet-output.net   |   32 +
 .../common/outputs/gsch2pcb/singlenet.retcode      |    1 +
 .../tests/common/outputs/mathematica}/.gitignore   |    0 
 .../tests/common/outputs/mathematica/JD-output.net |   78 ++
 .../tests/common/outputs/mathematica/JD.retcode    |    1 +
 .../outputs/mathematica/JD_Include-output.net      |   78 ++
 .../common/outputs/mathematica/JD_Include.retcode  |    1 +
 .../mathematica/JD_Include_nomunge-output.net      |   78 ++
 .../outputs/mathematica/JD_Include_nomunge.retcode |    1 +
 .../common/outputs/mathematica/JD_Sort-output.net  |   78 ++
 .../common/outputs/mathematica/JD_Sort.retcode     |    1 +
 .../outputs/mathematica/JD_Sort_nomunge-output.net |   78 ++
 .../outputs/mathematica/JD_Sort_nomunge.retcode    |    1 +
 .../outputs/mathematica/JD_nomunge-output.net      |   78 ++
 .../tests/common/outputs/mathematica/Makefile.am   |   30 +
 .../outputs/mathematica/SlottedOpamps-output.net   |   46 +
 .../outputs/mathematica/SlottedOpamps.retcode      |    1 +
 .../outputs/mathematica/TwoStageAmp-output.net     |  132 ++
 .../common/outputs/mathematica/TwoStageAmp.retcode |    1 +
 .../mathematica/TwoStageAmp_Include-output.net     |  132 ++
 .../mathematica/TwoStageAmp_Include.retcode        |    1 +
 .../mathematica/TwoStageAmp_Sort-output.net        |  132 ++
 .../outputs/mathematica/TwoStageAmp_Sort.retcode   |    1 +
 .../common/outputs/mathematica/cascade-output.net  |   49 +
 .../common/outputs/mathematica/cascade.retcode     |    1 +
 .../outputs/mathematica/multiequal-output.net      |   16 +
 .../common/outputs/mathematica/multiequal.retcode  |    1 +
 .../outputs/mathematica/netattrib-output.net       |   41 +
 .../common/outputs/mathematica/netattrib.retcode   |    1 +
 .../outputs/mathematica/powersupply-output.net     |   97 ++
 .../common/outputs/mathematica/powersupply.retcode |    1 +
 .../outputs/mathematica/singlenet-output.net       |   30 +
 .../common/outputs/mathematica/singlenet.retcode   |    1 +
 .../tests/common/outputs/maxascii}/.gitignore      |    0 
 .../tests/common/outputs/maxascii/JD-output.net    |   27 +
 gnetlist/tests/common/outputs/maxascii/JD.retcode  |    1 +
 .../common/outputs/maxascii/JD_Include-output.net  |   27 +
 .../common/outputs/maxascii/JD_Include.retcode     |    1 +
 .../outputs/maxascii/JD_Include_nomunge-output.net |   27 +
 .../outputs/maxascii/JD_Include_nomunge.retcode    |    1 +
 .../common/outputs/maxascii/JD_Sort-output.net     |   27 +
 .../tests/common/outputs/maxascii/JD_Sort.retcode  |    1 +
 .../outputs/maxascii/JD_Sort_nomunge-output.net    |   27 +
 .../outputs/maxascii/JD_Sort_nomunge.retcode       |    1 +
 .../common/outputs/maxascii/JD_nomunge-output.net  |   27 +
 gnetlist/tests/common/outputs/maxascii/Makefile.am |   30 +
 .../outputs/maxascii/SlottedOpamps-output.net      |   23 +
 .../common/outputs/maxascii/SlottedOpamps.retcode  |    1 +
 .../common/outputs/maxascii/TwoStageAmp-output.net |   51 +
 .../common/outputs/maxascii/TwoStageAmp.retcode    |    1 +
 .../maxascii/TwoStageAmp_Include-output.net        |   51 +
 .../outputs/maxascii/TwoStageAmp_Include.retcode   |    1 +
 .../outputs/maxascii/TwoStageAmp_Sort-output.net   |   51 +
 .../outputs/maxascii/TwoStageAmp_Sort.retcode      |    1 +
 .../common/outputs/maxascii/cascade-output.net     |   26 +
 .../tests/common/outputs/maxascii/cascade.retcode  |    1 +
 .../common/outputs/maxascii/multiequal-output.net  |   11 +
 .../common/outputs/maxascii/multiequal.retcode     |    1 +
 .../common/outputs/maxascii/netattrib-output.net   |   18 +
 .../common/outputs/maxascii/netattrib.retcode      |    1 +
 .../outputs/maxascii/powersupply-output.net}       |    0 
 .../common/outputs/maxascii/powersupply.retcode    |    1 +
 .../common/outputs/maxascii/singlenet-output.net   |   13 +
 .../common/outputs/maxascii/singlenet.retcode      |    1 +
 .../tests/common/outputs/osmond}/.gitignore        |    0 
 gnetlist/tests/common/outputs/osmond/JD-output.net |   23 +
 gnetlist/tests/common/outputs/osmond/JD.retcode    |    1 +
 .../common/outputs/osmond/JD_Include-output.net    |   23 +
 .../tests/common/outputs/osmond/JD_Include.retcode |    1 +
 .../outputs/osmond/JD_Include_nomunge-output.net   |   23 +
 .../outputs/osmond/JD_Include_nomunge.retcode      |    1 +
 .../tests/common/outputs/osmond/JD_Sort-output.net |   23 +
 .../tests/common/outputs/osmond/JD_Sort.retcode    |    1 +
 .../outputs/osmond/JD_Sort_nomunge-output.net      |   23 +
 .../common/outputs/osmond/JD_Sort_nomunge.retcode  |    1 +
 .../common/outputs/osmond/JD_nomunge-output.net    |   23 +
 gnetlist/tests/common/outputs/osmond/Makefile.am   |   30 +
 .../common/outputs/osmond/SlottedOpamps-output.net |   19 +
 .../common/outputs/osmond/SlottedOpamps.retcode    |    1 +
 .../common/outputs/osmond/TwoStageAmp-output.net   |   47 +
 .../common/outputs/osmond/TwoStageAmp.retcode      |    1 +
 .../outputs/osmond/TwoStageAmp_Include-output.net  |   47 +
 .../outputs/osmond/TwoStageAmp_Include.retcode     |    1 +
 .../outputs/osmond/TwoStageAmp_Sort-output.net     |   47 +
 .../common/outputs/osmond/TwoStageAmp_Sort.retcode |    1 +
 .../tests/common/outputs/osmond/cascade-output.net |   22 +
 .../tests/common/outputs/osmond/cascade.retcode    |    1 +
 .../common/outputs/osmond/multiequal-output.net    |    7 +
 .../tests/common/outputs/osmond/multiequal.retcode |    1 +
 .../common/outputs/osmond/netattrib-output.net     |   14 +
 .../tests/common/outputs/osmond/netattrib.retcode  |    1 +
 .../common/outputs/osmond/powersupply-output.net   |   34 +
 .../common/outputs/osmond/powersupply.retcode      |    1 +
 .../common/outputs/osmond/singlenet-output.net     |    9 +
 .../tests/common/outputs/osmond/singlenet.retcode  |    1 +
 .../tests/common/outputs/pads}/.gitignore          |    0 
 gnetlist/tests/common/outputs/pads/JD-output.net   |   30 +
 gnetlist/tests/common/outputs/pads/JD.retcode      |    1 +
 .../common/outputs/pads/JD_Include-output.net      |   30 +
 .../tests/common/outputs/pads/JD_Include.retcode   |    1 +
 .../outputs/pads/JD_Include_nomunge-output.net     |   30 +
 .../common/outputs/pads/JD_Include_nomunge.retcode |    1 +
 .../tests/common/outputs/pads/JD_Sort-output.net   |   30 +
 gnetlist/tests/common/outputs/pads/JD_Sort.retcode |    1 +
 .../common/outputs/pads/JD_Sort_nomunge-output.net |   30 +
 .../common/outputs/pads/JD_Sort_nomunge.retcode    |    1 +
 .../common/outputs/pads/JD_nomunge-output.net      |   30 +
 gnetlist/tests/common/outputs/pads/Makefile.am     |   30 +
 .../common/outputs/pads/SlottedOpamps-output.net   |   26 +
 .../common/outputs/pads/SlottedOpamps.retcode      |    1 +
 .../common/outputs/pads/TwoStageAmp-output.net     |   54 +
 .../tests/common/outputs/pads/TwoStageAmp.retcode  |    1 +
 .../outputs/pads/TwoStageAmp_Include-output.net    |   54 +
 .../outputs/pads/TwoStageAmp_Include.retcode       |    1 +
 .../outputs/pads/TwoStageAmp_Sort-output.net       |   54 +
 .../common/outputs/pads/TwoStageAmp_Sort.retcode   |    1 +
 .../tests/common/outputs/pads/cascade-output.net   |   29 +
 gnetlist/tests/common/outputs/pads/cascade.retcode |    1 +
 .../common/outputs/pads/multiequal-output.net      |   14 +
 .../tests/common/outputs/pads/multiequal.retcode   |    1 +
 .../tests/common/outputs/pads/netattrib-output.net |   21 +
 .../tests/common/outputs/pads/netattrib.retcode    |    1 +
 .../outputs/pads/powersupply-output.net}           |    0 
 .../tests/common/outputs/pads/powersupply.retcode  |    1 +
 .../outputs/pads/singlenet-output.net}             |    4 +-
 .../tests/common/outputs/pads/singlenet.retcode    |    1 +
 .../tests/common/outputs/partslist1}/.gitignore    |    0 
 .../tests/common/outputs/partslist1/JD-output.net  |   14 +
 .../tests/common/outputs/partslist1/JD.retcode     |    1 +
 .../outputs/partslist1/JD_Include-output.net       |   14 +
 .../common/outputs/partslist1/JD_Include.retcode   |    1 +
 .../partslist1/JD_Include_nomunge-output.net       |   14 +
 .../outputs/partslist1/JD_Include_nomunge.retcode  |    1 +
 .../common/outputs/partslist1/JD_Sort-output.net   |   14 +
 .../common/outputs/partslist1/JD_Sort.retcode      |    1 +
 .../outputs/partslist1/JD_Sort_nomunge-output.net  |   14 +
 .../outputs/partslist1/JD_Sort_nomunge.retcode     |    1 +
 .../outputs/partslist1/JD_nomunge-output.net       |   14 +
 .../tests/common/outputs/partslist1/Makefile.am    |   30 +
 .../outputs/partslist1/SlottedOpamps-output.net    |    4 +
 .../outputs/partslist1/SlottedOpamps.retcode       |    1 +
 .../outputs/partslist1/TwoStageAmp-output.net      |   25 +
 .../common/outputs/partslist1/TwoStageAmp.retcode  |    1 +
 .../partslist1/TwoStageAmp_Include-output.net      |   25 +
 .../outputs/partslist1/TwoStageAmp_Include.retcode |    1 +
 .../outputs/partslist1/TwoStageAmp_Sort-output.net |   25 +
 .../outputs/partslist1/TwoStageAmp_Sort.retcode    |    1 +
 .../common/outputs/partslist1/cascade-output.net   |   11 +
 .../common/outputs/partslist1/cascade.retcode      |    1 +
 .../outputs/partslist1/multiequal-output.net       |    6 +
 .../common/outputs/partslist1/multiequal.retcode   |    1 +
 .../common/outputs/partslist1/netattrib-output.net |    7 +
 .../common/outputs/partslist1/netattrib.retcode    |    1 +
 .../outputs/partslist1/powersupply-output.net      |   15 +
 .../common/outputs/partslist1/powersupply.retcode  |    1 +
 .../common/outputs/partslist1/singlenet-output.net |    4 +
 .../common/outputs/partslist1/singlenet.retcode    |    1 +
 .../tests/common/outputs/partslist2}/.gitignore    |    0 
 .../tests/common/outputs/partslist2/JD-output.net  |   14 +
 .../tests/common/outputs/partslist2/JD.retcode     |    1 +
 .../outputs/partslist2/JD_Include-output.net       |   14 +
 .../common/outputs/partslist2/JD_Include.retcode   |    1 +
 .../partslist2/JD_Include_nomunge-output.net       |   14 +
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 .../common/outputs/pcbpins/TwoStageAmp-output.net  |   89 ++
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 gnetlist/tests/common/outputs/protelII/Makefile.am |   30 +
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 .../common/outputs/protelII/TwoStageAmp.retcode    |    1 +
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 .../tests/common/outputs/switcap}/.gitignore       |    0 
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 .../common/outputs/switcap/JD_Sort_nomunge.retcode |    1 +
 .../common/outputs/switcap/JD_nomunge-output.net   |   15 +
 gnetlist/tests/common/outputs/switcap/Makefile.am  |   30 +
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 .../outputs/switcap/TwoStageAmp_Include-output.net |   15 +
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 gnetlist/tests/common/outputs/tango/JD-output.net  |  122 ++
 gnetlist/tests/common/outputs/tango/JD.retcode     |    1 +
 .../common/outputs/tango/JD_Include-output.net     |  122 ++
 .../tests/common/outputs/tango/JD_Include.retcode  |    1 +
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 .../common/outputs/tango/JD_Sort_nomunge.retcode   |    1 +
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 gnetlist/tests/common/outputs/tango/Makefile.am    |   30 +
 .../common/outputs/tango/SlottedOpamps-output.net  |   46 +
 .../common/outputs/tango/SlottedOpamps.retcode     |    1 +
 .../common/outputs/tango/TwoStageAmp-output.net    |  239 ++++
 .../tests/common/outputs/tango/TwoStageAmp.retcode |    1 +
 .../outputs/tango/TwoStageAmp_Include-output.net   |  239 ++++
 .../outputs/tango/TwoStageAmp_Include.retcode      |    1 +
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 .../common/outputs/tango/TwoStageAmp_Sort.retcode  |    1 +
 .../tests/common/outputs/tango/cascade-output.net  |   90 ++
 .../tests/common/outputs/tango/cascade.retcode     |    1 +
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 .../tests/common/outputs/tango/multiequal.retcode  |    1 +
 .../common/outputs/tango/netattrib-output.net      |   56 +
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 .../tests/common/outputs/tango/singlenet.retcode   |    1 +
 .../tests/common/outputs/vams}/.gitignore          |    0 
 gnetlist/tests/common/outputs/vams/JD-output.net   |   94 ++
 gnetlist/tests/common/outputs/vams/JD.retcode      |    1 +
 .../common/outputs/vams/JD_Include-output.net      |   94 ++
 .../tests/common/outputs/vams/JD_Include.retcode   |    1 +
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 .../common/outputs/vams/JD_Include_nomunge.retcode |    1 +
 .../tests/common/outputs/vams/JD_Sort-output.net   |   94 ++
 gnetlist/tests/common/outputs/vams/JD_Sort.retcode |    1 +
 .../common/outputs/vams/JD_Sort_nomunge-output.net |   94 ++
 .../common/outputs/vams/JD_Sort_nomunge.retcode    |    1 +
 .../common/outputs/vams/JD_nomunge-output.net      |   94 ++
 gnetlist/tests/common/outputs/vams/Makefile.am     |   30 +
 .../common/outputs/vams/SlottedOpamps-output.net   |   33 +
 .../common/outputs/vams/SlottedOpamps.retcode      |    1 +
 .../common/outputs/vams/TwoStageAmp-output.net     |  187 +++
 .../tests/common/outputs/vams/TwoStageAmp.retcode  |    1 +
 .../outputs/vams/TwoStageAmp_Include-output.net    |  187 +++
 .../outputs/vams/TwoStageAmp_Include.retcode       |    1 +
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 .../common/outputs/vams/TwoStageAmp_Sort.retcode   |    1 +
 .../tests/common/outputs/vams/cascade-output.net   |   91 ++
 gnetlist/tests/common/outputs/vams/cascade.retcode |    1 +
 .../common/outputs/vams/multiequal-output.net      |   26 +
 .../tests/common/outputs/vams/multiequal.retcode   |    1 +
 .../tests/common/outputs/vams/netattrib-output.net |   38 +
 .../tests/common/outputs/vams/netattrib.retcode    |    1 +
 .../common/outputs/vams/powersupply-output.net     |   85 ++
 .../tests/common/outputs/vams/powersupply.retcode  |    1 +
 .../tests/common/outputs/vams/singlenet-output.net |   30 +
 .../tests/common/outputs/vams/singlenet.retcode    |    1 +
 .../tests/common/outputs/verilog}/.gitignore       |    0 
 .../tests/common/outputs/verilog/JD-output.net     |   87 ++
 gnetlist/tests/common/outputs/verilog/JD.retcode   |    1 +
 .../common/outputs/verilog/JD_Include-output.net   |   87 ++
 .../common/outputs/verilog/JD_Include.retcode      |    1 +
 .../outputs/verilog/JD_Include_nomunge-output.net  |   87 ++
 .../outputs/verilog/JD_Include_nomunge.retcode     |    1 +
 .../common/outputs/verilog/JD_Sort-output.net      |   87 ++
 .../tests/common/outputs/verilog/JD_Sort.retcode   |    1 +
 .../outputs/verilog/JD_Sort_nomunge-output.net     |   87 ++
 .../common/outputs/verilog/JD_Sort_nomunge.retcode |    1 +
 .../common/outputs/verilog/JD_nomunge-output.net   |   87 ++
 gnetlist/tests/common/outputs/verilog/Makefile.am  |   30 +
 .../outputs/verilog/SlottedOpamps-output.net       |   46 +
 .../common/outputs/verilog/SlottedOpamps.retcode   |    1 +
 .../common/outputs/verilog/TwoStageAmp-output.net  |  142 ++
 .../common/outputs/verilog/TwoStageAmp.retcode     |    1 +
 .../outputs/verilog/TwoStageAmp_Include-output.net |  142 ++
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 .../run_tests.sh => common/run_backend_tests.sh}   |   79 +-
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=================
 Commit Messages
=================

commit aaa1abbcfac8e67901c5b2a279e0a13f88d774b0
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 18:04:40 2008 +0100

    Tolerated changes in golden files for the vipec netlist backend.
    
    The way slotted parts are handled has changed since 1.2.0, as
    has the output of the vipec backend for slotted parts. Since
    this backend isn't likely to care about slotted parts, we allow
    these output changes as harmless.

:100644 100644 fbf59df... 663c0e3... M	gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
:100644 100644 0da0f66... 53b7251... M	gnetlist/tests/common/outputs/vipec/singlenet-output.net

commit ae9d82b1fdcd14acde5cbf4d54718ef3566aec80
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 18:03:50 2008 +0100

    Desired changes in golden file output for spice-sdb
    
    Slotted parts are now handled correctly. Was partly broken in 1.2.0.

:100644 100644 391b789... e571f05... M	gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
:100644 100644 895c7bb... 775b16e... M	gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
:100644 100644 966f3f2... 21adb89... M	gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net

commit 850a80faa3038f688ef3630aff61a05c64904abc
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:48:57 2008 +0100

    Update pads backend golden files to match the new \r\n line ends.
    
    The \r\n line end change was made after 1.2.0, so we need to update.

:100644 100644 c4fc30c... f3a5213... M	gnetlist/tests/common/outputs/pads/JD-output.net
:100644 100644 c4fc30c... f3a5213... M	gnetlist/tests/common/outputs/pads/JD_Include-output.net
:100644 100644 c4fc30c... f3a5213... M	gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
:100644 100644 c4fc30c... f3a5213... M	gnetlist/tests/common/outputs/pads/JD_Sort-output.net
:100644 100644 c4fc30c... f3a5213... M	gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
:100644 100644 ec0991e... 2031be3... M	gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
:100644 100644 0295af5... f443d47... M	gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
:100644 100644 0295af5... f443d47... M	gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
:100644 100644 0295af5... f443d47... M	gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
:100644 100644 2643962... 52c4cd5... M	gnetlist/tests/common/outputs/pads/cascade-output.net
:100644 100644 557fc85... d325973... M	gnetlist/tests/common/outputs/pads/multiequal-output.net
:100644 100644 71d95b1... 332cf53... M	gnetlist/tests/common/outputs/pads/netattrib-output.net
:100644 100644 5200ae8... 3aa5cd9... M	gnetlist/tests/common/outputs/pads/powersupply-output.net
:100644 100644 a0bfde7... db44a14... M	gnetlist/tests/common/outputs/pads/singlenet-output.net

commit 345cd09f3517380a466a3254b1f6dc16ef2ce896
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:47:49 2008 +0100

    Remove the spice-sdb backend specific directory of gnetlist tests.
    
    They are now covered for all backends in the "common" tests directory.

:100644 100644 0fbdb9b... 4009073... M	gnetlist/configure.ac
:100644 100644 1f4b468... b232426... M	gnetlist/tests/Makefile.am
:100644 000000 23c1897... 0000000... D	gnetlist/tests/spice-sdb/.gitignore
:100644 000000 ab5a457... 0000000... D	gnetlist/tests/spice-sdb/Makefile.am
:100644 000000 23c1897... 0000000... D	gnetlist/tests/spice-sdb/inputs/.gitignore
:100644 000000 419a0e6... 0000000... D	gnetlist/tests/spice-sdb/inputs/LVDfoo.sch
:100644 000000 d91dd00... 0000000... D	gnetlist/tests/spice-sdb/inputs/Makefile.am
:100644 000000 8e6e522... 0000000... D	gnetlist/tests/spice-sdb/inputs/Simulation.cmd
:100644 000000 3eeaf01... 0000000... D	gnetlist/tests/spice-sdb/inputs/SlottedOpamps.sch
:100644 000000 473a990... 0000000... D	gnetlist/tests/spice-sdb/inputs/TwoStageAmp.sch
:100644 000000 7408ef0... 0000000... D	gnetlist/tests/spice-sdb/inputs/gafrc
:100644 000000 23c1897... 0000000... D	gnetlist/tests/spice-sdb/inputs/models/.gitignore
:100644 000000 f8d0e80... 0000000... D	gnetlist/tests/spice-sdb/inputs/models/2N3904.mod
:100644 000000 4630408... 0000000... D	gnetlist/tests/spice-sdb/inputs/models/Makefile.am
:100644 000000 26bf372... 0000000... D	gnetlist/tests/spice-sdb/inputs/models/openIP_5.cir
:100644 000000 23c1897... 0000000... D	gnetlist/tests/spice-sdb/inputs/sym/.gitignore
:100644 000000 1707dad... 0000000... D	gnetlist/tests/spice-sdb/inputs/sym/LM324_slotted-1.sym
:100644 000000 6ab69da... 0000000... D	gnetlist/tests/spice-sdb/inputs/sym/LVD.sym
:100644 000000 76adbcf... 0000000... D	gnetlist/tests/spice-sdb/inputs/sym/Makefile.am
:100644 000000 65492d4... 0000000... D	gnetlist/tests/spice-sdb/inputs/sym/transistor.sym
:100644 000000 23c1897... 0000000... D	gnetlist/tests/spice-sdb/outputs/.gitignore
:100644 000000 e1bb285... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD-output.net
:100644 000000 647fbff... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Include-output.net
:100644 000000 eec3dd1... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge-output.net
:100644 000000 5d34df1... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge_longopt-output.net
:100644 000000 d715184... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Sort-output.net
:100644 000000 ce92fdf... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge-output.net
:100644 000000 6dceec6... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge_longopt-output.net
:100644 000000 e1bb285... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_nomunge-output.net
:100644 000000 9c1c1d8... 0000000... D	gnetlist/tests/spice-sdb/outputs/JD_nomunge_longopt-output.net
:100644 000000 cb9d0cf... 0000000... D	gnetlist/tests/spice-sdb/outputs/Makefile.am
:100644 000000 e571f05... 0000000... D	gnetlist/tests/spice-sdb/outputs/SlottedOpamps-output.net
:100644 000000 3fa5a97... 0000000... D	gnetlist/tests/spice-sdb/outputs/TwoStageAmp-output.net
:100644 000000 6b45461... 0000000... D	gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include-output.net
:100644 000000 6d70b90... 0000000... D	gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include_longopt-output.net
:100644 000000 ed893be... 0000000... D	gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort-output.net
:100644 000000 69a928e... 0000000... D	gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort_longopt-output.net
:100755 000000 fe10f64... 0000000... D	gnetlist/tests/spice-sdb/run_tests.sh
:100644 000000 dfc9d69... 0000000... D	gnetlist/tests/spice-sdb/tests.list

commit 8a0e4e649e0aab8820fcca32214f99322788bc31
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:43:08 2008 +0100

    Commit golden files from netlist backends as produced by gEDA 1.2.0
    
    We want to track changes in netlist backend behaviour since version 1.2.0,
    as changes in slotted part handling since then have caused unintended
    differences in outputs for some backends. We can explicitly confirm
    thoses changes as desired or tolerable by checking in new golden files.

:100644 100644 573541a... d00491f... M	gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
:100644 100644 573541a... d00491f... M	gnetlist/tests/common/outputs/drc2/cascade.retcode
:100644 100644 573541a... d00491f... M	gnetlist/tests/common/outputs/drc2/netattrib.retcode
:100644 100644 573541a... d00491f... M	gnetlist/tests/common/outputs/drc2/powersupply.retcode
:100644 100644 573541a... d00491f... M	gnetlist/tests/common/outputs/drc2/singlenet.retcode
:100644 100644 f3a5213... c4fc30c... M	gnetlist/tests/common/outputs/pads/JD-output.net
:100644 100644 f3a5213... c4fc30c... M	gnetlist/tests/common/outputs/pads/JD_Include-output.net
:100644 100644 f3a5213... c4fc30c... M	gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
:100644 100644 f3a5213... c4fc30c... M	gnetlist/tests/common/outputs/pads/JD_Sort-output.net
:100644 100644 f3a5213... c4fc30c... M	gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
:100644 100644 2031be3... ec0991e... M	gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
:100644 100644 f443d47... 0295af5... M	gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
:100644 100644 f443d47... 0295af5... M	gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
:100644 100644 f443d47... 0295af5... M	gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
:100644 100644 52c4cd5... 2643962... M	gnetlist/tests/common/outputs/pads/cascade-output.net
:100644 100644 d325973... 557fc85... M	gnetlist/tests/common/outputs/pads/multiequal-output.net
:100644 100644 332cf53... 71d95b1... M	gnetlist/tests/common/outputs/pads/netattrib-output.net
:100644 100644 3aa5cd9... 5200ae8... M	gnetlist/tests/common/outputs/pads/powersupply-output.net
:100644 100644 db44a14... a0bfde7... M	gnetlist/tests/common/outputs/pads/singlenet-output.net
:100644 100644 e571f05... 391b789... M	gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
:100644 100644 775b16e... 895c7bb... M	gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
:100644 100644 21adb89... 966f3f2... M	gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
:100644 100644 c73d322... a5f6fdb... M	gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
:100644 100644 4667f91... b19effc... M	gnetlist/tests/common/outputs/spice/singlenet-output.net
:100644 100644 663c0e3... fbf59df... M	gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
:100644 100644 53b7251... 0da0f66... M	gnetlist/tests/common/outputs/vipec/singlenet-output.net

commit dc5a2e6b352ac4e5833ec86c0685da747362e04a
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Wed Feb 13 16:47:40 2008 +0000

    Add a common set of tests to gnetlist evolved from the spice-sdb tests.
    
    The tests are applied to all backends, with control files being used to
    document the expected return codes, and golden files with the expected
    output. These files are generated from a 1.5.0 development release of
    of the gEDA suite, and do not in all cases represent "correct" behaviour,
    merely "gEDA 1.5.0" behaviour.

:100644 100644 c03a1d0... 0fbdb9b... M	gnetlist/configure.ac
:100644 100644 682ac99... 1f4b468... M	gnetlist/tests/Makefile.am
:000000 100644 0000000... af1e4c0... A	gnetlist/tests/common/.gitignore
:000000 100644 0000000... 161a210... A	gnetlist/tests/common/Makefile.am
:000000 100644 0000000... aee1abb... A	gnetlist/tests/common/always-copy.list
:000000 100644 0000000... 780f618... A	gnetlist/tests/common/backends.list
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/inputs/.gitignore
:000000 100644 0000000... 419a0e6... A	gnetlist/tests/common/inputs/LVDfoo.sch
:000000 100644 0000000... 8add101... A	gnetlist/tests/common/inputs/Makefile.am
:000000 100644 0000000... 8e6e522... A	gnetlist/tests/common/inputs/Simulation.cmd
:000000 100644 0000000... 3eeaf01... A	gnetlist/tests/common/inputs/SlottedOpamps.sch
:000000 100644 0000000... 473a990... A	gnetlist/tests/common/inputs/TwoStageAmp.sch
:000000 100644 0000000... 12527f4... A	gnetlist/tests/common/inputs/attribs
:000000 100644 0000000... 8d91db9... A	gnetlist/tests/common/inputs/cascade.sch
:000000 100644 0000000... 7408ef0... A	gnetlist/tests/common/inputs/gafrc
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/inputs/models/.gitignore
:000000 100644 0000000... f8d0e80... A	gnetlist/tests/common/inputs/models/2N3904.mod
:000000 100644 0000000... 4630408... A	gnetlist/tests/common/inputs/models/Makefile.am
:000000 100644 0000000... 26bf372... A	gnetlist/tests/common/inputs/models/openIP_5.cir
:000000 100644 0000000... f724ba4... A	gnetlist/tests/common/inputs/multiequal.sch
:000000 100644 0000000... 2c56e7b... A	gnetlist/tests/common/inputs/netattrib.sch
:000000 100644 0000000... 4f378a6... A	gnetlist/tests/common/inputs/powersupply.sch
:000000 100644 0000000... 5a60f73... A	gnetlist/tests/common/inputs/singlenet.sch
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/inputs/sym/.gitignore
:000000 100644 0000000... 1707dad... A	gnetlist/tests/common/inputs/sym/LM324_slotted-1.sym
:000000 100644 0000000... 6ab69da... A	gnetlist/tests/common/inputs/sym/LVD.sym
:000000 100644 0000000... 76adbcf... A	gnetlist/tests/common/inputs/sym/Makefile.am
:000000 100644 0000000... 65492d4... A	gnetlist/tests/common/inputs/sym/transistor.sym
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/.gitignore
:000000 100644 0000000... d2f9934... A	gnetlist/tests/common/outputs/Makefile.am
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/PCB/.gitignore
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/JD.retcode
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/JD_Include.retcode
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD_Include_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/JD_Include_nomunge.retcode
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/JD_Sort.retcode
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge.retcode
:000000 100644 0000000... 4f7f45d... A	gnetlist/tests/common/outputs/PCB/JD_nomunge-output.net
:000000 100644 0000000... bf3dd39... A	gnetlist/tests/common/outputs/PCB/Makefile.am
:000000 100644 0000000... ec5b7ed... A	gnetlist/tests/common/outputs/PCB/SlottedOpamps-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/SlottedOpamps.retcode
:000000 100644 0000000... e45cdbe... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp.retcode
:000000 100644 0000000... e45cdbe... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include.retcode
:000000 100644 0000000... e45cdbe... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort.retcode
:000000 100644 0000000... 68cf477... A	gnetlist/tests/common/outputs/PCB/cascade-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/cascade.retcode
:000000 100644 0000000... 882aee9... A	gnetlist/tests/common/outputs/PCB/multiequal-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/multiequal.retcode
:000000 100644 0000000... bdaacfa... A	gnetlist/tests/common/outputs/PCB/netattrib-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/netattrib.retcode
:000000 100644 0000000... ee5267d... A	gnetlist/tests/common/outputs/PCB/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/powersupply.retcode
:000000 100644 0000000... 3052c13... A	gnetlist/tests/common/outputs/PCB/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCB/singlenet.retcode
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/PCBboard/.gitignore
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/JD.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/JD_Include.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/JD_Sort.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/JD_nomunge-output.net
:000000 100644 0000000... bf3dd39... A	gnetlist/tests/common/outputs/PCBboard/Makefile.am
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/SlottedOpamps-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/SlottedOpamps.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort.retcode
:000000 100644 0000000... 65641ae... A	gnetlist/tests/common/outputs/PCBboard/cascade-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/cascade.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/multiequal-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/multiequal.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/netattrib-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/netattrib.retcode
:000000 100644 0000000... 54f4a0b... A	gnetlist/tests/common/outputs/PCBboard/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/powersupply.retcode
:000000 100644 0000000... 4081b3d... A	gnetlist/tests/common/outputs/PCBboard/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/PCBboard/singlenet.retcode
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/allegro/.gitignore
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/JD.retcode
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/JD_Include.retcode
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/JD_Include_nomunge.retcode
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/JD_Sort.retcode
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge.retcode
:000000 100644 0000000... 5492bf8... A	gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
:000000 100644 0000000... bf3dd39... A	gnetlist/tests/common/outputs/allegro/Makefile.am
:000000 100644 0000000... e83277e... A	gnetlist/tests/common/outputs/allegro/SlottedOpamps-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/SlottedOpamps.retcode
:000000 100644 0000000... d48fc78... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp.retcode
:000000 100644 0000000... d48fc78... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include.retcode
:000000 100644 0000000... d48fc78... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort.retcode
:000000 100644 0000000... 9ad1608... A	gnetlist/tests/common/outputs/allegro/cascade-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/cascade.retcode
:000000 100644 0000000... f59daf7... A	gnetlist/tests/common/outputs/allegro/multiequal-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/multiequal.retcode
:000000 100644 0000000... ac3f34a... A	gnetlist/tests/common/outputs/allegro/netattrib-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/netattrib.retcode
:000000 100644 0000000... a338584... A	gnetlist/tests/common/outputs/allegro/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/powersupply.retcode
:000000 100644 0000000... b73b3cb... A	gnetlist/tests/common/outputs/allegro/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/allegro/singlenet.retcode
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/bae/.gitignore
:000000 100644 0000000... 2878a95... A	gnetlist/tests/common/outputs/bae/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/bae/JD.retcode
:000000 100644 0000000... 2878a95... A	gnetlist/tests/common/outputs/bae/JD_Include-output.net
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:000000 100644 0000000... 9386f4b... A	gnetlist/tests/common/outputs/verilog/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/verilog/powersupply.retcode
:000000 100644 0000000... 3790cab... A	gnetlist/tests/common/outputs/verilog/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/verilog/singlenet.retcode
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/vhdl/.gitignore
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/JD.retcode
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/JD_Include.retcode
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge.retcode
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/JD_Sort.retcode
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge.retcode
:000000 100644 0000000... 534f455... A	gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
:000000 100644 0000000... bf3dd39... A	gnetlist/tests/common/outputs/vhdl/Makefile.am
:000000 100644 0000000... 0cd6b9f... A	gnetlist/tests/common/outputs/vhdl/SlottedOpamps-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/SlottedOpamps.retcode
:000000 100644 0000000... 30a9a84... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp.retcode
:000000 100644 0000000... 30a9a84... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include.retcode
:000000 100644 0000000... 30a9a84... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort.retcode
:000000 100644 0000000... 3ff2e72... A	gnetlist/tests/common/outputs/vhdl/cascade-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/cascade.retcode
:000000 100644 0000000... 68da18d... A	gnetlist/tests/common/outputs/vhdl/multiequal-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/multiequal.retcode
:000000 100644 0000000... a97e18e... A	gnetlist/tests/common/outputs/vhdl/netattrib-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/netattrib.retcode
:000000 100644 0000000... b815feb... A	gnetlist/tests/common/outputs/vhdl/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/powersupply.retcode
:000000 100644 0000000... 9c09d03... A	gnetlist/tests/common/outputs/vhdl/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vhdl/singlenet.retcode
:000000 100644 0000000... 23c1897... A	gnetlist/tests/common/outputs/vipec/.gitignore
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/JD.retcode
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/JD_Include.retcode
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/JD_Include_nomunge.retcode
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/JD_Sort.retcode
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge.retcode
:000000 100644 0000000... c7cd2ab... A	gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
:000000 100644 0000000... bf3dd39... A	gnetlist/tests/common/outputs/vipec/Makefile.am
:000000 100644 0000000... 663c0e3... A	gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/SlottedOpamps.retcode
:000000 100644 0000000... a5eda3f... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp.retcode
:000000 100644 0000000... a5eda3f... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include.retcode
:000000 100644 0000000... a5eda3f... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort.retcode
:000000 100644 0000000... 75b0b79... A	gnetlist/tests/common/outputs/vipec/cascade-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/cascade.retcode
:000000 100644 0000000... a800cc8... A	gnetlist/tests/common/outputs/vipec/multiequal-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/multiequal.retcode
:000000 100644 0000000... 9685438... A	gnetlist/tests/common/outputs/vipec/netattrib-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/netattrib.retcode
:000000 100644 0000000... 6e9bd91... A	gnetlist/tests/common/outputs/vipec/powersupply-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/powersupply.retcode
:000000 100644 0000000... 53b7251... A	gnetlist/tests/common/outputs/vipec/singlenet-output.net
:000000 100644 0000000... 573541a... A	gnetlist/tests/common/outputs/vipec/singlenet.retcode
:000000 100755 0000000... 933ce50... A	gnetlist/tests/common/run_backend_tests.sh
:000000 100755 0000000... 495868b... A	gnetlist/tests/common/run_tests.sh
:000000 100644 0000000... 8607735... A	gnetlist/tests/common/tests.list

=========
 Changes
=========

commit aaa1abbcfac8e67901c5b2a279e0a13f88d774b0
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 18:04:40 2008 +0100

    Tolerated changes in golden files for the vipec netlist backend.
    
    The way slotted parts are handled has changed since 1.2.0, as
    has the output of the vipec backend for slotted parts. Since
    this backend isn't likely to care about slotted parts, we allow
    these output changes as harmless.

diff --git a/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
index fbf59df..663c0e3 100644
--- a/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
@@ -2,7 +2,7 @@
 % Written by Matthew Ettus
 % Based on code by Bas Gieltjes
 CKT
-	error	7 8 9 7 5 6 7 3 4 7 1 2 	% U1
+	error	7 8 9 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U1
 	DEF2P	#<unspecified>  #<unspecified>
 	TERM	50 50
 
diff --git a/gnetlist/tests/common/outputs/vipec/singlenet-output.net b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
index 0da0f66..53b7251 100644
--- a/gnetlist/tests/common/outputs/vipec/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
@@ -2,7 +2,7 @@
 % Written by Matthew Ettus
 % Based on code by Bas Gieltjes
 CKT
-	error	1 #<unspecified> 1 3 3 3 3 3 3 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U100
+	error	3 3 3 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U100
 	DEF2P	#<unspecified>  #<unspecified>
 	TERM	50 50
 

commit ae9d82b1fdcd14acde5cbf4d54718ef3566aec80
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 18:03:50 2008 +0100

    Desired changes in golden file output for spice-sdb
    
    Slotted parts are now handled correctly. Was partly broken in 1.2.0.

diff --git a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
index 391b789..e571f05 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
@@ -6,8 +6,8 @@
 * Documentation at http://www.brorson.com/gEDA/SPICE/   *
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
-U1.1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a unknown
-U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
-U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
 U1.4 samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a unknown
+U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
+U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
+U1.1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a unknown
 .end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
index 895c7bb..775b16e 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
@@ -7,7 +7,7 @@
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
 F1 one unconnected_pin-3 <No valid value attribute found>
-U100.1 unconnected_pin-2 unconnected_pin-1 one unknown
-U300.1 one 1 unknown
-U200.1 one netattrib unknown
+U100 unconnected_pin-2 unconnected_pin-1 one unknown
+U300 one 1 unknown
+U200 one netattrib unknown
 .end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
index 966f3f2..21adb89 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
@@ -6,7 +6,7 @@
 * Documentation at http://www.brorson.com/gEDA/SPICE/   *
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
-U100.1 SING_N_2 unconnected_pin-1 SING_N_2 SING_N SING_N unknown
-U100.2 SING_N SING_N SING_N SING_N unknown
-U100.3 unknown
+U100.3 SING_N SING_N SING_N unknown
+U100.2 SING_N SING_N SING_N unknown
+U100.1 SING_N_2 unconnected_pin-1 SING_N_2 unknown
 .end

commit 850a80faa3038f688ef3630aff61a05c64904abc
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:48:57 2008 +0100

    Update pads backend golden files to match the new \r\n line ends.
    
    The \r\n line end change was made after 1.2.0, so we need to update.

diff --git a/gnetlist/tests/common/outputs/pads/JD-output.net b/gnetlist/tests/common/outputs/pads/JD-output.net
index c4fc30c..f3a5213 100644
--- a/gnetlist/tests/common/outputs/pads/JD-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include-output.net b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
index c4fc30c..f3a5213 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
index c4fc30c..f3a5213 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
index c4fc30c..f3a5213 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
index c4fc30c..f3a5213 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
index ec0991e..2031be3 100644
--- a/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
@@ -1,26 +1,26 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-U1	unknown
-
-*NET*
-*SIGNAL* MINUSIN_SLOT4_PIN13_B
- U1.13
-*SIGNAL* PLUSIN_SLOT4_PIN12_A
- U1.12
-*SIGNAL* MINUSIN_SLOT3_PIN_B
- U1.9
-*SIGNAL* PLUSIN_SLOT3_PIN10_A
- U1.10
-*SIGNAL* MINUSIN_SLOT2_PIN6_B
- U1.6
-*SIGNAL* PLUSIN_SLOT2_PIN5_A
- U1.5
-*SIGNAL* SAMENET_OUTPUT_C
- U1.14 U1.8 U1.7 U1.1
-*SIGNAL* MINUSIN_SLOT1_PIN_B
- U1.2
-*SIGNAL* PLUSIN_SLOT1_PIN3_A
- U1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U1	unknown
+
+*NET*
+*SIGNAL* MINUSIN_SLOT4_PIN13_B
+ U1.13
+*SIGNAL* PLUSIN_SLOT4_PIN12_A
+ U1.12
+*SIGNAL* MINUSIN_SLOT3_PIN_B
+ U1.9
+*SIGNAL* PLUSIN_SLOT3_PIN10_A
+ U1.10
+*SIGNAL* MINUSIN_SLOT2_PIN6_B
+ U1.6
+*SIGNAL* PLUSIN_SLOT2_PIN5_A
+ U1.5
+*SIGNAL* SAMENET_OUTPUT_C
+ U1.14 U1.8 U1.7 U1.1
+*SIGNAL* MINUSIN_SLOT1_PIN_B
+ U1.2
+*SIGNAL* PLUSIN_SLOT1_PIN3_A
+ U1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
index 0295af5..f443d47 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
index 0295af5..f443d47 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
index 0295af5..f443d47 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/cascade-output.net b/gnetlist/tests/common/outputs/pads/cascade-output.net
index 2643962..52c4cd5 100644
--- a/gnetlist/tests/common/outputs/pads/cascade-output.net
+++ b/gnetlist/tests/common/outputs/pads/cascade-output.net
@@ -1,29 +1,29 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-AMP2	none
-AMP1	none
-SOURCE	none
-DEFAULTS	unknown
-MX1	none
-DEF1	none
-T1	none
-FL1	none
-
-*NET*
-*SIGNAL* UNNAMED_NET6
- AMP2.1 T1.2
-*SIGNAL* UNNAMED_NET5
- T1.1 MX1.2
-*SIGNAL* UNNAMED_NET4
- MX1.1 FL1.2
-*SIGNAL* UNNAMED_NET3
- FL1.1 DEF1.2
-*SIGNAL* UNNAMED_NET2
- DEF1.1 AMP1.2
-*SIGNAL* UNNAMED_NET1
- AMP1.1 SOURCE.1
-*SIGNAL* GND
- DEFAULTS.1
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+AMP2	none
+AMP1	none
+SOURCE	none
+DEFAULTS	unknown
+MX1	none
+DEF1	none
+T1	none
+FL1	none
+
+*NET*
+*SIGNAL* UNNAMED_NET6
+ AMP2.1 T1.2
+*SIGNAL* UNNAMED_NET5
+ T1.1 MX1.2
+*SIGNAL* UNNAMED_NET4
+ MX1.1 FL1.2
+*SIGNAL* UNNAMED_NET3
+ FL1.1 DEF1.2
+*SIGNAL* UNNAMED_NET2
+ DEF1.1 AMP1.2
+*SIGNAL* UNNAMED_NET1
+ AMP1.1 SOURCE.1
+*SIGNAL* GND
+ DEFAULTS.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/multiequal-output.net b/gnetlist/tests/common/outputs/pads/multiequal-output.net
index 557fc85..d325973 100644
--- a/gnetlist/tests/common/outputs/pads/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/pads/multiequal-output.net
@@ -1,14 +1,14 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-A1	unknown
-R1	unknown
-
-*NET*
-*SIGNAL* GND
- V1.2 R1.1
-*SIGNAL* UNNAMED_NET1
- V1.1 R1.2
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+A1	unknown
+R1	unknown
+
+*NET*
+*SIGNAL* GND
+ V1.2 R1.1
+*SIGNAL* UNNAMED_NET1
+ V1.1 R1.2
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/netattrib-output.net b/gnetlist/tests/common/outputs/pads/netattrib-output.net
index 71d95b1..332cf53 100644
--- a/gnetlist/tests/common/outputs/pads/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/pads/netattrib-output.net
@@ -1,21 +1,21 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-F1	unknown
-U100	DIP14
-U300	DIP14
-U200	DIP14
-
-*NET*
-*SIGNAL* UNNAMED_NET1
- U300.2
-*SIGNAL* NETATTRIB
- U200.2 U100.5
-*SIGNAL* GND
- U300.7 U200.7 U100.7
-*SIGNAL* VCC
- U300.14 U200.14 U100.14
-*SIGNAL* ONE
- F1.1 U300.1 U200.1 U100.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+U100	DIP14
+U300	DIP14
+U200	DIP14
+
+*NET*
+*SIGNAL* UNNAMED_NET1
+ U300.2
+*SIGNAL* NETATTRIB
+ U200.2 U100.5
+*SIGNAL* GND
+ U300.7 U200.7 U100.7
+*SIGNAL* VCC
+ U300.14 U200.14 U100.14
+*SIGNAL* ONE
+ F1.1 U300.1 U200.1 U100.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/powersupply-output.net b/gnetlist/tests/common/outputs/pads/powersupply-output.net
index 5200ae8..3aa5cd9 100644
--- a/gnetlist/tests/common/outputs/pads/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/pads/powersupply-output.net
@@ -1,41 +1,41 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-F1	unknown
-R2	unknown
-CONN1	unknown
-C4	unknown
-R1	unknown
-C3	unknown
-C2	unknown
-S1	unknown
-C1	unknown
-T1	unknown
-U2	unknown
-U1	unknown
-
-*NET*
-*SIGNAL* TEN
- U2.1 R1.2 C3.1 R2.1
-*SIGNAL* ELEVEN
- U2.2 C4.1 R2.2
-*SIGNAL* GND
- CONN1.3
-*SIGNAL* ONE
- S1.1 CONN1.1
-*SIGNAL* FIVE
- CONN1.2 T1.2
-*SIGNAL* THREE
- T1.1 F1.2
-*SIGNAL* TWO
- S1.2 F1.1
-*SIGNAL* SIX
- T1.3 U1.4
-*SIGNAL* SEVEN
- T1.4 U1.3
-*SIGNAL* NINE
- C4.2 C3.2 R1.3 R1.1 C2.2 C1.2 U1.2
-*SIGNAL* EIGHT
- U2.3 C2.1 C1.1 U1.1
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+R2	unknown
+CONN1	unknown
+C4	unknown
+R1	unknown
+C3	unknown
+C2	unknown
+S1	unknown
+C1	unknown
+T1	unknown
+U2	unknown
+U1	unknown
+
+*NET*
+*SIGNAL* TEN
+ U2.1 R1.2 C3.1 R2.1
+*SIGNAL* ELEVEN
+ U2.2 C4.1 R2.2
+*SIGNAL* GND
+ CONN1.3
+*SIGNAL* ONE
+ S1.1 CONN1.1
+*SIGNAL* FIVE
+ CONN1.2 T1.2
+*SIGNAL* THREE
+ T1.1 F1.2
+*SIGNAL* TWO
+ S1.2 F1.1
+*SIGNAL* SIX
+ T1.3 U1.4
+*SIGNAL* SEVEN
+ T1.4 U1.3
+*SIGNAL* NINE
+ C4.2 C3.2 R1.3 R1.1 C2.2 C1.2 U1.2
+*SIGNAL* EIGHT
+ U2.3 C2.1 C1.1 U1.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/singlenet-output.net b/gnetlist/tests/common/outputs/pads/singlenet-output.net
index a0bfde7..db44a14 100644
--- a/gnetlist/tests/common/outputs/pads/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/pads/singlenet-output.net
@@ -1,16 +1,16 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-U100	DIP14
-
-*NET*
-*SIGNAL* SING_N_2
- U100.1 U100.3
-*SIGNAL* GND
- U100.7
-*SIGNAL* VCC
- U100.14
-*SIGNAL* SING_N
- U100.4 U100.5 U100.10 U100.8 U100.9 U100.6
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U100	DIP14
+
+*NET*
+*SIGNAL* SING_N_2
+ U100.1 U100.3
+*SIGNAL* GND
+ U100.7
+*SIGNAL* VCC
+ U100.14
+*SIGNAL* SING_N
+ U100.4 U100.5 U100.10 U100.8 U100.9 U100.6
+
+*END*

commit 345cd09f3517380a466a3254b1f6dc16ef2ce896
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:47:49 2008 +0100

    Remove the spice-sdb backend specific directory of gnetlist tests.
    
    They are now covered for all backends in the "common" tests directory.

diff --git a/gnetlist/configure.ac b/gnetlist/configure.ac
index 0fbdb9b..4009073 100644
--- a/gnetlist/configure.ac
+++ b/gnetlist/configure.ac
@@ -436,11 +436,6 @@ AC_CONFIG_FILES([Makefile
 		 tests/hierarchy/Makefile 
 		 tests/hierarchy2/Makefile 
 		 tests/drc2/Makefile
-		 tests/spice-sdb/Makefile
-		 tests/spice-sdb/inputs/Makefile
-		 tests/spice-sdb/inputs/sym/Makefile
-		 tests/spice-sdb/inputs/models/Makefile
-		 tests/spice-sdb/outputs/Makefile
 		 tests/common/Makefile
 		 tests/common/outputs/osmond/Makefile
 		 tests/common/outputs/pcbpins/Makefile
diff --git a/gnetlist/tests/Makefile.am b/gnetlist/tests/Makefile.am
index 1f4b468..b232426 100644
--- a/gnetlist/tests/Makefile.am
+++ b/gnetlist/tests/Makefile.am
@@ -1,6 +1,6 @@
 ## Process this file with automake to produce Makefile.in
 
-SUBDIRS = hierarchy hierarchy2 drc2 spice-sdb common
+SUBDIRS = hierarchy hierarchy2 drc2 common
 
 EXTRA_DIST = runtest.sh \
 	     7447.vhdl README amp.spice cascade.sch cascade.cascade \
diff --git a/gnetlist/tests/spice-sdb/.gitignore b/gnetlist/tests/spice-sdb/.gitignore
deleted file mode 100644
index 23c1897..0000000
--- a/gnetlist/tests/spice-sdb/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-Makefile
-Makefile.in
-*~
diff --git a/gnetlist/tests/spice-sdb/Makefile.am b/gnetlist/tests/spice-sdb/Makefile.am
deleted file mode 100644
index ab5a457..0000000
--- a/gnetlist/tests/spice-sdb/Makefile.am
+++ /dev/null
@@ -1,15 +0,0 @@
-## $Id$
-##
-
-SUBDIRS= inputs outputs
-
-TESTS_ENVIRONMENT= PERL=${PERL} HAVE_GETOPT_LONG=${HAVE_GETOPT_LONG}
-
-RUN_TESTS= run_tests.sh
-
-check_SCRIPTS= ${RUN_TESTS}
-
-TESTS= ${RUN_TESTS}
-
-EXTRA_DIST= run_tests.sh ${RUN_TESTS} tests.list 
-
diff --git a/gnetlist/tests/spice-sdb/inputs/.gitignore b/gnetlist/tests/spice-sdb/inputs/.gitignore
deleted file mode 100644
index 23c1897..0000000
--- a/gnetlist/tests/spice-sdb/inputs/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-Makefile
-Makefile.in
-*~
diff --git a/gnetlist/tests/spice-sdb/inputs/LVDfoo.sch b/gnetlist/tests/spice-sdb/inputs/LVDfoo.sch
deleted file mode 100644
index 419a0e6..0000000
--- a/gnetlist/tests/spice-sdb/inputs/LVDfoo.sch
+++ /dev/null
@@ -1,160 +0,0 @@
-v 20070216 1
-C 8700 85500 1 0 0 LVD.sym
-{
-T 9700 84500 5 10 1 1 0 0 1
-refdes=X1
-T 9600 84300 5 10 1 1 0 0 1
-model-name=unknown_LVD
-}
-C 9300 86500 1 0 0 asic-pmos-1.sym
-{
-T 10100 87300 5 10 1 1 0 0 1
-refdes=M1
-T 10100 87100 5 8 1 1 0 0 1
-model-name=pch
-T 10100 86800 5 8 1 0 0 0 1
-w=3u
-T 10100 86600 5 8 1 0 0 0 1
-l=3u
-T 10700 86700 5 10 1 0 0 0 1
-m=36
-}
-N 9300 85500 9300 87000 4
-N 9300 86500 11300 86500 4
-{
-T 11400 86500 5 10 1 1 0 0 1
-netname=LVH
-}
-N 10000 87000 10000 87500 4
-N 9900 87500 9900 88200 4
-{
-T 10100 88200 5 10 1 1 0 0 1
-netname=Vdd1
-}
-C 8400 86900 1 0 0 resistor-1.sym
-{
-T 8600 87200 5 10 1 1 0 0 1
-refdes=Rb
-T 8700 86700 5 10 1 1 0 0 1
-value=5.6k
-T 8400 86900 5 10 1 1 0 0 1
-device=RESISTOR
-}
-C 7900 86500 1 0 0 gnd-1.sym
-C 10800 84900 1 0 0 resistor-1.sym
-{
-T 11000 85200 5 10 1 1 0 0 1
-refdes=Rt
-T 11500 85200 5 10 1 1 0 0 1
-value=1k
-}
-N 9500 85500 9500 86300 4
-N 9900 84800 12600 84800 4
-{
-T 12700 84800 5 10 1 1 0 0 1
-netname=m
-}
-N 9900 85200 9900 85600 4
-N 9900 85600 12600 85600 4
-{
-T 12700 85600 5 10 1 1 0 0 1
-netname=p
-}
-N 11700 85000 11700 84800 4
-C 6800 83300 1 0 0 vpulse-1.sym
-{
-T 7500 83950 5 10 1 1 0 0 1
-refdes=V1
-T 7500 83750 5 10 1 1 0 0 1
-value=pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-}
-C 7000 82700 1 0 0 gnd-1.sym
-N 8700 85000 7100 85000 4
-{
-T 7700 85100 5 10 1 1 0 0 1
-netname=i
-}
-N 7100 85000 7100 84500 4
-C 13200 84800 1 0 0 vdc-1.sym
-{
-T 13900 85450 5 10 1 1 0 0 1
-refdes=Vdd
-T 13900 85250 5 10 1 1 0 0 1
-value=DC 3.3V
-}
-C 13400 84200 1 0 0 gnd-1.sym
-N 9900 87500 13500 87500 4
-N 13500 87500 13500 86000 4
-N 9500 86300 13500 86300 4
-C 10800 83900 1 0 0 resistor-1.sym
-{
-T 11000 84200 5 10 1 1 0 0 1
-refdes=Rlm
-T 11500 84200 5 10 1 1 0 0 1
-value=500k
-}
-C 11600 83300 1 0 0 gnd-1.sym
-N 10800 84000 10800 84800 4
-C 11100 85800 1 0 0 resistor-1.sym
-{
-T 11300 86100 5 10 1 1 0 0 1
-refdes=Rlp
-T 11800 86100 5 10 1 1 0 0 1
-value=1meg
-}
-N 12000 85900 13200 85900 4
-N 13200 85900 13200 86100 4
-N 13200 86100 13500 86100 4
-N 11100 85900 11100 85600 4
-C 9200 84000 1 0 0 gnd-1.sym
-C 9400 84000 1 0 0 gnd-1.sym
-N 10800 85000 10800 85600 4
-C 12700 83400 1 0 0 capacitor-1.sym
-{
-T 12900 83900 5 10 1 1 0 0 1
-refdes=Cp
-T 12900 84300 5 10 0 0 0 0 1
-symversion=0.1
-T 12700 83400 5 10 1 1 0 0 1
-value=20p
-}
-C 12700 82600 1 0 0 capacitor-1.sym
-{
-T 12900 83100 5 10 1 1 0 0 1
-refdes=Cm
-T 12900 83500 5 10 0 0 0 0 1
-symversion=0.1
-T 12700 82600 5 10 1 1 0 0 1
-value=20p
-T 12700 82600 5 10 1 1 0 0 1
-device=CAPACITOR
-}
-C 14000 83100 1 0 0 gnd-1.sym
-C 14000 82300 1 0 0 gnd-1.sym
-N 12700 83600 12300 83600 4
-N 12300 83600 12300 85600 4
-N 12700 82800 12100 82800 4
-C 5200 80400 0 0 0 title-bordered-A.sym
-N 8400 87000 8000 87000 4
-N 8000 87000 8000 86800 4
-N 9500 84300 9500 84500 4
-N 9300 84500 9300 84300 4
-N 12100 82800 12100 84800 4
-N 13500 84500 13500 84800 4
-N 7100 83300 7100 83000 4
-N 11700 84000 11700 83600 4
-N 13600 83600 14100 83600 4
-N 14100 83600 14100 83400 4
-N 13600 82800 14100 82800 4
-N 14100 82800 14100 82600 4
-C 5800 87400 1 0 0 spice-model-1.sym
-{
-T 5900 88100 5 10 0 1 0 0 1
-device=model
-T 5900 88000 5 10 1 1 0 0 1
-refdes=A1
-T 7100 87700 5 10 1 1 0 0 1
-model-name=unknown_LVD
-T 6300 87500 5 10 1 1 0 0 1
-file=./models/openIP_5.cir
-}
diff --git a/gnetlist/tests/spice-sdb/inputs/Makefile.am b/gnetlist/tests/spice-sdb/inputs/Makefile.am
deleted file mode 100644
index d91dd00..0000000
--- a/gnetlist/tests/spice-sdb/inputs/Makefile.am
+++ /dev/null
@@ -1,9 +0,0 @@
-SUBDIRS = models sym
-
-EXTRA_DIST= \
-     gafrc \
-     LVDfoo.sch \
-     Simulation.cmd \
-     TwoStageAmp.sch \
-     SlottedOpamps.sch
-
diff --git a/gnetlist/tests/spice-sdb/inputs/Simulation.cmd b/gnetlist/tests/spice-sdb/inputs/Simulation.cmd
deleted file mode 100644
index 8e6e522..0000000
--- a/gnetlist/tests/spice-sdb/inputs/Simulation.cmd
+++ /dev/null
@@ -1,5 +0,0 @@
-.OP
-.AC DEC 20 1Hz 100MegHz
-* .DC Vinput 0 5 .01
-* .DC Vinput 1 2 .01
-
diff --git a/gnetlist/tests/spice-sdb/inputs/SlottedOpamps.sch b/gnetlist/tests/spice-sdb/inputs/SlottedOpamps.sch
deleted file mode 100644
index 3eeaf01..0000000
--- a/gnetlist/tests/spice-sdb/inputs/SlottedOpamps.sch
+++ /dev/null
@@ -1,98 +0,0 @@
-v 20070216 1
-C 40000 40000 0 0 0 title-B.sym
-C 46500 48100 1 0 0 LM324_slotted-1.sym
-{
-T 47325 48250 5 8 0 0 0 0 1
-device=LM324
-T 46700 49000 5 10 1 1 0 0 1
-refdes=U1
-T 46500 48100 5 10 1 0 0 0 1
-slot=1
-}
-C 46500 46000 1 0 0 LM324_slotted-1.sym
-{
-T 47325 46150 5 8 0 0 0 0 1
-device=LM324
-T 46700 46900 5 10 1 1 0 0 1
-refdes=U1
-T 46500 46000 5 10 1 0 0 0 1
-slot=2
-}
-C 46500 44200 1 0 0 LM324_slotted-1.sym
-{
-T 47325 44350 5 8 0 0 0 0 1
-device=LM324
-T 46700 45100 5 10 1 1 0 0 1
-refdes=U1
-T 46500 44200 5 10 1 0 0 0 1
-slot=3
-}
-C 46500 42100 1 0 0 LM324_slotted-1.sym
-{
-T 47325 42250 5 8 0 0 0 0 1
-device=LM324
-T 46700 43000 5 10 1 1 0 0 1
-refdes=U1
-T 46500 42100 5 10 1 0 0 0 1
-slot=4
-}
-N 46600 48700 45400 48700 4
-{
-T 44000 48800 5 10 1 0 0 0 1
-netname=plusin_slot1_pin3_a
-}
-N 46500 46600 45300 46600 4
-{
-T 43900 46700 5 10 1 0 0 0 1
-netname=plusin_slot2_pin5_a
-}
-N 46500 44800 45300 44800 4
-{
-T 43900 44900 5 10 1 0 0 0 1
-netname=plusin_slot3_pin10_a
-}
-N 46500 42700 45300 42700 4
-{
-T 43900 42800 5 10 1 0 0 0 1
-netname=plusin_slot4_pin12_a
-}
-N 46500 48300 45300 48300 4
-{
-T 43900 48400 5 10 1 0 0 0 1
-netname=minusin_slot1_pin_b
-}
-N 46500 46200 45300 46200 4
-{
-T 43900 46300 5 10 1 0 0 0 1
-netname=minusin_slot2_pin6_b
-}
-N 46500 44400 45300 44400 4
-{
-T 43900 44500 5 10 1 0 0 0 1
-netname=minusin_slot3_pin_b
-}
-N 46500 42300 45300 42300 4
-{
-T 43900 42400 5 10 1 0 0 0 1
-netname=minusin_slot4_pin13_b
-}
-N 47500 48500 48900 48500 4
-{
-T 47500 48600 5 10 1 0 0 0 1
-netname=samenet_output_c
-}
-N 47500 46400 48900 46400 4
-{
-T 47500 46500 5 10 1 0 0 0 1
-netname=samenet_output_c
-}
-N 47500 44600 48900 44600 4
-{
-T 47500 44700 5 10 1 0 0 0 1
-netname=samenet_output_c
-}
-N 47500 42500 48900 42500 4
-{
-T 47500 42600 5 10 1 0 0 0 1
-netname=samenet_output_c
-}
diff --git a/gnetlist/tests/spice-sdb/inputs/TwoStageAmp.sch b/gnetlist/tests/spice-sdb/inputs/TwoStageAmp.sch
deleted file mode 100644
index 473a990..0000000
--- a/gnetlist/tests/spice-sdb/inputs/TwoStageAmp.sch
+++ /dev/null
@@ -1,313 +0,0 @@
-v 20070216 1
-C 31900 49200 1 0 0 transistor.sym
-{
-T 32800 49700 5 10 1 1 0 0 1
-refdes=Q1
-T 32800 49900 5 10 1 1 0 0 1
-model-name=2N3904
-T 32800 49900 5 10 0 0 0 0 1
-device=NPN_TRANSISTOR
-}
-C 28100 49600 1 0 0 resistor-1.sym
-{
-T 28300 49900 5 10 1 1 0 0 1
-refdes=R5
-T 28400 49400 5 10 1 1 0 0 1
-value=10
-T 28400 50000 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 31100 49900 1 90 0 resistor-1.sym
-{
-T 31400 50700 5 10 1 1 180 0 1
-refdes=R1
-T 31200 50200 5 10 1 1 0 0 1
-value=28K
-T 31400 50300 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 31600 48200 1 90 0 resistor-1.sym
-{
-T 31900 48900 5 10 1 1 180 0 1
-refdes=R2
-T 31600 48200 5 10 1 1 0 0 1
-value=2K
-T 31900 48600 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 32600 47900 1 90 0 resistor-1.sym
-{
-T 33000 48600 5 10 1 1 180 0 1
-refdes=RE1
-T 32600 47900 5 10 1 1 0 0 1
-value=100
-T 32900 48300 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 38000 54600 1 90 0 resistor-1.sym
-{
-T 38400 55300 5 10 1 1 180 0 1
-refdes=RC2
-T 38000 54600 5 10 1 1 0 0 1
-value=1K
-T 38300 55000 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 40800 52200 1 90 0 resistor-1.sym
-{
-T 41100 53100 5 10 1 1 180 0 1
-refdes=RL
-T 40800 52200 5 10 1 1 0 0 1
-value=100K
-T 41100 52600 5 10 0 0 0 0 1
-device=RESISTOR
-}
-N 32500 49200 32500 48800 4
-C 39300 53900 1 0 0 capacitor-1.sym
-{
-T 39500 54400 5 10 1 1 0 0 1
-refdes=Cout
-T 39500 53700 5 10 1 1 0 0 1
-value=2.2uF
-T 39500 54600 5 10 0 0 0 0 1
-device=CAPACITOR
-T 39500 54800 5 10 0 0 0 0 1
-symversion=0.1
-}
-C 33700 47900 1 90 0 capacitor-1.sym
-{
-T 34100 48600 5 10 1 1 180 0 1
-refdes=CE1
-T 33700 47900 5 10 1 1 0 0 1
-value=1pF
-T 33900 48600 5 10 0 0 0 0 1
-device=CAPACITOR
-T 33900 48800 5 10 0 0 0 0 1
-symversion=0.1
-}
-N 33500 48800 33500 49100 4
-N 39300 54100 37900 54100 4
-{
-T 38000 53800 5 10 1 1 0 0 1
-netname=VColl2
-}
-N 40700 54100 40700 53100 4
-C 31400 47400 1 0 0 gnd-1.sym
-C 32400 47400 1 0 0 gnd-1.sym
-C 33400 47400 1 0 0 gnd-1.sym
-C 40600 51200 1 0 0 gnd-1.sym
-C 27200 48300 1 0 0 vsin-1.sym
-{
-T 27900 48950 5 10 1 1 0 0 1
-refdes=Vinput
-T 26800 48150 5 10 1 1 0 0 1
-value=DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-T 27900 49150 5 10 0 0 0 0 1
-device=vsin
-T 27900 49350 5 10 0 0 0 0 1
-footprint=none
-}
-C 40700 48700 1 0 0 vdc-1.sym
-{
-T 41400 49350 5 10 1 1 0 0 1
-refdes=VCC
-T 41400 49150 5 10 1 1 0 0 1
-value=DC 15V
-T 41400 49550 5 10 0 0 0 0 1
-device=VOLTAGE_SOURCE
-T 41400 49750 5 10 0 0 0 0 1
-footprint=none
-}
-C 40800 50100 1 0 0 vcc-1.sym
-C 37700 55700 1 0 0 vcc-1.sym
-N 37900 55700 37900 55500 4
-N 41000 50100 41000 49900 4
-C 40900 48200 1 0 0 gnd-1.sym
-C 27400 47600 1 0 0 gnd-1.sym
-N 27500 48300 27500 47900 4
-N 27500 49700 27500 49500 4
-N 31500 48200 31500 47700 4
-N 32500 47900 32500 47700 4
-N 33500 47900 33500 47700 4
-N 40700 52200 40700 51500 4
-N 41000 48700 41000 48500 4
-N 40200 54100 41300 54100 4
-{
-T 41500 54100 5 10 1 1 0 0 1
-netname=Vout
-}
-C 26000 46000 0 0 0 title-B.sym
-C 26500 55500 1 0 0 spice-model-1.sym
-{
-T 26600 56100 5 10 1 1 0 0 1
-refdes=A1
-T 27800 55800 5 10 1 1 0 0 1
-model-name=2N3904
-T 27000 55600 5 10 1 1 0 0 1
-file=./models/2N3904.mod
-T 26600 56200 5 10 0 1 0 0 1
-device=model
-}
-C 26500 54600 1 0 0 spice-include-1.sym
-{
-T 26600 55000 5 10 1 1 0 0 1
-refdes=A2
-T 27000 54700 5 10 1 1 0 0 1
-file=Simulation.cmd
-T 26600 54900 5 10 0 1 0 0 1
-device=include
-}
-C 26500 53700 1 0 0 spice-directive-1.sym
-{
-T 26600 54100 5 10 1 1 0 0 1
-refdes=A3
-T 26600 53800 5 10 1 1 0 0 1
-value=.options TEMP=25
-T 26600 54000 5 10 0 1 0 0 1
-device=directive
-T 26600 53800 5 10 1 1 0 0 1
-file=?
-}
-N 27000 49700 28100 49700 4
-{
-T 26700 49700 5 10 1 1 0 0 1
-netname=Vin
-}
-N 31000 49900 31000 49700 4
-N 31500 49100 31500 49700 4
-C 29400 49500 1 0 0 capacitor-1.sym
-{
-T 29600 50000 5 10 1 1 0 0 1
-refdes=C1
-T 29500 49300 5 10 1 1 0 0 1
-value=2.2uF
-T 29600 50200 5 10 0 0 0 0 1
-device=CAPACITOR
-T 29600 50400 5 10 0 0 0 0 1
-symversion=0.1
-}
-N 29000 49700 29400 49700 4
-C 37300 52600 1 0 0 transistor.sym
-{
-T 38200 53100 5 10 1 1 0 0 1
-refdes=Q2
-T 38200 52700 5 10 1 1 0 0 1
-model-name=2N3904
-T 38200 53300 5 10 0 0 0 0 1
-device=NPN_TRANSISTOR
-}
-C 37800 48900 1 0 0 gnd-1.sym
-N 37900 53600 37900 54600 4
-C 30800 51000 1 0 0 vcc-1.sym
-N 31000 50800 31000 51000 4
-T 36100 46800 9 20 1 0 0 0 1
-Two stage amplifier SPICE playpen
-T 40000 46100 9 10 1 0 0 0 1
-Stuart Brorson -- sdb@xxxxxxxxxx
-C 32600 53500 1 90 0 resistor-1.sym
-{
-T 32900 54400 5 10 1 1 180 0 1
-refdes=RC1
-T 32600 53500 5 10 1 1 0 0 1
-value=3.3K
-T 32900 53900 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 38000 49500 1 90 0 resistor-1.sym
-{
-T 38500 50300 5 10 1 1 180 0 1
-refdes=RE2
-T 38000 49500 5 10 1 1 0 0 1
-value=100
-T 38300 49900 5 10 0 0 0 0 1
-device=RESISTOR
-}
-N 37900 49200 37900 49500 4
-N 37900 50400 37900 52600 4
-N 32500 50200 32500 53500 4
-C 32300 54800 1 0 0 vcc-1.sym
-N 32500 54400 32500 54800 4
-N 30300 49700 31900 49700 4
-{
-T 30700 49500 5 10 1 1 0 0 1
-netname=Vbase1
-}
-C 39200 49500 1 90 0 capacitor-1.sym
-{
-T 39600 50200 5 10 1 1 180 0 1
-refdes=CE2
-T 39200 49500 5 10 1 1 0 0 1
-value=1pF
-T 39400 50200 5 10 0 0 0 0 1
-device=CAPACITOR
-T 39400 50400 5 10 0 0 0 0 1
-symversion=0.1
-}
-C 38900 48900 1 0 0 gnd-1.sym
-N 39000 49500 39000 49200 4
-N 39000 50400 39000 51000 4
-N 39000 51000 37900 51000 4
-{
-T 38000 51100 5 10 1 1 0 0 1
-netname=Vem2
-}
-N 32500 49100 33500 49100 4
-{
-T 32700 49200 5 10 1 1 0 0 1
-netname=Vem1
-}
-C 33300 53000 1 0 0 resistor-1.sym
-{
-T 33500 53300 5 10 1 1 0 0 1
-refdes=R8
-T 33500 52700 5 10 1 1 0 0 1
-value=1
-T 33600 53400 5 10 0 0 0 0 1
-device=RESISTOR
-}
-N 35900 53100 37300 53100 4
-{
-T 36800 52900 5 10 1 1 0 0 1
-netname=Vbase2
-}
-N 32500 53100 33300 53100 4
-{
-T 32600 52900 5 10 1 1 0 0 1
-netname=Vcoll1
-}
-C 36700 54700 1 90 0 resistor-1.sym
-{
-T 37000 55500 5 10 1 1 180 0 1
-refdes=R3
-T 36800 55000 5 10 1 1 0 0 1
-value=28K
-T 37000 55100 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 36400 51600 1 90 0 resistor-1.sym
-{
-T 36700 52300 5 10 1 1 180 0 1
-refdes=R4
-T 36400 51600 5 10 1 1 0 0 1
-value=2.8K
-T 36700 52000 5 10 0 0 0 0 1
-device=RESISTOR
-}
-C 36200 50800 1 0 0 gnd-1.sym
-N 36300 51600 36300 51100 4
-N 36300 52500 36300 53100 4
-C 36400 55800 1 0 0 vcc-1.sym
-N 36600 55600 36600 55800 4
-C 35000 52900 1 0 0 capacitor-1.sym
-{
-T 35200 53400 5 10 1 1 0 0 1
-refdes=C2
-T 35100 52700 5 10 1 1 0 0 1
-value=2.2uF
-T 35200 53600 5 10 0 0 0 0 1
-device=CAPACITOR
-T 35200 53800 5 10 0 0 0 0 1
-symversion=0.1
-}
-N 35000 53100 34200 53100 4
-N 36600 53100 36600 54700 4
diff --git a/gnetlist/tests/spice-sdb/inputs/gafrc b/gnetlist/tests/spice-sdb/inputs/gafrc
deleted file mode 100644
index 7408ef0..0000000
--- a/gnetlist/tests/spice-sdb/inputs/gafrc
+++ /dev/null
@@ -1 +0,0 @@
-(component-library "./sym")
diff --git a/gnetlist/tests/spice-sdb/inputs/models/.gitignore b/gnetlist/tests/spice-sdb/inputs/models/.gitignore
deleted file mode 100644
index 23c1897..0000000
--- a/gnetlist/tests/spice-sdb/inputs/models/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-Makefile
-Makefile.in
-*~
diff --git a/gnetlist/tests/spice-sdb/inputs/models/2N3904.mod b/gnetlist/tests/spice-sdb/inputs/models/2N3904.mod
deleted file mode 100644
index f8d0e80..0000000
--- a/gnetlist/tests/spice-sdb/inputs/models/2N3904.mod
+++ /dev/null
@@ -1,4 +0,0 @@
-.model 2N3904   NPN(Stuff
-+               More stuff
-+               Yet more stuff
-+               Final line of stuff)
diff --git a/gnetlist/tests/spice-sdb/inputs/models/Makefile.am b/gnetlist/tests/spice-sdb/inputs/models/Makefile.am
deleted file mode 100644
index 4630408..0000000
--- a/gnetlist/tests/spice-sdb/inputs/models/Makefile.am
+++ /dev/null
@@ -1,3 +0,0 @@
-EXTRA_DIST= \
-     2N3904.mod \
-     openIP_5.cir
diff --git a/gnetlist/tests/spice-sdb/inputs/models/openIP_5.cir b/gnetlist/tests/spice-sdb/inputs/models/openIP_5.cir
deleted file mode 100644
index 26bf372..0000000
--- a/gnetlist/tests/spice-sdb/inputs/models/openIP_5.cir
+++ /dev/null
@@ -1,2 +0,0 @@
-*
-.model unknown_LVD (stuff)
diff --git a/gnetlist/tests/spice-sdb/inputs/sym/.gitignore b/gnetlist/tests/spice-sdb/inputs/sym/.gitignore
deleted file mode 100644
index 23c1897..0000000
--- a/gnetlist/tests/spice-sdb/inputs/sym/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-Makefile
-Makefile.in
-*~
diff --git a/gnetlist/tests/spice-sdb/inputs/sym/LM324_slotted-1.sym b/gnetlist/tests/spice-sdb/inputs/sym/LM324_slotted-1.sym
deleted file mode 100644
index 1707dad..0000000
--- a/gnetlist/tests/spice-sdb/inputs/sym/LM324_slotted-1.sym
+++ /dev/null
@@ -1,60 +0,0 @@
-v 20031231 1
-L 200 0 200 800 3 0 0 0 -1 -1
-L 200 800 800 400 3 0 0 0 -1 -1
-L 800 400 200 0 3 0 0 0 -1 -1
-T 825 150 5 8 0 0 0 0 1
-device=LM324
-T 700 1200 5 10 0 0 0 0 1
-numslots=4
-T 675 1050 5 10 0 0 0 0 1
-slotdef=1:1,2,3
-T 675 900 5 10 0 0 0 0 1
-slotdef=2:7,6,5
-T 675 750 5 10 0 0 0 0 1
-slotdef=3:8,9,10
-T 675 600 5 10 0 0 0 0 1
-slotdef=4:14,13,12
-T 1225 450 5 10 0 0 0 0 1
-slot=1
-P 200 600 0 600 1 0 1
-{
-T 50 625 5 8 1 1 0 0 1
-pinnumber=3
-T 50 625 5 8 0 0 0 0 1
-pinseq=3
-}
-P 200 200 0 200 1 0 1
-{
-T 50 225 5 8 1 1 0 0 1
-pinnumber=2
-T 50 225 5 8 0 0 0 0 1
-pinseq=2
-}
-P 800 400 1000 400 1 0 1
-{
-T 875 425 5 8 1 1 0 0 1
-pinnumber=1
-T 875 425 5 8 0 0 0 0 1
-pinseq=1
-}
-#P 500 200 500 0 1 0 1
-#{
-#T 525 50 5 8 1 1 0 0 1
-#pinnumber=11
-#T 525 50 5 8 0 0 0 0 1
-#pinseq=11
-#}
-#P 500 600 500 800 1 0 1
-#{
-#T 525 650 5 8 1 1 0 0 1
-#pinnumber=4
-#T 525 650 5 8 0 0 0 0 1
-#pinseq=4
-#}
-L 250 600 350 600 3 0 0 0 -1 -1
-L 300 650 300 550 3 0 0 0 -1 -1
-L 250 200 350 200 3 0 0 0 -1 -1
-T 225 350 9 8 1 0 0 0 1
-LM324
-T 200 900 8 10 1 1 0 0 1
-refdes=U?
diff --git a/gnetlist/tests/spice-sdb/inputs/sym/LVD.sym b/gnetlist/tests/spice-sdb/inputs/sym/LVD.sym
deleted file mode 100644
index 6ab69da..0000000
--- a/gnetlist/tests/spice-sdb/inputs/sym/LVD.sym
+++ /dev/null
@@ -1,86 +0,0 @@
-v 20070216 1
-L 200 0 200 -1000 3 0 0 0 -1 -1
-T 500 -500 8 10 0 1 0 4 1
-device=LVD
-L 200 -1000 1200 -500 3 0 0 0 -1 -1
-L 1200 -500 200 0 3 0 0 0 -1 -1
-V 900 -700 49 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-P 1200 -700 950 -700 1 0 0
-{
-T 1200 -700 5 10 0 0 0 0 1
-pinnumber=4
-T 1200 -700 5 10 0 0 0 0 1
-pinseq=4
-T 1200 -700 5 10 0 0 0 0 1
-pintype=out
-T 1200 -700 5 10 0 0 0 0 1
-pinlabel=Y0
-}
-P 1200 -300 800 -300 1 0 0
-{
-T 1200 -300 5 10 0 0 0 0 1
-pinnumber=5
-T 1200 -300 5 10 0 0 0 0 1
-pinseq=5
-T 1200 -300 5 10 0 0 0 0 1
-pintype=out
-T 1200 -300 5 10 0 0 0 0 1
-pinlabel=Y1
-}
-P 0 -500 200 -500 1 0 0
-{
-T 0 -500 5 10 0 0 0 0 1
-pinnumber=1
-T 0 -500 5 10 0 0 0 0 1
-pinseq=1
-T 0 -500 5 10 0 0 0 0 1
-pintype=in
-T 0 -500 5 10 0 0 0 0 1
-pinlabel=D
-}
-P 600 0 600 -200 1 0 0
-{
-T 600 0 5 10 0 0 0 0 1
-pinnumber=3
-T 600 0 5 10 0 0 0 0 1
-pinseq=3
-T 600 0 5 10 0 0 0 0 1
-pintype=in
-T 600 -200 5 6 1 1 0 8 1
-pinlabel=VH
-}
-P 600 -1000 600 -800 1 0 0
-{
-T 600 -1000 5 10 0 0 0 0 1
-pinnumber=2
-T 600 -1000 5 10 0 0 0 0 1
-pinseq=2
-T 600 -1000 5 10 0 0 0 0 1
-pintype=pwr
-T 600 -800 5 6 1 1 0 6 1
-pinlabel=DGND
-}
-T 200 0 8 10 0 1 0 0 1
-refdes=X?
-P 800 0 800 -300 1 0 0
-{
-T 600 -300 5 10 0 0 0 0 1
-pinnumber=6
-T 600 -300 5 10 0 0 0 0 1
-pinseq=6
-T 600 -300 5 10 0 0 0 0 1
-pintype=pwr
-T 600 -300 5 10 0 0 0 0 1
-pinlabel=Vdd1
-}
-P 800 -1000 800 -700 1 0 0
-{
-T 600 -700 5 10 0 0 0 0 1
-pinnumber=7
-T 600 -700 5 10 0 0 0 0 1
-pinseq=7
-T 600 -700 5 10 0 0 0 0 1
-pintype=pwr
-T 600 -700 5 10 0 0 0 0 1
-pinlabel=Vss
-}
diff --git a/gnetlist/tests/spice-sdb/inputs/sym/Makefile.am b/gnetlist/tests/spice-sdb/inputs/sym/Makefile.am
deleted file mode 100644
index 76adbcf..0000000
--- a/gnetlist/tests/spice-sdb/inputs/sym/Makefile.am
+++ /dev/null
@@ -1,4 +0,0 @@
-EXTRA_DIST= \
-     LVD.sym \
-     transistor.sym \
-     LM324_slotted-1.sym 
diff --git a/gnetlist/tests/spice-sdb/inputs/sym/transistor.sym b/gnetlist/tests/spice-sdb/inputs/sym/transistor.sym
deleted file mode 100644
index 65492d4..0000000
--- a/gnetlist/tests/spice-sdb/inputs/sym/transistor.sym
+++ /dev/null
@@ -1,36 +0,0 @@
-v 20031011 1
-P 600 1000 600 800 1 0 0
-{
-T 500 850 5 6 1 1 0 0 1
-pinnumber=3
-T 500 850 5 6 0 0 0 0 1
-pinseq=1
-}
-P 600 200 600 0 1 0 1
-{
-T 500 50 5 6 1 1 0 0 1
-pinnumber=1
-T 500 50 5 6 0 0 0 0 1
-pinseq=3
-}
-V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
-T 900 700 5 10 0 0 0 0 1
-device=NPN_TRANSISTOR
-L 600 200 400 400 3 0 0 0 -1 -1
-L 600 800 400 600 3 0 0 0 -1 -1
-L 400 700 400 300 3 0 0 0 -1 -1
-P 0 500 184 500 1 0 0
-{
-T 100 550 5 6 1 1 0 0 1
-pinnumber=2
-T 100 550 5 6 0 0 0 0 1
-pinseq=2
-}
-L 400 500 184 500 3 0 0 0 -1 -1
-L 600 200 564 272 3 0 0 0 -1 -1
-L 600 200 528 236 3 0 0 0 -1 -1
-L 528 236 564 272 3 0 0 0 -1 -1
-T 900 500 8 10 1 1 0 0 1
-refdes=Q?
-T 900 300 9 10 1 0 0 0 1
-Generic_Transistor
diff --git a/gnetlist/tests/spice-sdb/outputs/.gitignore b/gnetlist/tests/spice-sdb/outputs/.gitignore
deleted file mode 100644
index 23c1897..0000000
--- a/gnetlist/tests/spice-sdb/outputs/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-Makefile
-Makefile.in
-*~
diff --git a/gnetlist/tests/spice-sdb/outputs/JD-output.net b/gnetlist/tests/spice-sdb/outputs/JD-output.net
deleted file mode 100644
index e1bb285..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Include-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Include-output.net
deleted file mode 100644
index 647fbff..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Include-output.net
+++ /dev/null
@@ -1,20 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -I LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-.INCLUDE ./models/openIP_5.cir
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge-output.net
deleted file mode 100644
index eec3dd1..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge-output.net
+++ /dev/null
@@ -1,20 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -I -n LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-.INCLUDE ./models/openIP_5.cir
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge_longopt-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge_longopt-output.net
deleted file mode 100644
index 5d34df1..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Include_nomunge_longopt-output.net
+++ /dev/null
@@ -1,20 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -I --nomunge LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-.INCLUDE ./models/openIP_5.cir
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Sort-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Sort-output.net
deleted file mode 100644
index d715184..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Sort-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -s LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-Cm m 0 20p  
-Cp p 0 20p  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-Rb 0 LVH 5.6k  
-Rlm m 0 500k  
-Rlp p Vdd1 1meg  
-Rt p m 1k  
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Vdd Vdd1 0 DC 3.3V
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge-output.net
deleted file mode 100644
index ce92fdf..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -s -n LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-Cm m 0 20p  
-Cp p 0 20p  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-Rb 0 LVH 5.6k  
-Rlm m 0 500k  
-Rlp p Vdd1 1meg  
-Rt p m 1k  
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Vdd Vdd1 0 DC 3.3V
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge_longopt-output.net b/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge_longopt-output.net
deleted file mode 100644
index 6dceec6..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_Sort_nomunge_longopt-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -s --nomunge LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-Cm m 0 20p  
-Cp p 0 20p  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-Rb 0 LVH 5.6k  
-Rlm m 0 500k  
-Rlp p Vdd1 1meg  
-Rt p m 1k  
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Vdd Vdd1 0 DC 3.3V
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_nomunge-output.net b/gnetlist/tests/spice-sdb/outputs/JD_nomunge-output.net
deleted file mode 100644
index e1bb285..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_nomunge-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-UX1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/JD_nomunge_longopt-output.net b/gnetlist/tests/spice-sdb/outputs/JD_nomunge_longopt-output.net
deleted file mode 100644
index 9c1c1d8..0000000
--- a/gnetlist/tests/spice-sdb/outputs/JD_nomunge_longopt-output.net
+++ /dev/null
@@ -1,24 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb --nomunge LVDfoo.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
-*
-.model unknown_LVD (stuff)
-*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
-Cm m 0 20p  
-Rt p m 1k  
-M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
-X1 i 0 LVH m p Vdd1 0 unknown_LVD
-Rlp p Vdd1 1meg  
-Vdd Vdd1 0 DC 3.3V
-Rlm m 0 500k  
-Cp p 0 20p  
-Rb 0 LVH 5.6k  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/Makefile.am b/gnetlist/tests/spice-sdb/outputs/Makefile.am
deleted file mode 100644
index cb9d0cf..0000000
--- a/gnetlist/tests/spice-sdb/outputs/Makefile.am
+++ /dev/null
@@ -1,22 +0,0 @@
-# can recreate easily with
-# ls *.net | sort | awk 'BEGIN{printf("EXTRA_DIST= \\\n")} {printf("\t%s \\\n", $0)}' >> Makefile.am
-#
-# don't forget to remove the last backslash
-
-EXTRA_DIST= \
-	JD-output.net \
-	JD_Include-output.net \
-	JD_Include_nomunge-output.net \
-	JD_Include_nomunge_longopt-output.net \
-	JD_Sort-output.net \
-	JD_Sort_nomunge-output.net \
-	JD_Sort_nomunge_longopt-output.net \
-	JD_nomunge-output.net \
-	JD_nomunge_longopt-output.net \
-	SlottedOpamps-output.net \
-	TwoStageAmp-output.net \
-	TwoStageAmp_Include-output.net \
-	TwoStageAmp_Include_longopt-output.net \
-	TwoStageAmp_Sort-output.net \
-	TwoStageAmp_Sort_longopt-output.net
-
diff --git a/gnetlist/tests/spice-sdb/outputs/SlottedOpamps-output.net b/gnetlist/tests/spice-sdb/outputs/SlottedOpamps-output.net
deleted file mode 100644
index e571f05..0000000
--- a/gnetlist/tests/spice-sdb/outputs/SlottedOpamps-output.net
+++ /dev/null
@@ -1,13 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb SlottedOpamps.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*==============  Begin SPICE netlist of main design ============
-U1.4 samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a unknown
-U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
-U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
-U1.1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a unknown
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp-output.net b/gnetlist/tests/spice-sdb/outputs/TwoStageAmp-output.net
deleted file mode 100644
index 3fa5a97..0000000
--- a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp-output.net
+++ /dev/null
@@ -1,38 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb TwoStageAmp.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
-.model 2N3904   NPN(Stuff
-+               More stuff
-+               Yet more stuff
-+               Final line of stuff)
-*^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-Cout VColl2 Vout 2.2uF  
-R5 Vin 1 10  
-R4 0 Vbase2 2.8K  
-RE2 0 Vem2 100  
-Q2 VColl2 Vbase2 Vem2 2N3904 
-.options TEMP=25
-R3 Vbase2 Vcc 28K  
-.INCLUDE Simulation.cmd
-RE1 0 Vem1 100  
-Q1 Vcoll1 Vbase1 Vem1 2N3904 
-R2 0 Vbase1 2K  
-Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K  
-C2 2 Vbase2 2.2uF  
-CE2 0 Vem2 1pF  
-C1 1 Vbase1 2.2uF  
-CE1 0 Vem1 1pF  
-R8 Vcoll1 2 1  
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K  
-RC1 Vcoll1 Vcc 3.3K  
-RL 0 Vout 100K  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include-output.net b/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include-output.net
deleted file mode 100644
index 6b45461..0000000
--- a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include-output.net
+++ /dev/null
@@ -1,32 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -I TwoStageAmp.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-.INCLUDE ./models/2N3904.mod
-*==============  Begin SPICE netlist of main design ============
-Cout VColl2 Vout 2.2uF  
-R5 Vin 1 10  
-R4 0 Vbase2 2.8K  
-RE2 0 Vem2 100  
-Q2 VColl2 Vbase2 Vem2 2N3904 
-.options TEMP=25
-R3 Vbase2 Vcc 28K  
-.INCLUDE Simulation.cmd
-RE1 0 Vem1 100  
-Q1 Vcoll1 Vbase1 Vem1 2N3904 
-R2 0 Vbase1 2K  
-Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K  
-C2 2 Vbase2 2.2uF  
-CE2 0 Vem2 1pF  
-C1 1 Vbase1 2.2uF  
-CE1 0 Vem1 1pF  
-R8 Vcoll1 2 1  
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K  
-RC1 Vcoll1 Vcc 3.3K  
-RL 0 Vout 100K  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include_longopt-output.net b/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include_longopt-output.net
deleted file mode 100644
index 6d70b90..0000000
--- a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Include_longopt-output.net
+++ /dev/null
@@ -1,32 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb --include TwoStageAmp.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-.INCLUDE ./models/2N3904.mod
-*==============  Begin SPICE netlist of main design ============
-Cout VColl2 Vout 2.2uF  
-R5 Vin 1 10  
-R4 0 Vbase2 2.8K  
-RE2 0 Vem2 100  
-Q2 VColl2 Vbase2 Vem2 2N3904 
-.options TEMP=25
-R3 Vbase2 Vcc 28K  
-.INCLUDE Simulation.cmd
-RE1 0 Vem1 100  
-Q1 Vcoll1 Vbase1 Vem1 2N3904 
-R2 0 Vbase1 2K  
-Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-R1 Vbase1 Vcc 28K  
-C2 2 Vbase2 2.2uF  
-CE2 0 Vem2 1pF  
-C1 1 Vbase1 2.2uF  
-CE1 0 Vem1 1pF  
-R8 Vcoll1 2 1  
-VCC Vcc 0 DC 15V
-RC2 VColl2 Vcc 1K  
-RC1 Vcoll1 Vcc 3.3K  
-RL 0 Vout 100K  
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort-output.net b/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort-output.net
deleted file mode 100644
index ed893be..0000000
--- a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort-output.net
+++ /dev/null
@@ -1,38 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb -s TwoStageAmp.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
-.model 2N3904   NPN(Stuff
-+               More stuff
-+               Yet more stuff
-+               Final line of stuff)
-*^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-C1 1 Vbase1 2.2uF  
-C2 2 Vbase2 2.2uF  
-CE1 0 Vem1 1pF  
-CE2 0 Vem2 1pF  
-Cout VColl2 Vout 2.2uF  
-Q1 Vcoll1 Vbase1 Vem1 2N3904 
-Q2 VColl2 Vbase2 Vem2 2N3904 
-R1 Vbase1 Vcc 28K  
-R2 0 Vbase1 2K  
-R3 Vbase2 Vcc 28K  
-R4 0 Vbase2 2.8K  
-R5 Vin 1 10  
-R8 Vcoll1 2 1  
-RC1 Vcoll1 Vcc 3.3K  
-RC2 VColl2 Vcc 1K  
-RE1 0 Vem1 100  
-RE2 0 Vem2 100  
-RL 0 Vout 100K  
-VCC Vcc 0 DC 15V
-Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-.INCLUDE Simulation.cmd
-.options TEMP=25
-.end
diff --git a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort_longopt-output.net b/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort_longopt-output.net
deleted file mode 100644
index 69a928e..0000000
--- a/gnetlist/tests/spice-sdb/outputs/TwoStageAmp_Sort_longopt-output.net
+++ /dev/null
@@ -1,38 +0,0 @@
-* ../../../src/gnetlist -g spice-sdb --sort TwoStageAmp.sch
-*********************************************************
-* Spice file generated by gnetlist                      *
-* spice-sdb version 4.28.2007 by SDB --                 *
-* provides advanced spice netlisting capability.        *
-* Documentation at http://www.brorson.com/gEDA/SPICE/   *
-*********************************************************
-*vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
-.model 2N3904   NPN(Stuff
-+               More stuff
-+               Yet more stuff
-+               Final line of stuff)
-*^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
-*
-*==============  Begin SPICE netlist of main design ============
-C1 1 Vbase1 2.2uF  
-C2 2 Vbase2 2.2uF  
-CE1 0 Vem1 1pF  
-CE2 0 Vem2 1pF  
-Cout VColl2 Vout 2.2uF  
-Q1 Vcoll1 Vbase1 Vem1 2N3904 
-Q2 VColl2 Vbase2 Vem2 2N3904 
-R1 Vbase1 Vcc 28K  
-R2 0 Vbase1 2K  
-R3 Vbase2 Vcc 28K  
-R4 0 Vbase2 2.8K  
-R5 Vin 1 10  
-R8 Vcoll1 2 1  
-RC1 Vcoll1 Vcc 3.3K  
-RC2 VColl2 Vcc 1K  
-RE1 0 Vem1 100  
-RE2 0 Vem2 100  
-RL 0 Vout 100K  
-VCC Vcc 0 DC 15V
-Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
-.INCLUDE Simulation.cmd
-.options TEMP=25
-.end
diff --git a/gnetlist/tests/spice-sdb/run_tests.sh b/gnetlist/tests/spice-sdb/run_tests.sh
deleted file mode 100755
index fe10f64..0000000
--- a/gnetlist/tests/spice-sdb/run_tests.sh
+++ /dev/null
@@ -1,242 +0,0 @@
-#!/bin/sh
-#
-# This script runs the tests called out for in test.list
-#
-
-regen=no
-
-usage() {
-cat << EOF
-
-$0 -- Testsuite program for spice-sdb
-
-Usage
-
-  $0 [-h | --help]
-  $0 [-r | --regen] [test1 [test2 [....]]]
-
-Options
-
-  -h | --help     Prints this help message and exits.
-
-  -r | --regen    Regenerates the reference files.  If you use
-                  this option, YOU MUST HAND VERIFY THE RESULTS
-                  BEFORE COMMITTING to the repository.
-
-Description
-
-$0 reads a file, tests.list,  describing tests to run on spice-sdb.
-If no specific test is specified on the $0 command line, then all 
-tests are run.
-
-Examples
-
-$0
-$0 --regen new_test 
-
-EOF
-}
-while test -n "$1"
-do
-    case "$1"
-    in
-
-    -h|--help)
-	usage
-	exit 0
-	;;
-
-    -r|--regen)
-	# regenerate the 'golden' output files.  Use this with caution.
-	# In particular, all differences should be noted and understood.
-	regen=yes
-	shift
-	;;
-
-    -*)
-	echo "unknown option: $1"
-	usage
-	exit 1
-	;;
-
-    *)
-	break
-	;;
-
-    esac
-done
-
-
-# make sure we have the right paths when running this from inside the
-# source tree and also from outside the source tree.
-here=`pwd`
-srcdir=${srcdir:-$here}
-srcdir=`cd $srcdir && pwd`
-
-GNETLIST=../../../src/gnetlist
-
-rundir=${here}/run
-
-GOLDEN_DIR=${srcdir}/outputs
-INPUT_DIR=${srcdir}/inputs
-
-TESTLIST=${srcdir}/tests.list
-
-if test ! -f $TESTLIST ; then
-    echo "ERROR: ($0)  Test list $TESTLIST does not exist"
-    exit 1
-fi
-
-# fail/pass/total counts
-fail=0
-pass=0
-skip=0
-tot=0
-
-# here's where we look at the test.list file and extract the names of all
-# the tests we want to run.
-if test -z "$1" ; then
-    all_tests=`awk 'BEGIN{FS="|"} /^#/{next} /^[ \t]*$/{next} {print $1}' $TESTLIST | sed 's; ;;g'`
-else
-    all_tests=$*
-fi
-echo All tests = $all_tests
-
-cat << EOF
-
-Starting tests in $here
-srcdir:     $srcdir
-INPUT_DIR:  ${INPUT_DIR}
-GOLDEN_DIR: ${GOLDEN_DIR}
-GNETLIST:   ${GNETLIST}
-all_tests:
-
-${all_tests}
-
-EOF
-
-# Now run through all tests in test.list, prepare the $rundir,
-# then run the tests. 
-for t in $all_tests ; do
-
-    # strip any leading garbage 
-    t=`echo $t | sed 's;^\*;;g'`
-
-    # figure out what files we need to copy for this test and what
-    # arguments to feed gnetlist 
-    schematics=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $2}'`
-    auxfiles=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $3}'`
-    args=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $4}'`
-    code=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $5}' | sed 's; ;;g'`
-    if test "X$code" = "X" ; then
-	code=0
-    fi
-    condition=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $6}' | sed 's; ;;g'`
-
-    echo "Schematics to copy   = $schematics"
-    echo "Args to copy         = $args"
-    echo "Expected return code = \"$code\""
-    if test "X$condition" != "X" ; then
-        eval "ctest=\`echo \$$condition\`"
-        if test X$ctest = "Xyes" ; then
-            echo "Running test because $condition = yes"
-        else
-            echo "Skipping test because $condition = $ctest"
-	    continue
-        fi
-    fi
-
-    tot=`expr $tot + 1`
-
-    # create temporary run directory and required subdirs
-    if test ! -d $rundir ; then
-	mkdir -p $rundir
-	mkdir -p $rundir/sym
-	mkdir -p $rundir/models
-    fi
-
-    # Create the files needed
-    # Note that we need to include not only the .sch files,
-    # but also the contents of the sym and model directories.
-    if test ! -z "$schematics" ; then
-	echo "Copying over schematics to run dir"
-	for f in $schematics ; do
-	    echo "cp ${INPUT_DIR}/${f} ${rundir}/${f}"
-	    cp ${INPUT_DIR}/${f} ${rundir}/${f}
-	    chmod 644 ${rundir}/${f}
-	done
-    fi
-    if test ! -z "$auxfiles" ; then
-	echo "Copying over aux files to run dir"
-	for f in $auxfiles ; do
-	    echo "cp ${INPUT_DIR}/${f} ${rundir}/${f}"
-	    cp ${INPUT_DIR}/${f} ${rundir}/${f}
-	    chmod 644 ${rundir}/${f}
-	done
-    fi
-
-    # run gnetlist -g spice-sdb
-    echo "${GNETLIST} -g spice-sdb $args $schematics"
-    cd ${rundir} && ${GNETLIST} -g spice-sdb $args $schematics 
-    rc=$?
-    if test $rc -ne $code ; then
-	echo "FAILED:  gnetlist -g spice-sdb returned $rc which did not match the expected $code"
-	fail=`expr $fail + 1`
-	continue
-    fi
-
-    # OK, now check results of run.
-    good=1
-    bad=0
-    soso=0
-
-    ref=${GOLDEN_DIR}/${t}-output.net
-    out=${rundir}/output.net
-    
-    if test "X$regen" = "Xyes" ; then
-	cp ${out} ${ref}
-	echo "Regenerated ${ref}"
-    elif test -f ${ref} ; then
-
-	sed '/gnetlist -g/d' ${ref} > ${out}.tmp1
-	sed '/gnetlist -g/d' ${out} > ${out}.tmp2
-
-	if diff -w ${out}.tmp1 ${out}.tmp2 >/dev/null ; then
-	    echo "PASS"
-	else
-	    echo "FAILED:  See diff -w ${ref} ${out}"
-	    fail=`expr $fail + 1`
-	    good=0
-	    bad=1
-	fi
-    else
-	echo "No reference file.  Skipping"
-	good=0
-	soso=1
-    fi
-
-    if test $soso -ne 0 ; then
-	good=0
-	bad=0
-    fi
-    pass=`expr $pass + $good`
-    fail=`expr $fail + $bad`
-    skip=`expr $skip + $soso`
-
-    cd $here
-    
-    # Delete the run directory in prep for the next test
-    rm -fr ${rundir}
-
-done
-
-echo "Passed $pass, failed $fail, skipped $skip out of $tot tests."
-
-rc=0
-if test $pass -ne $tot ; then
-    rc=`expr $tot - $pass`
-
-fi
-
-exit $rc
-
diff --git a/gnetlist/tests/spice-sdb/tests.list b/gnetlist/tests/spice-sdb/tests.list
deleted file mode 100644
index dfc9d69..0000000
--- a/gnetlist/tests/spice-sdb/tests.list
+++ /dev/null
@@ -1,36 +0,0 @@
-# Format:
-#
-# test_name | input schematics | aux files (gafrc, symbols, etc) | \ 
-# extra flags to pass to gnetlist -g spice-sdb | \
-# return code if non-zero expected | \
-# variable which must be set for the test to run
-#
-
-
-# -----------------------------------------
-# Simple netlisting tests
-# -----------------------------------------
-
-# The two stage amp
-TwoStageAmp | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | | 
-TwoStageAmp_Include | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | -I
-TwoStageAmp_Include_longopt | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | --include | | HAVE_GETOPT_LONG
-TwoStageAmp_Sort | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | -s
-TwoStageAmp_Sort_longopt | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | --sort | | HAVE_GETOPT_LONG
-
-# John Doty's test circuit
-# First test mangling
-JD | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | | 
-JD_Include | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -I
-JD_Sort | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -s
-# Now test non-munged version.
-JD_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | | -n
-JD_Include_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -I -n
-JD_Sort_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -s -n
-JD_nomunge_longopt | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | --nomunge | | HAVE_GETOPT_LONG
-JD_Include_nomunge_longopt | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -I --nomunge | | HAVE_GETOPT_LONG
-JD_Sort_nomunge_longopt | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -s --nomunge | | HAVE_GETOPT_LONG
-
-
-# Tests for slotted parts
-SlottedOpamps | SlottedOpamps.sch | gafrc sym/LM324_slotted-1.sym | |

commit 8a0e4e649e0aab8820fcca32214f99322788bc31
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sat May 31 17:43:08 2008 +0100

    Commit golden files from netlist backends as produced by gEDA 1.2.0
    
    We want to track changes in netlist backend behaviour since version 1.2.0,
    as changes in slotted part handling since then have caused unintended
    differences in outputs for some backends. We can explicitly confirm
    thoses changes as desired or tolerable by checking in new golden files.

diff --git a/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
index 573541a..d00491f 100644
--- a/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
+++ b/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
@@ -1 +1 @@
-0
+1
diff --git a/gnetlist/tests/common/outputs/drc2/cascade.retcode b/gnetlist/tests/common/outputs/drc2/cascade.retcode
index 573541a..d00491f 100644
--- a/gnetlist/tests/common/outputs/drc2/cascade.retcode
+++ b/gnetlist/tests/common/outputs/drc2/cascade.retcode
@@ -1 +1 @@
-0
+1
diff --git a/gnetlist/tests/common/outputs/drc2/netattrib.retcode b/gnetlist/tests/common/outputs/drc2/netattrib.retcode
index 573541a..d00491f 100644
--- a/gnetlist/tests/common/outputs/drc2/netattrib.retcode
+++ b/gnetlist/tests/common/outputs/drc2/netattrib.retcode
@@ -1 +1 @@
-0
+1
diff --git a/gnetlist/tests/common/outputs/drc2/powersupply.retcode b/gnetlist/tests/common/outputs/drc2/powersupply.retcode
index 573541a..d00491f 100644
--- a/gnetlist/tests/common/outputs/drc2/powersupply.retcode
+++ b/gnetlist/tests/common/outputs/drc2/powersupply.retcode
@@ -1 +1 @@
-0
+1
diff --git a/gnetlist/tests/common/outputs/drc2/singlenet.retcode b/gnetlist/tests/common/outputs/drc2/singlenet.retcode
index 573541a..d00491f 100644
--- a/gnetlist/tests/common/outputs/drc2/singlenet.retcode
+++ b/gnetlist/tests/common/outputs/drc2/singlenet.retcode
@@ -1 +1 @@
-0
+1
diff --git a/gnetlist/tests/common/outputs/pads/JD-output.net b/gnetlist/tests/common/outputs/pads/JD-output.net
index f3a5213..c4fc30c 100644
--- a/gnetlist/tests/common/outputs/pads/JD-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include-output.net b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
index f3a5213..c4fc30c 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
index f3a5213..c4fc30c 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
index f3a5213..c4fc30c 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
index f3a5213..c4fc30c 100644
--- a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
@@ -1,30 +1,30 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-CM	unknown
-A1	unknown
-RT	unknown
-M1	unknown
-X1	unknown
-RLP	unknown
-VDD	none
-RLM	unknown
-CP	unknown
-RB	unknown
-
-*NET*
-*SIGNAL* VDD1
- RLP.2 M1.B M1.S VDD.1 X1.6
-*SIGNAL* GND
- CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
-*SIGNAL* LVH
- RB.2 M1.D M1.G X1.3
-*SIGNAL* I
- V1.1 X1.1
-*SIGNAL* P
- CP.1 RT.1 RLP.1 X1.5
-*SIGNAL* M
- CM.1 RLM.1 RT.2 X1.4
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
index 2031be3..ec0991e 100644
--- a/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
@@ -1,26 +1,26 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-U1	unknown
-
-*NET*
-*SIGNAL* MINUSIN_SLOT4_PIN13_B
- U1.13
-*SIGNAL* PLUSIN_SLOT4_PIN12_A
- U1.12
-*SIGNAL* MINUSIN_SLOT3_PIN_B
- U1.9
-*SIGNAL* PLUSIN_SLOT3_PIN10_A
- U1.10
-*SIGNAL* MINUSIN_SLOT2_PIN6_B
- U1.6
-*SIGNAL* PLUSIN_SLOT2_PIN5_A
- U1.5
-*SIGNAL* SAMENET_OUTPUT_C
- U1.14 U1.8 U1.7 U1.1
-*SIGNAL* MINUSIN_SLOT1_PIN_B
- U1.2
-*SIGNAL* PLUSIN_SLOT1_PIN3_A
- U1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U1	unknown
+
+*NET*
+*SIGNAL* MINUSIN_SLOT4_PIN13_B
+ U1.13
+*SIGNAL* PLUSIN_SLOT4_PIN12_A
+ U1.12
+*SIGNAL* MINUSIN_SLOT3_PIN_B
+ U1.9
+*SIGNAL* PLUSIN_SLOT3_PIN10_A
+ U1.10
+*SIGNAL* MINUSIN_SLOT2_PIN6_B
+ U1.6
+*SIGNAL* PLUSIN_SLOT2_PIN5_A
+ U1.5
+*SIGNAL* SAMENET_OUTPUT_C
+ U1.14 U1.8 U1.7 U1.1
+*SIGNAL* MINUSIN_SLOT1_PIN_B
+ U1.2
+*SIGNAL* PLUSIN_SLOT1_PIN3_A
+ U1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
index f443d47..0295af5 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
index f443d47..0295af5 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
index f443d47..0295af5 100644
--- a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
@@ -1,54 +1,54 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-COUT	unknown
-R5	unknown
-R4	unknown
-RE2	unknown
-Q2	unknown
-A3	unknown
-R3	unknown
-A2	unknown
-RE1	unknown
-Q1	unknown
-A1	unknown
-R2	unknown
-VINPUT	none
-R1	unknown
-C2	unknown
-CE2	unknown
-C1	unknown
-CE1	unknown
-R8	unknown
-VCC	none
-RC2	unknown
-RC1	unknown
-RL	unknown
-
-*NET*
-*SIGNAL* UNNAMED_NET2
- C2.1 R8.2
-*SIGNAL* VBASE2
- R3.1 C2.2 R4.2 Q2.2
-*SIGNAL* VEM2
- CE2.2 RE2.2 Q2.1
-*SIGNAL* VOUT
- COUT.2 RL.2
-*SIGNAL* VCOLL2
- Q2.3 COUT.1 RC2.1
-*SIGNAL* GND
- R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
-*SIGNAL* VCC
- R3.2 RC1.2 VCC.1 RC2.2 R1.2
-*SIGNAL* VIN
- VINPUT.1 R5.1
-*SIGNAL* UNNAMED_NET1
- C1.1 R5.2
-*SIGNAL* VBASE1
- C1.2 R2.2 R1.1 Q1.2
-*SIGNAL* VEM1
- CE1.2 RE1.2 Q1.1
-*SIGNAL* VCOLL1
- R8.1 RC1.1 Q1.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/cascade-output.net b/gnetlist/tests/common/outputs/pads/cascade-output.net
index 52c4cd5..2643962 100644
--- a/gnetlist/tests/common/outputs/pads/cascade-output.net
+++ b/gnetlist/tests/common/outputs/pads/cascade-output.net
@@ -1,29 +1,29 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-AMP2	none
-AMP1	none
-SOURCE	none
-DEFAULTS	unknown
-MX1	none
-DEF1	none
-T1	none
-FL1	none
-
-*NET*
-*SIGNAL* UNNAMED_NET6
- AMP2.1 T1.2
-*SIGNAL* UNNAMED_NET5
- T1.1 MX1.2
-*SIGNAL* UNNAMED_NET4
- MX1.1 FL1.2
-*SIGNAL* UNNAMED_NET3
- FL1.1 DEF1.2
-*SIGNAL* UNNAMED_NET2
- DEF1.1 AMP1.2
-*SIGNAL* UNNAMED_NET1
- AMP1.1 SOURCE.1
-*SIGNAL* GND
- DEFAULTS.1
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+AMP2	none
+AMP1	none
+SOURCE	none
+DEFAULTS	unknown
+MX1	none
+DEF1	none
+T1	none
+FL1	none
+
+*NET*
+*SIGNAL* UNNAMED_NET6
+ AMP2.1 T1.2
+*SIGNAL* UNNAMED_NET5
+ T1.1 MX1.2
+*SIGNAL* UNNAMED_NET4
+ MX1.1 FL1.2
+*SIGNAL* UNNAMED_NET3
+ FL1.1 DEF1.2
+*SIGNAL* UNNAMED_NET2
+ DEF1.1 AMP1.2
+*SIGNAL* UNNAMED_NET1
+ AMP1.1 SOURCE.1
+*SIGNAL* GND
+ DEFAULTS.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/multiequal-output.net b/gnetlist/tests/common/outputs/pads/multiequal-output.net
index d325973..557fc85 100644
--- a/gnetlist/tests/common/outputs/pads/multiequal-output.net
+++ b/gnetlist/tests/common/outputs/pads/multiequal-output.net
@@ -1,14 +1,14 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-V1	none
-A1	unknown
-R1	unknown
-
-*NET*
-*SIGNAL* GND
- V1.2 R1.1
-*SIGNAL* UNNAMED_NET1
- V1.1 R1.2
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+A1	unknown
+R1	unknown
+
+*NET*
+*SIGNAL* GND
+ V1.2 R1.1
+*SIGNAL* UNNAMED_NET1
+ V1.1 R1.2
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/netattrib-output.net b/gnetlist/tests/common/outputs/pads/netattrib-output.net
index 332cf53..71d95b1 100644
--- a/gnetlist/tests/common/outputs/pads/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/pads/netattrib-output.net
@@ -1,21 +1,21 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-F1	unknown
-U100	DIP14
-U300	DIP14
-U200	DIP14
-
-*NET*
-*SIGNAL* UNNAMED_NET1
- U300.2
-*SIGNAL* NETATTRIB
- U200.2 U100.5
-*SIGNAL* GND
- U300.7 U200.7 U100.7
-*SIGNAL* VCC
- U300.14 U200.14 U100.14
-*SIGNAL* ONE
- F1.1 U300.1 U200.1 U100.3
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+U100	DIP14
+U300	DIP14
+U200	DIP14
+
+*NET*
+*SIGNAL* UNNAMED_NET1
+ U300.2
+*SIGNAL* NETATTRIB
+ U200.2 U100.5
+*SIGNAL* GND
+ U300.7 U200.7 U100.7
+*SIGNAL* VCC
+ U300.14 U200.14 U100.14
+*SIGNAL* ONE
+ F1.1 U300.1 U200.1 U100.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/powersupply-output.net b/gnetlist/tests/common/outputs/pads/powersupply-output.net
index 3aa5cd9..5200ae8 100644
--- a/gnetlist/tests/common/outputs/pads/powersupply-output.net
+++ b/gnetlist/tests/common/outputs/pads/powersupply-output.net
@@ -1,41 +1,41 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-F1	unknown
-R2	unknown
-CONN1	unknown
-C4	unknown
-R1	unknown
-C3	unknown
-C2	unknown
-S1	unknown
-C1	unknown
-T1	unknown
-U2	unknown
-U1	unknown
-
-*NET*
-*SIGNAL* TEN
- U2.1 R1.2 C3.1 R2.1
-*SIGNAL* ELEVEN
- U2.2 C4.1 R2.2
-*SIGNAL* GND
- CONN1.3
-*SIGNAL* ONE
- S1.1 CONN1.1
-*SIGNAL* FIVE
- CONN1.2 T1.2
-*SIGNAL* THREE
- T1.1 F1.2
-*SIGNAL* TWO
- S1.2 F1.1
-*SIGNAL* SIX
- T1.3 U1.4
-*SIGNAL* SEVEN
- T1.4 U1.3
-*SIGNAL* NINE
- C4.2 C3.2 R1.3 R1.1 C2.2 C1.2 U1.2
-*SIGNAL* EIGHT
- U2.3 C2.1 C1.1 U1.1
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+R2	unknown
+CONN1	unknown
+C4	unknown
+R1	unknown
+C3	unknown
+C2	unknown
+S1	unknown
+C1	unknown
+T1	unknown
+U2	unknown
+U1	unknown
+
+*NET*
+*SIGNAL* TEN
+ U2.1 R1.2 C3.1 R2.1
+*SIGNAL* ELEVEN
+ U2.2 C4.1 R2.2
+*SIGNAL* GND
+ CONN1.3
+*SIGNAL* ONE
+ S1.1 CONN1.1
+*SIGNAL* FIVE
+ CONN1.2 T1.2
+*SIGNAL* THREE
+ T1.1 F1.2
+*SIGNAL* TWO
+ S1.2 F1.1
+*SIGNAL* SIX
+ T1.3 U1.4
+*SIGNAL* SEVEN
+ T1.4 U1.3
+*SIGNAL* NINE
+ C4.2 C3.2 R1.3 R1.1 C2.2 C1.2 U1.2
+*SIGNAL* EIGHT
+ U2.3 C2.1 C1.1 U1.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/singlenet-output.net b/gnetlist/tests/common/outputs/pads/singlenet-output.net
index db44a14..a0bfde7 100644
--- a/gnetlist/tests/common/outputs/pads/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/pads/singlenet-output.net
@@ -1,16 +1,16 @@
-!PADS-POWERPCB-V3.0-MILS!
-
-*PART*
-U100	DIP14
-
-*NET*
-*SIGNAL* SING_N_2
- U100.1 U100.3
-*SIGNAL* GND
- U100.7
-*SIGNAL* VCC
- U100.14
-*SIGNAL* SING_N
- U100.4 U100.5 U100.10 U100.8 U100.9 U100.6
-
-*END*
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U100	DIP14
+
+*NET*
+*SIGNAL* SING_N_2
+ U100.1 U100.3
+*SIGNAL* GND
+ U100.7
+*SIGNAL* VCC
+ U100.14
+*SIGNAL* SING_N
+ U100.4 U100.5 U100.10 U100.8 U100.9 U100.6
+
+*END*
diff --git a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
index e571f05..391b789 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
@@ -6,8 +6,8 @@
 * Documentation at http://www.brorson.com/gEDA/SPICE/   *
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
-U1.4 samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a unknown
-U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
-U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
 U1.1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a unknown
+U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
+U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
+U1.4 samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a unknown
 .end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
index 775b16e..895c7bb 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
@@ -7,7 +7,7 @@
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
 F1 one unconnected_pin-3 <No valid value attribute found>
-U100 unconnected_pin-2 unconnected_pin-1 one unknown
-U300 one 1 unknown
-U200 one netattrib unknown
+U100.1 unconnected_pin-2 unconnected_pin-1 one unknown
+U300.1 one 1 unknown
+U200.1 one netattrib unknown
 .end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
index 21adb89..966f3f2 100644
--- a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
@@ -6,7 +6,7 @@
 * Documentation at http://www.brorson.com/gEDA/SPICE/   *
 *********************************************************
 *==============  Begin SPICE netlist of main design ============
-U100.3 SING_N SING_N SING_N unknown
-U100.2 SING_N SING_N SING_N unknown
-U100.1 SING_N_2 unconnected_pin-1 SING_N_2 unknown
+U100.1 SING_N_2 unconnected_pin-1 SING_N_2 SING_N SING_N unknown
+U100.2 SING_N SING_N SING_N SING_N unknown
+U100.3 unknown
 .end
diff --git a/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
index c73d322..a5f6fdb 100644
--- a/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
@@ -1,3 +1,3 @@
 * Spice netlister for gnetlist
-U1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+U1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a <No valid value attribute found>
 .END
diff --git a/gnetlist/tests/common/outputs/spice/singlenet-output.net b/gnetlist/tests/common/outputs/spice/singlenet-output.net
index 4667f91..b19effc 100644
--- a/gnetlist/tests/common/outputs/spice/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/spice/singlenet-output.net
@@ -1,3 +1,3 @@
 * Spice netlister for gnetlist
-U100 SING_N SING_N SING_N ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+U100 SING_N_2 unconnected_pin-1 SING_N_2 SING_N SING_N SING_N SING_N SING_N SING_N ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
 .END
diff --git a/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
index 663c0e3..fbf59df 100644
--- a/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
+++ b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
@@ -2,7 +2,7 @@
 % Written by Matthew Ettus
 % Based on code by Bas Gieltjes
 CKT
-	error	7 8 9 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U1
+	error	7 8 9 7 5 6 7 3 4 7 1 2 	% U1
 	DEF2P	#<unspecified>  #<unspecified>
 	TERM	50 50
 
diff --git a/gnetlist/tests/common/outputs/vipec/singlenet-output.net b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
index 53b7251..0da0f66 100644
--- a/gnetlist/tests/common/outputs/vipec/singlenet-output.net
+++ b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
@@ -2,7 +2,7 @@
 % Written by Matthew Ettus
 % Based on code by Bas Gieltjes
 CKT
-	error	3 3 3 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U100
+	error	1 #<unspecified> 1 3 3 3 3 3 3 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U100
 	DEF2P	#<unspecified>  #<unspecified>
 	TERM	50 50
 

commit dc5a2e6b352ac4e5833ec86c0685da747362e04a
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Wed Feb 13 16:47:40 2008 +0000

    Add a common set of tests to gnetlist evolved from the spice-sdb tests.
    
    The tests are applied to all backends, with control files being used to
    document the expected return codes, and golden files with the expected
    output. These files are generated from a 1.5.0 development release of
    of the gEDA suite, and do not in all cases represent "correct" behaviour,
    merely "gEDA 1.5.0" behaviour.

diff --git a/gnetlist/configure.ac b/gnetlist/configure.ac
index c03a1d0..0fbdb9b 100644
--- a/gnetlist/configure.ac
+++ b/gnetlist/configure.ac
@@ -441,6 +441,45 @@ AC_CONFIG_FILES([Makefile
 		 tests/spice-sdb/inputs/sym/Makefile
 		 tests/spice-sdb/inputs/models/Makefile
 		 tests/spice-sdb/outputs/Makefile
+		 tests/common/Makefile
+		 tests/common/outputs/osmond/Makefile
+		 tests/common/outputs/pcbpins/Makefile
+		 tests/common/outputs/redac/Makefile
+		 tests/common/outputs/switcap/Makefile
+		 tests/common/outputs/futurenet2/Makefile
+		 tests/common/outputs/mathematica/Makefile
+		 tests/common/outputs/bom/Makefile
+		 tests/common/outputs/verilog/Makefile
+		 tests/common/outputs/cascade/Makefile
+		 tests/common/outputs/partslist1/Makefile
+		 tests/common/outputs/spice/Makefile
+		 tests/common/outputs/drc2/Makefile
+		 tests/common/outputs/geda/Makefile
+		 tests/common/outputs/gossip/Makefile
+		 tests/common/outputs/systemc/Makefile
+		 tests/common/outputs/pads/Makefile
+		 tests/common/outputs/vams/Makefile
+		 tests/common/outputs/Makefile
+		 tests/common/outputs/partslist2/Makefile
+		 tests/common/outputs/PCBboard/Makefile
+		 tests/common/outputs/bae/Makefile
+		 tests/common/outputs/vipec/Makefile
+		 tests/common/outputs/eagle/Makefile
+		 tests/common/outputs/protelII/Makefile
+		 tests/common/outputs/PCB/Makefile
+		 tests/common/outputs/gsch2pcb/Makefile
+		 tests/common/outputs/vhdl/Makefile
+		 tests/common/outputs/calay/Makefile
+		 tests/common/outputs/tango/Makefile
+		 tests/common/outputs/spice-sdb/Makefile
+		 tests/common/outputs/maxascii/Makefile
+		 tests/common/outputs/bom2/Makefile
+		 tests/common/outputs/drc/Makefile
+		 tests/common/outputs/partslist3/Makefile
+		 tests/common/outputs/allegro/Makefile
+		 tests/common/inputs/models/Makefile
+		 tests/common/inputs/Makefile
+		 tests/common/inputs/sym/Makefile
 		 docs/Makefile 
 		 docs/vams/Makefile 
 		 examples/vams/Makefile 
diff --git a/gnetlist/tests/Makefile.am b/gnetlist/tests/Makefile.am
index 682ac99..1f4b468 100644
--- a/gnetlist/tests/Makefile.am
+++ b/gnetlist/tests/Makefile.am
@@ -1,6 +1,6 @@
 ## Process this file with automake to produce Makefile.in
 
-SUBDIRS = hierarchy hierarchy2 drc2 spice-sdb
+SUBDIRS = hierarchy hierarchy2 drc2 spice-sdb common
 
 EXTRA_DIST = runtest.sh \
 	     7447.vhdl README amp.spice cascade.sch cascade.cascade \
diff --git a/gnetlist/tests/common/.gitignore b/gnetlist/tests/common/.gitignore
new file mode 100644
index 0000000..af1e4c0
--- /dev/null
+++ b/gnetlist/tests/common/.gitignore
@@ -0,0 +1,4 @@
+Makefile
+Makefile.in
+*~
+*.log
diff --git a/gnetlist/tests/common/Makefile.am b/gnetlist/tests/common/Makefile.am
new file mode 100644
index 0000000..161a210
--- /dev/null
+++ b/gnetlist/tests/common/Makefile.am
@@ -0,0 +1,15 @@
+## $Id$
+##
+
+SUBDIRS= inputs outputs
+
+TESTS_ENVIRONMENT= PERL=${PERL}
+
+RUN_TESTS= run_tests.sh
+
+check_SCRIPTS= ${RUN_TESTS}
+
+TESTS= ${RUN_TESTS}
+
+EXTRA_DIST= run_backend_tests.sh ${RUN_TESTS} tests.list backends.list always-copy.list
+CLEANFILES= *.log
diff --git a/gnetlist/tests/common/always-copy.list b/gnetlist/tests/common/always-copy.list
new file mode 100644
index 0000000..aee1abb
--- /dev/null
+++ b/gnetlist/tests/common/always-copy.list
@@ -0,0 +1 @@
+attribs
diff --git a/gnetlist/tests/common/backends.list b/gnetlist/tests/common/backends.list
new file mode 100644
index 0000000..780f618
--- /dev/null
+++ b/gnetlist/tests/common/backends.list
@@ -0,0 +1,34 @@
+allegro
+bae
+bom2
+bom
+calay
+cascade
+drc2
+drc
+eagle
+futurenet2
+geda
+gossip
+gsch2pcb
+mathematica
+maxascii
+osmond
+pads
+partslist1
+partslist2
+partslist3
+PCBboard
+pcbpins
+PCB
+protelII
+redac
+spice
+spice-sdb
+switcap
+systemc
+tango
+vams
+verilog
+vhdl
+vipec
diff --git a/gnetlist/tests/common/inputs/.gitignore b/gnetlist/tests/common/inputs/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/inputs/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/inputs/LVDfoo.sch b/gnetlist/tests/common/inputs/LVDfoo.sch
new file mode 100644
index 0000000..419a0e6
--- /dev/null
+++ b/gnetlist/tests/common/inputs/LVDfoo.sch
@@ -0,0 +1,160 @@
+v 20070216 1
+C 8700 85500 1 0 0 LVD.sym
+{
+T 9700 84500 5 10 1 1 0 0 1
+refdes=X1
+T 9600 84300 5 10 1 1 0 0 1
+model-name=unknown_LVD
+}
+C 9300 86500 1 0 0 asic-pmos-1.sym
+{
+T 10100 87300 5 10 1 1 0 0 1
+refdes=M1
+T 10100 87100 5 8 1 1 0 0 1
+model-name=pch
+T 10100 86800 5 8 1 0 0 0 1
+w=3u
+T 10100 86600 5 8 1 0 0 0 1
+l=3u
+T 10700 86700 5 10 1 0 0 0 1
+m=36
+}
+N 9300 85500 9300 87000 4
+N 9300 86500 11300 86500 4
+{
+T 11400 86500 5 10 1 1 0 0 1
+netname=LVH
+}
+N 10000 87000 10000 87500 4
+N 9900 87500 9900 88200 4
+{
+T 10100 88200 5 10 1 1 0 0 1
+netname=Vdd1
+}
+C 8400 86900 1 0 0 resistor-1.sym
+{
+T 8600 87200 5 10 1 1 0 0 1
+refdes=Rb
+T 8700 86700 5 10 1 1 0 0 1
+value=5.6k
+T 8400 86900 5 10 1 1 0 0 1
+device=RESISTOR
+}
+C 7900 86500 1 0 0 gnd-1.sym
+C 10800 84900 1 0 0 resistor-1.sym
+{
+T 11000 85200 5 10 1 1 0 0 1
+refdes=Rt
+T 11500 85200 5 10 1 1 0 0 1
+value=1k
+}
+N 9500 85500 9500 86300 4
+N 9900 84800 12600 84800 4
+{
+T 12700 84800 5 10 1 1 0 0 1
+netname=m
+}
+N 9900 85200 9900 85600 4
+N 9900 85600 12600 85600 4
+{
+T 12700 85600 5 10 1 1 0 0 1
+netname=p
+}
+N 11700 85000 11700 84800 4
+C 6800 83300 1 0 0 vpulse-1.sym
+{
+T 7500 83950 5 10 1 1 0 0 1
+refdes=V1
+T 7500 83750 5 10 1 1 0 0 1
+value=pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+}
+C 7000 82700 1 0 0 gnd-1.sym
+N 8700 85000 7100 85000 4
+{
+T 7700 85100 5 10 1 1 0 0 1
+netname=i
+}
+N 7100 85000 7100 84500 4
+C 13200 84800 1 0 0 vdc-1.sym
+{
+T 13900 85450 5 10 1 1 0 0 1
+refdes=Vdd
+T 13900 85250 5 10 1 1 0 0 1
+value=DC 3.3V
+}
+C 13400 84200 1 0 0 gnd-1.sym
+N 9900 87500 13500 87500 4
+N 13500 87500 13500 86000 4
+N 9500 86300 13500 86300 4
+C 10800 83900 1 0 0 resistor-1.sym
+{
+T 11000 84200 5 10 1 1 0 0 1
+refdes=Rlm
+T 11500 84200 5 10 1 1 0 0 1
+value=500k
+}
+C 11600 83300 1 0 0 gnd-1.sym
+N 10800 84000 10800 84800 4
+C 11100 85800 1 0 0 resistor-1.sym
+{
+T 11300 86100 5 10 1 1 0 0 1
+refdes=Rlp
+T 11800 86100 5 10 1 1 0 0 1
+value=1meg
+}
+N 12000 85900 13200 85900 4
+N 13200 85900 13200 86100 4
+N 13200 86100 13500 86100 4
+N 11100 85900 11100 85600 4
+C 9200 84000 1 0 0 gnd-1.sym
+C 9400 84000 1 0 0 gnd-1.sym
+N 10800 85000 10800 85600 4
+C 12700 83400 1 0 0 capacitor-1.sym
+{
+T 12900 83900 5 10 1 1 0 0 1
+refdes=Cp
+T 12900 84300 5 10 0 0 0 0 1
+symversion=0.1
+T 12700 83400 5 10 1 1 0 0 1
+value=20p
+}
+C 12700 82600 1 0 0 capacitor-1.sym
+{
+T 12900 83100 5 10 1 1 0 0 1
+refdes=Cm
+T 12900 83500 5 10 0 0 0 0 1
+symversion=0.1
+T 12700 82600 5 10 1 1 0 0 1
+value=20p
+T 12700 82600 5 10 1 1 0 0 1
+device=CAPACITOR
+}
+C 14000 83100 1 0 0 gnd-1.sym
+C 14000 82300 1 0 0 gnd-1.sym
+N 12700 83600 12300 83600 4
+N 12300 83600 12300 85600 4
+N 12700 82800 12100 82800 4
+C 5200 80400 0 0 0 title-bordered-A.sym
+N 8400 87000 8000 87000 4
+N 8000 87000 8000 86800 4
+N 9500 84300 9500 84500 4
+N 9300 84500 9300 84300 4
+N 12100 82800 12100 84800 4
+N 13500 84500 13500 84800 4
+N 7100 83300 7100 83000 4
+N 11700 84000 11700 83600 4
+N 13600 83600 14100 83600 4
+N 14100 83600 14100 83400 4
+N 13600 82800 14100 82800 4
+N 14100 82800 14100 82600 4
+C 5800 87400 1 0 0 spice-model-1.sym
+{
+T 5900 88100 5 10 0 1 0 0 1
+device=model
+T 5900 88000 5 10 1 1 0 0 1
+refdes=A1
+T 7100 87700 5 10 1 1 0 0 1
+model-name=unknown_LVD
+T 6300 87500 5 10 1 1 0 0 1
+file=./models/openIP_5.cir
+}
diff --git a/gnetlist/tests/common/inputs/Makefile.am b/gnetlist/tests/common/inputs/Makefile.am
new file mode 100644
index 0000000..8add101
--- /dev/null
+++ b/gnetlist/tests/common/inputs/Makefile.am
@@ -0,0 +1,14 @@
+SUBDIRS = models sym
+
+EXTRA_DIST= \
+     gafrc \
+     LVDfoo.sch \
+     Simulation.cmd \
+     TwoStageAmp.sch \
+     SlottedOpamps.sch \
+     cascade.sch \
+     multiequal.sch \
+     netattrib.sch \
+     powersupply.sch \
+     singlenet.sch \
+     attribs
diff --git a/gnetlist/tests/common/inputs/Simulation.cmd b/gnetlist/tests/common/inputs/Simulation.cmd
new file mode 100644
index 0000000..8e6e522
--- /dev/null
+++ b/gnetlist/tests/common/inputs/Simulation.cmd
@@ -0,0 +1,5 @@
+.OP
+.AC DEC 20 1Hz 100MegHz
+* .DC Vinput 0 5 .01
+* .DC Vinput 1 2 .01
+
diff --git a/gnetlist/tests/common/inputs/SlottedOpamps.sch b/gnetlist/tests/common/inputs/SlottedOpamps.sch
new file mode 100644
index 0000000..3eeaf01
--- /dev/null
+++ b/gnetlist/tests/common/inputs/SlottedOpamps.sch
@@ -0,0 +1,98 @@
+v 20070216 1
+C 40000 40000 0 0 0 title-B.sym
+C 46500 48100 1 0 0 LM324_slotted-1.sym
+{
+T 47325 48250 5 8 0 0 0 0 1
+device=LM324
+T 46700 49000 5 10 1 1 0 0 1
+refdes=U1
+T 46500 48100 5 10 1 0 0 0 1
+slot=1
+}
+C 46500 46000 1 0 0 LM324_slotted-1.sym
+{
+T 47325 46150 5 8 0 0 0 0 1
+device=LM324
+T 46700 46900 5 10 1 1 0 0 1
+refdes=U1
+T 46500 46000 5 10 1 0 0 0 1
+slot=2
+}
+C 46500 44200 1 0 0 LM324_slotted-1.sym
+{
+T 47325 44350 5 8 0 0 0 0 1
+device=LM324
+T 46700 45100 5 10 1 1 0 0 1
+refdes=U1
+T 46500 44200 5 10 1 0 0 0 1
+slot=3
+}
+C 46500 42100 1 0 0 LM324_slotted-1.sym
+{
+T 47325 42250 5 8 0 0 0 0 1
+device=LM324
+T 46700 43000 5 10 1 1 0 0 1
+refdes=U1
+T 46500 42100 5 10 1 0 0 0 1
+slot=4
+}
+N 46600 48700 45400 48700 4
+{
+T 44000 48800 5 10 1 0 0 0 1
+netname=plusin_slot1_pin3_a
+}
+N 46500 46600 45300 46600 4
+{
+T 43900 46700 5 10 1 0 0 0 1
+netname=plusin_slot2_pin5_a
+}
+N 46500 44800 45300 44800 4
+{
+T 43900 44900 5 10 1 0 0 0 1
+netname=plusin_slot3_pin10_a
+}
+N 46500 42700 45300 42700 4
+{
+T 43900 42800 5 10 1 0 0 0 1
+netname=plusin_slot4_pin12_a
+}
+N 46500 48300 45300 48300 4
+{
+T 43900 48400 5 10 1 0 0 0 1
+netname=minusin_slot1_pin_b
+}
+N 46500 46200 45300 46200 4
+{
+T 43900 46300 5 10 1 0 0 0 1
+netname=minusin_slot2_pin6_b
+}
+N 46500 44400 45300 44400 4
+{
+T 43900 44500 5 10 1 0 0 0 1
+netname=minusin_slot3_pin_b
+}
+N 46500 42300 45300 42300 4
+{
+T 43900 42400 5 10 1 0 0 0 1
+netname=minusin_slot4_pin13_b
+}
+N 47500 48500 48900 48500 4
+{
+T 47500 48600 5 10 1 0 0 0 1
+netname=samenet_output_c
+}
+N 47500 46400 48900 46400 4
+{
+T 47500 46500 5 10 1 0 0 0 1
+netname=samenet_output_c
+}
+N 47500 44600 48900 44600 4
+{
+T 47500 44700 5 10 1 0 0 0 1
+netname=samenet_output_c
+}
+N 47500 42500 48900 42500 4
+{
+T 47500 42600 5 10 1 0 0 0 1
+netname=samenet_output_c
+}
diff --git a/gnetlist/tests/common/inputs/TwoStageAmp.sch b/gnetlist/tests/common/inputs/TwoStageAmp.sch
new file mode 100644
index 0000000..473a990
--- /dev/null
+++ b/gnetlist/tests/common/inputs/TwoStageAmp.sch
@@ -0,0 +1,313 @@
+v 20070216 1
+C 31900 49200 1 0 0 transistor.sym
+{
+T 32800 49700 5 10 1 1 0 0 1
+refdes=Q1
+T 32800 49900 5 10 1 1 0 0 1
+model-name=2N3904
+T 32800 49900 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+}
+C 28100 49600 1 0 0 resistor-1.sym
+{
+T 28300 49900 5 10 1 1 0 0 1
+refdes=R5
+T 28400 49400 5 10 1 1 0 0 1
+value=10
+T 28400 50000 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 31100 49900 1 90 0 resistor-1.sym
+{
+T 31400 50700 5 10 1 1 180 0 1
+refdes=R1
+T 31200 50200 5 10 1 1 0 0 1
+value=28K
+T 31400 50300 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 31600 48200 1 90 0 resistor-1.sym
+{
+T 31900 48900 5 10 1 1 180 0 1
+refdes=R2
+T 31600 48200 5 10 1 1 0 0 1
+value=2K
+T 31900 48600 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 32600 47900 1 90 0 resistor-1.sym
+{
+T 33000 48600 5 10 1 1 180 0 1
+refdes=RE1
+T 32600 47900 5 10 1 1 0 0 1
+value=100
+T 32900 48300 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 38000 54600 1 90 0 resistor-1.sym
+{
+T 38400 55300 5 10 1 1 180 0 1
+refdes=RC2
+T 38000 54600 5 10 1 1 0 0 1
+value=1K
+T 38300 55000 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 40800 52200 1 90 0 resistor-1.sym
+{
+T 41100 53100 5 10 1 1 180 0 1
+refdes=RL
+T 40800 52200 5 10 1 1 0 0 1
+value=100K
+T 41100 52600 5 10 0 0 0 0 1
+device=RESISTOR
+}
+N 32500 49200 32500 48800 4
+C 39300 53900 1 0 0 capacitor-1.sym
+{
+T 39500 54400 5 10 1 1 0 0 1
+refdes=Cout
+T 39500 53700 5 10 1 1 0 0 1
+value=2.2uF
+T 39500 54600 5 10 0 0 0 0 1
+device=CAPACITOR
+T 39500 54800 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 33700 47900 1 90 0 capacitor-1.sym
+{
+T 34100 48600 5 10 1 1 180 0 1
+refdes=CE1
+T 33700 47900 5 10 1 1 0 0 1
+value=1pF
+T 33900 48600 5 10 0 0 0 0 1
+device=CAPACITOR
+T 33900 48800 5 10 0 0 0 0 1
+symversion=0.1
+}
+N 33500 48800 33500 49100 4
+N 39300 54100 37900 54100 4
+{
+T 38000 53800 5 10 1 1 0 0 1
+netname=VColl2
+}
+N 40700 54100 40700 53100 4
+C 31400 47400 1 0 0 gnd-1.sym
+C 32400 47400 1 0 0 gnd-1.sym
+C 33400 47400 1 0 0 gnd-1.sym
+C 40600 51200 1 0 0 gnd-1.sym
+C 27200 48300 1 0 0 vsin-1.sym
+{
+T 27900 48950 5 10 1 1 0 0 1
+refdes=Vinput
+T 26800 48150 5 10 1 1 0 0 1
+value=DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+T 27900 49150 5 10 0 0 0 0 1
+device=vsin
+T 27900 49350 5 10 0 0 0 0 1
+footprint=none
+}
+C 40700 48700 1 0 0 vdc-1.sym
+{
+T 41400 49350 5 10 1 1 0 0 1
+refdes=VCC
+T 41400 49150 5 10 1 1 0 0 1
+value=DC 15V
+T 41400 49550 5 10 0 0 0 0 1
+device=VOLTAGE_SOURCE
+T 41400 49750 5 10 0 0 0 0 1
+footprint=none
+}
+C 40800 50100 1 0 0 vcc-1.sym
+C 37700 55700 1 0 0 vcc-1.sym
+N 37900 55700 37900 55500 4
+N 41000 50100 41000 49900 4
+C 40900 48200 1 0 0 gnd-1.sym
+C 27400 47600 1 0 0 gnd-1.sym
+N 27500 48300 27500 47900 4
+N 27500 49700 27500 49500 4
+N 31500 48200 31500 47700 4
+N 32500 47900 32500 47700 4
+N 33500 47900 33500 47700 4
+N 40700 52200 40700 51500 4
+N 41000 48700 41000 48500 4
+N 40200 54100 41300 54100 4
+{
+T 41500 54100 5 10 1 1 0 0 1
+netname=Vout
+}
+C 26000 46000 0 0 0 title-B.sym
+C 26500 55500 1 0 0 spice-model-1.sym
+{
+T 26600 56100 5 10 1 1 0 0 1
+refdes=A1
+T 27800 55800 5 10 1 1 0 0 1
+model-name=2N3904
+T 27000 55600 5 10 1 1 0 0 1
+file=./models/2N3904.mod
+T 26600 56200 5 10 0 1 0 0 1
+device=model
+}
+C 26500 54600 1 0 0 spice-include-1.sym
+{
+T 26600 55000 5 10 1 1 0 0 1
+refdes=A2
+T 27000 54700 5 10 1 1 0 0 1
+file=Simulation.cmd
+T 26600 54900 5 10 0 1 0 0 1
+device=include
+}
+C 26500 53700 1 0 0 spice-directive-1.sym
+{
+T 26600 54100 5 10 1 1 0 0 1
+refdes=A3
+T 26600 53800 5 10 1 1 0 0 1
+value=.options TEMP=25
+T 26600 54000 5 10 0 1 0 0 1
+device=directive
+T 26600 53800 5 10 1 1 0 0 1
+file=?
+}
+N 27000 49700 28100 49700 4
+{
+T 26700 49700 5 10 1 1 0 0 1
+netname=Vin
+}
+N 31000 49900 31000 49700 4
+N 31500 49100 31500 49700 4
+C 29400 49500 1 0 0 capacitor-1.sym
+{
+T 29600 50000 5 10 1 1 0 0 1
+refdes=C1
+T 29500 49300 5 10 1 1 0 0 1
+value=2.2uF
+T 29600 50200 5 10 0 0 0 0 1
+device=CAPACITOR
+T 29600 50400 5 10 0 0 0 0 1
+symversion=0.1
+}
+N 29000 49700 29400 49700 4
+C 37300 52600 1 0 0 transistor.sym
+{
+T 38200 53100 5 10 1 1 0 0 1
+refdes=Q2
+T 38200 52700 5 10 1 1 0 0 1
+model-name=2N3904
+T 38200 53300 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+}
+C 37800 48900 1 0 0 gnd-1.sym
+N 37900 53600 37900 54600 4
+C 30800 51000 1 0 0 vcc-1.sym
+N 31000 50800 31000 51000 4
+T 36100 46800 9 20 1 0 0 0 1
+Two stage amplifier SPICE playpen
+T 40000 46100 9 10 1 0 0 0 1
+Stuart Brorson -- sdb@xxxxxxxxxx
+C 32600 53500 1 90 0 resistor-1.sym
+{
+T 32900 54400 5 10 1 1 180 0 1
+refdes=RC1
+T 32600 53500 5 10 1 1 0 0 1
+value=3.3K
+T 32900 53900 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 38000 49500 1 90 0 resistor-1.sym
+{
+T 38500 50300 5 10 1 1 180 0 1
+refdes=RE2
+T 38000 49500 5 10 1 1 0 0 1
+value=100
+T 38300 49900 5 10 0 0 0 0 1
+device=RESISTOR
+}
+N 37900 49200 37900 49500 4
+N 37900 50400 37900 52600 4
+N 32500 50200 32500 53500 4
+C 32300 54800 1 0 0 vcc-1.sym
+N 32500 54400 32500 54800 4
+N 30300 49700 31900 49700 4
+{
+T 30700 49500 5 10 1 1 0 0 1
+netname=Vbase1
+}
+C 39200 49500 1 90 0 capacitor-1.sym
+{
+T 39600 50200 5 10 1 1 180 0 1
+refdes=CE2
+T 39200 49500 5 10 1 1 0 0 1
+value=1pF
+T 39400 50200 5 10 0 0 0 0 1
+device=CAPACITOR
+T 39400 50400 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 38900 48900 1 0 0 gnd-1.sym
+N 39000 49500 39000 49200 4
+N 39000 50400 39000 51000 4
+N 39000 51000 37900 51000 4
+{
+T 38000 51100 5 10 1 1 0 0 1
+netname=Vem2
+}
+N 32500 49100 33500 49100 4
+{
+T 32700 49200 5 10 1 1 0 0 1
+netname=Vem1
+}
+C 33300 53000 1 0 0 resistor-1.sym
+{
+T 33500 53300 5 10 1 1 0 0 1
+refdes=R8
+T 33500 52700 5 10 1 1 0 0 1
+value=1
+T 33600 53400 5 10 0 0 0 0 1
+device=RESISTOR
+}
+N 35900 53100 37300 53100 4
+{
+T 36800 52900 5 10 1 1 0 0 1
+netname=Vbase2
+}
+N 32500 53100 33300 53100 4
+{
+T 32600 52900 5 10 1 1 0 0 1
+netname=Vcoll1
+}
+C 36700 54700 1 90 0 resistor-1.sym
+{
+T 37000 55500 5 10 1 1 180 0 1
+refdes=R3
+T 36800 55000 5 10 1 1 0 0 1
+value=28K
+T 37000 55100 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 36400 51600 1 90 0 resistor-1.sym
+{
+T 36700 52300 5 10 1 1 180 0 1
+refdes=R4
+T 36400 51600 5 10 1 1 0 0 1
+value=2.8K
+T 36700 52000 5 10 0 0 0 0 1
+device=RESISTOR
+}
+C 36200 50800 1 0 0 gnd-1.sym
+N 36300 51600 36300 51100 4
+N 36300 52500 36300 53100 4
+C 36400 55800 1 0 0 vcc-1.sym
+N 36600 55600 36600 55800 4
+C 35000 52900 1 0 0 capacitor-1.sym
+{
+T 35200 53400 5 10 1 1 0 0 1
+refdes=C2
+T 35100 52700 5 10 1 1 0 0 1
+value=2.2uF
+T 35200 53600 5 10 0 0 0 0 1
+device=CAPACITOR
+T 35200 53800 5 10 0 0 0 0 1
+symversion=0.1
+}
+N 35000 53100 34200 53100 4
+N 36600 53100 36600 54700 4
diff --git a/gnetlist/tests/common/inputs/attribs b/gnetlist/tests/common/inputs/attribs
new file mode 100644
index 0000000..12527f4
--- /dev/null
+++ b/gnetlist/tests/common/inputs/attribs
@@ -0,0 +1,3 @@
+refdes
+value
+device
diff --git a/gnetlist/tests/common/inputs/cascade.sch b/gnetlist/tests/common/inputs/cascade.sch
new file mode 100644
index 0000000..8d91db9
--- /dev/null
+++ b/gnetlist/tests/common/inputs/cascade.sch
@@ -0,0 +1,126 @@
+v 20070526 1
+C 40000 40000 0 0 0 title-B.sym
+C 41300 48800 1 0 0 cascade-defaults-2.sym
+{
+T 43100 52200 5 10 0 1 0 0 1
+device=cascade-defaults-top
+T 41400 48900 5 10 1 1 0 0 1
+refdes=DEFAULTS
+T 41500 49500 5 10 1 0 0 0 1
+RIN=50
+T 42900 49500 5 10 1 0 0 0 1
+ROUT=50
+T 44500 49500 5 10 1 0 0 0 1
+RHO=0
+}
+C 40800 46000 1 0 0 cascade-source-1.sym
+{
+T 39600 45900 5 10 0 0 0 0 1
+device=cascade-source
+T 40900 47300 5 10 1 1 0 0 1
+refdes=SOURCE
+T 40100 46200 5 10 0 1 0 0 1
+footprint=none
+T 40900 46400 5 10 1 0 0 0 1
+C=0
+T 40900 46200 5 10 1 0 0 0 1
+CN=70
+T 40900 46000 5 10 1 0 0 0 1
+BW=1
+}
+C 42500 46100 1 0 0 cascade-amp-1.sym
+{
+T 42425 46650 5 8 0 0 0 0 1
+device=cascade-amp
+T 42700 47500 5 10 1 1 0 0 1
+refdes=AMP1
+T 42100 46400 5 10 0 1 0 0 1
+footprint=none
+T 42800 46500 5 10 1 0 0 0 1
+G=12
+T 42800 46300 5 10 1 0 0 0 1
+NF=5
+T 42800 46100 5 10 1 0 0 0 1
+IIP3=-2
+}
+C 44000 46600 1 0 0 cascade-defaults-1.sym
+{
+T 44525 47550 5 8 0 0 0 0 1
+device=cascade-defaults
+T 44200 47700 5 10 1 1 0 0 1
+refdes=DEF1
+T 44300 47200 5 10 1 0 0 1 1
+RIN=50
+T 44300 47000 5 10 1 0 0 1 1
+ROUT=50
+T 44300 46800 5 10 1 0 0 1 1
+RHO=0.2
+T 44000 46600 5 10 0 1 0 0 1
+footprint=none
+}
+C 46500 46200 1 0 0 cascade-filter-1.sym
+{
+T 46700 47700 5 10 0 0 0 0 1
+footprint=none
+T 44700 44850 5 10 0 1 0 0 1
+device=cascade-filter
+T 46800 47500 5 10 1 1 0 0 1
+refdes=FL1
+T 46900 46400 5 10 1 0 0 0 1
+G=-5.5
+T 46900 46200 5 10 1 0 0 0 1
+NF=5.5
+}
+C 48500 45800 1 0 0 cascade-mixer-1.sym
+{
+T 49000 47400 5 10 0 0 0 0 1
+footprint=none
+T 47300 45650 5 10 0 1 0 0 1
+device=cascade-mixer
+T 48800 47600 5 10 1 1 0 0 1
+refdes=MX1
+T 49000 46200 5 10 1 0 0 0 1
+G=12
+T 49000 46000 5 10 1 0 0 0 1
+NF=15
+T 49000 45800 5 10 1 0 0 0 1
+IIP3=5
+}
+C 50500 45100 1 0 0 cascade-transformer-1.sym
+{
+T 50800 47150 5 10 1 1 0 0 1
+refdes=T1
+T 49200 45550 5 10 0 0 0 0 1
+device=cascade-transformer
+T 50200 46300 5 10 0 1 0 0 1
+footprint=none
+T 51100 45700 5 10 1 0 0 0 1
+G=0
+T 51100 45500 5 10 1 0 0 0 1
+NF=0
+T 51100 45300 5 10 1 0 0 0 1
+RIN=50
+T 51100 45100 5 10 1 0 0 0 1
+ROUT=50
+}
+C 52900 46100 1 0 0 cascade-amp-1.sym
+{
+T 52825 46650 5 8 0 0 0 0 1
+device=cascade-amp
+T 53100 47500 5 10 1 1 0 0 1
+refdes=AMP2
+T 52500 46400 5 10 0 1 0 0 1
+footprint=none
+T 53200 46500 5 10 1 0 0 0 1
+G=10
+T 53200 46300 5 10 1 0 0 0 1
+NF=12
+T 53200 46100 5 10 1 0 0 0 1
+IIP3=12
+}
+N 52900 47000 52000 47000 4
+N 50500 47000 49900 47000 4
+N 48500 47000 47800 47000 4
+N 46500 47000 45600 47000 4
+N 44000 47000 43500 47000 4
+N 42500 47000 41500 47000 4
diff --git a/gnetlist/tests/common/inputs/gafrc b/gnetlist/tests/common/inputs/gafrc
new file mode 100644
index 0000000..7408ef0
--- /dev/null
+++ b/gnetlist/tests/common/inputs/gafrc
@@ -0,0 +1 @@
+(component-library "./sym")
diff --git a/gnetlist/tests/common/inputs/models/.gitignore b/gnetlist/tests/common/inputs/models/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/inputs/models/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/inputs/models/2N3904.mod b/gnetlist/tests/common/inputs/models/2N3904.mod
new file mode 100644
index 0000000..f8d0e80
--- /dev/null
+++ b/gnetlist/tests/common/inputs/models/2N3904.mod
@@ -0,0 +1,4 @@
+.model 2N3904   NPN(Stuff
++               More stuff
++               Yet more stuff
++               Final line of stuff)
diff --git a/gnetlist/tests/common/inputs/models/Makefile.am b/gnetlist/tests/common/inputs/models/Makefile.am
new file mode 100644
index 0000000..4630408
--- /dev/null
+++ b/gnetlist/tests/common/inputs/models/Makefile.am
@@ -0,0 +1,3 @@
+EXTRA_DIST= \
+     2N3904.mod \
+     openIP_5.cir
diff --git a/gnetlist/tests/common/inputs/models/openIP_5.cir b/gnetlist/tests/common/inputs/models/openIP_5.cir
new file mode 100644
index 0000000..26bf372
--- /dev/null
+++ b/gnetlist/tests/common/inputs/models/openIP_5.cir
@@ -0,0 +1,2 @@
+*
+.model unknown_LVD (stuff)
diff --git a/gnetlist/tests/common/inputs/multiequal.sch b/gnetlist/tests/common/inputs/multiequal.sch
new file mode 100644
index 0000000..f724ba4
--- /dev/null
+++ b/gnetlist/tests/common/inputs/multiequal.sch
@@ -0,0 +1,34 @@
+v 20031019 1
+C 26600 47100 1 0 0 spice-options-1.sym
+{
+T 26700 47500 5 10 1 1 0 0 1
+refdes=A1
+T 26600 47200 5 10 1 1 0 0 1
+value=abotol=1e-11
+}
+C 28800 45800 1 90 0 resistor-1.sym
+{
+T 28900 46200 5 10 1 1 0 0 1
+refdes=R1
+T 28800 45800 5 10 1 1 0 0 1
+value=20
+}
+N 26700 47000 28700 47000 4
+N 26700 47000 26700 46800 4
+N 28700 47000 28700 46700 4
+N 28700 45500 26700 45500 4
+N 28700 45500 28700 45800 4
+N 26700 45500 26700 45600 4
+C 26400 45600 1 0 0 vdc-1.sym
+{
+T 27100 46250 5 10 1 1 0 0 1
+refdes=V1
+T 27100 46050 5 10 1 1 0 0 1
+value=DC 1V
+}
+T 26600 48200 9 10 1 0 0 0 4
+This test makes sure that
+attributes in the form:
+     name=name1=value1 
+work and get tested.
+C 27600 45200 1 0 0 gnd-1.sym
diff --git a/gnetlist/tests/common/inputs/netattrib.sch b/gnetlist/tests/common/inputs/netattrib.sch
new file mode 100644
index 0000000..2c56e7b
--- /dev/null
+++ b/gnetlist/tests/common/inputs/netattrib.sch
@@ -0,0 +1,46 @@
+v 20030901
+C 38100 60100 1 0 0 7400-1.sym
+{
+T 38400 61000 5 10 1 1 0 0
+refdes=U100
+T 39000 60200 5 10 1 1 0 0
+net=netattrib:5
+}
+C 41000 58800 1 0 0 7404-1.sym
+{
+T 41300 59700 5 10 1 1 0 0
+refdes=U200
+}
+N 40000 59300 41000 59300 4
+{
+T 40100 59400 5 10 1 1 0 0
+netname=two
+}
+N 40000 59300 40000 61300 4
+N 40000 61300 41200 61300 4
+{
+T 40200 61400 5 10 1 1 0 0
+netname=one
+}
+C 41200 60800 1 0 0 7404-1.sym
+{
+T 41500 61700 5 10 1 1 0 0
+refdes=U300
+}
+N 39400 60600 40000 60600 4
+N 42100 59300 43300 59300 4
+{
+T 42500 59400 5 10 1 1 0 0
+netname=netattrib
+}
+N 42300 61300 43000 61300 4
+N 38400 58600 39100 58600 4
+{
+T 38500 58700 5 10 1 1 0 0
+netname=two
+}
+C 39100 58600 1 0 0 fuse-1.sym
+{
+T 39300 58800 5 10 1 1 0 0
+refdes=F1
+}
diff --git a/gnetlist/tests/common/inputs/powersupply.sch b/gnetlist/tests/common/inputs/powersupply.sch
new file mode 100644
index 0000000..4f378a6
--- /dev/null
+++ b/gnetlist/tests/common/inputs/powersupply.sch
@@ -0,0 +1,165 @@
+v 20030901
+C 60900 56700 1 0 0 diode-bridge-1.sym
+{
+T 61800 57675 5 10 1 1 0 0
+refdes=U1
+}
+N 60900 57700 60400 57700 4
+N 61900 56700 61900 56500 4
+N 61900 56500 59700 56500 4
+{
+T 59900 56500 5 6 1 1 0 0
+netname=seven
+}
+N 61900 58900 59700 58900 4
+{
+T 59800 58900 5 6 1 1 0 0
+netname=six
+}
+N 61900 58900 61900 58700 4
+N 59700 56500 59700 57200 4
+N 59700 58200 59700 58900 4
+C 57000 58200 1 0 0 fuse-1.sym
+{
+T 57200 58400 5 10 1 1 0 0
+refdes=F1
+}
+N 58200 58200 57900 58200 4
+{
+T 57900 58100 5 6 1 1 0 0
+netname=three
+}
+C 58200 57100 1 0 0 transformer-1.sym
+{
+T 58500 58400 5 10 1 1 0 0
+refdes=T1
+}
+C 53800 57200 1 0 0 mains-plug-2.sym
+{
+T 54200 58300 5 10 1 1 0 0
+refdes=CONN1
+}
+N 55200 58200 55200 58000 4
+N 58200 57200 55200 57200 4
+{
+T 56300 57200 5 6 1 1 0 0
+netname=five
+}
+N 55200 57200 55200 57400 4
+N 55200 57700 55500 57700 4
+{
+T 55300 57700 5 6 1 1 0 0
+netname=four
+}
+N 55500 57700 55500 57600 4
+C 55400 57300 1 0 0 gnd-1.sym
+C 55800 58200 1 0 0 switch-spst-1.sym
+{
+T 56100 58500 5 10 1 1 0 0
+refdes=S1
+}
+N 55800 58200 55200 58200 4
+{
+T 55300 58100 5 6 1 1 0 0
+netname=one
+}
+N 56600 58200 57000 58200 4
+{
+T 56600 58100 5 6 1 1 0 0
+netname=two
+}
+C 63300 58900 1 270 0 capacitor-2.sym
+{
+T 63800 58500 5 10 1 1 0 0
+refdes=C1
+T 63800 58300 5 10 1 1 0 0
+value=2200uF
+}
+C 68400 58100 1 90 0 resistor-1.sym
+{
+T 68500 58600 5 10 1 1 0 0
+refdes=R2
+T 68500 58300 5 10 1 1 0 0
+value=220
+}
+N 60400 57700 60400 59200 4
+N 62900 57700 63500 57700 4
+{
+T 63000 57700 5 6 1 1 0 0
+netname=nine
+}
+N 63500 58900 63500 59200 4
+C 64800 58200 1 270 0 capacitor-2.sym
+{
+T 65300 57800 5 10 1 1 0 0
+refdes=C2
+T 65300 57600 5 10 1 1 0 0
+value=0.1uF
+}
+N 65000 58200 65000 59200 4
+N 63500 56400 63500 58000 4
+N 65000 56400 65000 57300 4
+C 66800 56600 1 90 0 resistor-variable-1.sym
+{
+T 66900 57200 5 10 1 1 0 0
+refdes=R1
+T 66900 57000 5 10 1 1 0 0
+value=5k
+}
+N 66700 56600 66700 56400 4
+N 66200 57100 65800 57100 4
+N 65800 57100 65800 56400 4
+C 68100 57500 1 270 0 capacitor-2.sym
+{
+T 68600 57100 5 10 1 1 0 0
+refdes=C3
+T 68600 56800 5 10 1 1 0 0
+value=22uF
+}
+N 68300 58100 68300 57500 4
+N 68300 56600 68300 56400 4
+N 66700 57800 68300 57800 4
+{
+T 67000 57800 5 6 1 1 0 0
+netname=ten
+}
+N 60400 59200 65700 59200 4
+{
+T 60500 59200 5 6 1 1 0 0
+netname=eight
+}
+N 66700 57500 66700 58400 4
+N 68300 59000 68300 59200 4
+C 69300 58200 1 270 0 capacitor-2.sym
+{
+T 69800 57800 5 10 1 1 0 0
+refdes=C4
+T 69800 57500 5 10 1 1 0 0
+value=1uf
+}
+N 69500 58200 69500 59200 4
+N 69500 56400 69500 57300 4
+N 63500 56400 70800 56400 4
+N 67700 59200 70800 59200 4
+{
+T 68500 59200 5 6 1 1 0 0
+netname=eleven
+}
+T 70900 59200 9 10 1 0 0 0
++
+T 70900 56400 9 10 1 0 0 0
+-
+T 70400 59400 9 10 1 0 0 0
++1.5 to 22Vdc
+T 69700 57300 9 10 1 0 0 0
+50V
+T 63800 58100 9 10 1 0 0 0
+35V
+C 51800 49900 0 0 0 title-C.sym
+T 66900 50800 9 10 1 0 0 0
+This is not a real circuit.  It is only used for testing purposes.
+C 65700 58400 1 0 0 lm317-1.sym
+{
+T 67400 59800 5 10 1 1 0 6
+refdes=U2
+}
diff --git a/gnetlist/tests/common/inputs/singlenet.sch b/gnetlist/tests/common/inputs/singlenet.sch
new file mode 100644
index 0000000..5a60f73
--- /dev/null
+++ b/gnetlist/tests/common/inputs/singlenet.sch
@@ -0,0 +1,57 @@
+v 20071229 1
+C 17400 25700 1 0 0 7400-1.sym
+{
+T 17700 26700 5 10 1 1 0 0 1
+refdes=U100
+T 17400 25700 5 10 0 0 0 0 1
+slot=2
+}
+N 18700 26200 21300 26200 4
+N 21300 26200 21300 24400 4
+N 21300 24400 22600 24400 4
+N 22600 24000 20300 24000 4
+N 20300 24000 20300 26200 4
+N 21300 25300 24100 25300 4
+{
+T 22700 25400 5 10 1 1 0 0 1
+netname=SING_N
+}
+N 24100 25300 24100 24200 4
+N 24100 24200 23900 24200 4
+N 17400 26000 17000 26000 4
+N 17000 26000 17000 25300 4
+N 17000 25300 18800 25300 4
+N 18800 25300 18800 26200 4
+N 17400 26400 17200 26400 4
+N 17200 26400 17200 27200 4
+N 17200 27200 19800 27200 4
+N 19800 27200 19800 26200 4
+T 17900 35200 3 30 1 0 0 0 1
+Test schematic for gnetlist
+T 17100 27600 3 20 1 0 0 0 1
+There is really only *one* net in this circuit
+N 19000 33100 21800 33100 4
+{
+T 20400 33200 5 10 1 1 0 0 1
+netname=SING_N_2
+}
+N 21800 33100 21800 32000 4
+N 21800 32000 21600 32000 4
+N 19000 33100 19000 32200 4
+N 19000 32200 20300 32200 4
+T 17200 30200 3 20 1 0 0 0 1
+This is a single net with one unconnected pin
+C 20300 31500 1 0 0 7400-1.sym
+{
+T 20600 32500 5 10 1 1 0 0 1
+refdes=U100
+T 20300 31500 5 10 0 0 0 0 1
+slot=1
+}
+C 22600 23700 1 0 0 7400-1.sym
+{
+T 22900 24700 5 10 1 1 0 0 1
+refdes=U100
+T 22600 23700 5 10 0 0 0 0 1
+slot=3
+}
diff --git a/gnetlist/tests/common/inputs/sym/.gitignore b/gnetlist/tests/common/inputs/sym/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/inputs/sym/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/inputs/sym/LM324_slotted-1.sym b/gnetlist/tests/common/inputs/sym/LM324_slotted-1.sym
new file mode 100644
index 0000000..1707dad
--- /dev/null
+++ b/gnetlist/tests/common/inputs/sym/LM324_slotted-1.sym
@@ -0,0 +1,60 @@
+v 20031231 1
+L 200 0 200 800 3 0 0 0 -1 -1
+L 200 800 800 400 3 0 0 0 -1 -1
+L 800 400 200 0 3 0 0 0 -1 -1
+T 825 150 5 8 0 0 0 0 1
+device=LM324
+T 700 1200 5 10 0 0 0 0 1
+numslots=4
+T 675 1050 5 10 0 0 0 0 1
+slotdef=1:1,2,3
+T 675 900 5 10 0 0 0 0 1
+slotdef=2:7,6,5
+T 675 750 5 10 0 0 0 0 1
+slotdef=3:8,9,10
+T 675 600 5 10 0 0 0 0 1
+slotdef=4:14,13,12
+T 1225 450 5 10 0 0 0 0 1
+slot=1
+P 200 600 0 600 1 0 1
+{
+T 50 625 5 8 1 1 0 0 1
+pinnumber=3
+T 50 625 5 8 0 0 0 0 1
+pinseq=3
+}
+P 200 200 0 200 1 0 1
+{
+T 50 225 5 8 1 1 0 0 1
+pinnumber=2
+T 50 225 5 8 0 0 0 0 1
+pinseq=2
+}
+P 800 400 1000 400 1 0 1
+{
+T 875 425 5 8 1 1 0 0 1
+pinnumber=1
+T 875 425 5 8 0 0 0 0 1
+pinseq=1
+}
+#P 500 200 500 0 1 0 1
+#{
+#T 525 50 5 8 1 1 0 0 1
+#pinnumber=11
+#T 525 50 5 8 0 0 0 0 1
+#pinseq=11
+#}
+#P 500 600 500 800 1 0 1
+#{
+#T 525 650 5 8 1 1 0 0 1
+#pinnumber=4
+#T 525 650 5 8 0 0 0 0 1
+#pinseq=4
+#}
+L 250 600 350 600 3 0 0 0 -1 -1
+L 300 650 300 550 3 0 0 0 -1 -1
+L 250 200 350 200 3 0 0 0 -1 -1
+T 225 350 9 8 1 0 0 0 1
+LM324
+T 200 900 8 10 1 1 0 0 1
+refdes=U?
diff --git a/gnetlist/tests/common/inputs/sym/LVD.sym b/gnetlist/tests/common/inputs/sym/LVD.sym
new file mode 100644
index 0000000..6ab69da
--- /dev/null
+++ b/gnetlist/tests/common/inputs/sym/LVD.sym
@@ -0,0 +1,86 @@
+v 20070216 1
+L 200 0 200 -1000 3 0 0 0 -1 -1
+T 500 -500 8 10 0 1 0 4 1
+device=LVD
+L 200 -1000 1200 -500 3 0 0 0 -1 -1
+L 1200 -500 200 0 3 0 0 0 -1 -1
+V 900 -700 49 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 1200 -700 950 -700 1 0 0
+{
+T 1200 -700 5 10 0 0 0 0 1
+pinnumber=4
+T 1200 -700 5 10 0 0 0 0 1
+pinseq=4
+T 1200 -700 5 10 0 0 0 0 1
+pintype=out
+T 1200 -700 5 10 0 0 0 0 1
+pinlabel=Y0
+}
+P 1200 -300 800 -300 1 0 0
+{
+T 1200 -300 5 10 0 0 0 0 1
+pinnumber=5
+T 1200 -300 5 10 0 0 0 0 1
+pinseq=5
+T 1200 -300 5 10 0 0 0 0 1
+pintype=out
+T 1200 -300 5 10 0 0 0 0 1
+pinlabel=Y1
+}
+P 0 -500 200 -500 1 0 0
+{
+T 0 -500 5 10 0 0 0 0 1
+pinnumber=1
+T 0 -500 5 10 0 0 0 0 1
+pinseq=1
+T 0 -500 5 10 0 0 0 0 1
+pintype=in
+T 0 -500 5 10 0 0 0 0 1
+pinlabel=D
+}
+P 600 0 600 -200 1 0 0
+{
+T 600 0 5 10 0 0 0 0 1
+pinnumber=3
+T 600 0 5 10 0 0 0 0 1
+pinseq=3
+T 600 0 5 10 0 0 0 0 1
+pintype=in
+T 600 -200 5 6 1 1 0 8 1
+pinlabel=VH
+}
+P 600 -1000 600 -800 1 0 0
+{
+T 600 -1000 5 10 0 0 0 0 1
+pinnumber=2
+T 600 -1000 5 10 0 0 0 0 1
+pinseq=2
+T 600 -1000 5 10 0 0 0 0 1
+pintype=pwr
+T 600 -800 5 6 1 1 0 6 1
+pinlabel=DGND
+}
+T 200 0 8 10 0 1 0 0 1
+refdes=X?
+P 800 0 800 -300 1 0 0
+{
+T 600 -300 5 10 0 0 0 0 1
+pinnumber=6
+T 600 -300 5 10 0 0 0 0 1
+pinseq=6
+T 600 -300 5 10 0 0 0 0 1
+pintype=pwr
+T 600 -300 5 10 0 0 0 0 1
+pinlabel=Vdd1
+}
+P 800 -1000 800 -700 1 0 0
+{
+T 600 -700 5 10 0 0 0 0 1
+pinnumber=7
+T 600 -700 5 10 0 0 0 0 1
+pinseq=7
+T 600 -700 5 10 0 0 0 0 1
+pintype=pwr
+T 600 -700 5 10 0 0 0 0 1
+pinlabel=Vss
+}
diff --git a/gnetlist/tests/common/inputs/sym/Makefile.am b/gnetlist/tests/common/inputs/sym/Makefile.am
new file mode 100644
index 0000000..76adbcf
--- /dev/null
+++ b/gnetlist/tests/common/inputs/sym/Makefile.am
@@ -0,0 +1,4 @@
+EXTRA_DIST= \
+     LVD.sym \
+     transistor.sym \
+     LM324_slotted-1.sym 
diff --git a/gnetlist/tests/common/inputs/sym/transistor.sym b/gnetlist/tests/common/inputs/sym/transistor.sym
new file mode 100644
index 0000000..65492d4
--- /dev/null
+++ b/gnetlist/tests/common/inputs/sym/transistor.sym
@@ -0,0 +1,36 @@
+v 20031011 1
+P 600 1000 600 800 1 0 0
+{
+T 500 850 5 6 1 1 0 0 1
+pinnumber=3
+T 500 850 5 6 0 0 0 0 1
+pinseq=1
+}
+P 600 200 600 0 1 0 1
+{
+T 500 50 5 6 1 1 0 0 1
+pinnumber=1
+T 500 50 5 6 0 0 0 0 1
+pinseq=3
+}
+V 500 501 316 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 900 700 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+L 600 200 400 400 3 0 0 0 -1 -1
+L 600 800 400 600 3 0 0 0 -1 -1
+L 400 700 400 300 3 0 0 0 -1 -1
+P 0 500 184 500 1 0 0
+{
+T 100 550 5 6 1 1 0 0 1
+pinnumber=2
+T 100 550 5 6 0 0 0 0 1
+pinseq=2
+}
+L 400 500 184 500 3 0 0 0 -1 -1
+L 600 200 564 272 3 0 0 0 -1 -1
+L 600 200 528 236 3 0 0 0 -1 -1
+L 528 236 564 272 3 0 0 0 -1 -1
+T 900 500 8 10 1 1 0 0 1
+refdes=Q?
+T 900 300 9 10 1 0 0 0 1
+Generic_Transistor
diff --git a/gnetlist/tests/common/outputs/.gitignore b/gnetlist/tests/common/outputs/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/Makefile.am b/gnetlist/tests/common/outputs/Makefile.am
new file mode 100644
index 0000000..d2f9934
--- /dev/null
+++ b/gnetlist/tests/common/outputs/Makefile.am
@@ -0,0 +1,37 @@
+SUBDIRS= \
+       allegro \
+       bae \
+       bom2 \
+       bom \
+       calay \
+       cascade \
+       drc2 \
+       drc \
+       eagle \
+       futurenet2 \
+       geda \
+       gossip \
+       gsch2pcb \
+       mathematica \
+       maxascii \
+       osmond \
+       pads \
+       partslist1 \
+       partslist2 \
+       partslist3 \
+       PCBboard \
+       pcbpins \
+       PCB \
+       protelII \
+       redac \
+       spice \
+       spice-sdb \
+       switcap \
+       systemc \
+       tango \
+       vams \
+       verilog \
+       vhdl \
+       vipec
+
+EXTRA_DIST= regen_sub_makefile_am.sh
diff --git a/gnetlist/tests/common/outputs/PCB/.gitignore b/gnetlist/tests/common/outputs/PCB/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/PCB/JD-output.net b/gnetlist/tests/common/outputs/PCB/JD-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/JD.retcode b/gnetlist/tests/common/outputs/PCB/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Include-output.net b/gnetlist/tests/common/outputs/PCB/JD_Include-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Include-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Include.retcode b/gnetlist/tests/common/outputs/PCB/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Sort-output.net b/gnetlist/tests/common/outputs/PCB/JD_Sort-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Sort-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Sort.retcode b/gnetlist/tests/common/outputs/PCB/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/JD_nomunge-output.net b/gnetlist/tests/common/outputs/PCB/JD_nomunge-output.net
new file mode 100644
index 0000000..4f7f45d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/JD_nomunge-output.net
@@ -0,0 +1,6 @@
+Vdd1	Rlp-2 M1-B M1-S Vdd-1 X1-6 
+GND	Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 
+LVH	Rb-2 M1-D M1-G X1-3 
+i	V1-1 X1-1 
+p	Cp-1 Rt-1 Rlp-1 X1-5 
+m	Cm-1 Rlm-1 Rt-2 X1-4 
diff --git a/gnetlist/tests/common/outputs/PCB/Makefile.am b/gnetlist/tests/common/outputs/PCB/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/PCB/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/PCB/SlottedOpamps-output.net
new file mode 100644
index 0000000..ec5b7ed
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/SlottedOpamps-output.net
@@ -0,0 +1,9 @@
+minusin_slot4_pin13_b	U1-13 
+plusin_slot4_pin12_a	U1-12 
+minusin_slot3_pin_b	U1-9 
+plusin_slot3_pin10_a	U1-10 
+minusin_slot2_pin6_b	U1-6 
+plusin_slot2_pin5_a	U1-5 
+samenet_output_c	U1-14 U1-8 U1-7 U1-1 
+minusin_slot1_pin_b	U1-2 
+plusin_slot1_pin3_a	U1-3 
diff --git a/gnetlist/tests/common/outputs/PCB/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/PCB/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/PCB/TwoStageAmp-output.net
new file mode 100644
index 0000000..e45cdbe
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp-output.net
@@ -0,0 +1,12 @@
+unnamed_net2	C2-1 R8-2 
+Vbase2	R3-1 C2-2 R4-2 Q2-2 
+Vem2	CE2-2 RE2-2 Q2-1 
+Vout	Cout-2 RL-2 
+VColl2	Q2-3 Cout-1 RC2-1 
+GND	R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 
+Vcc	R3-2 RC1-2 VCC-1 RC2-2 R1-2 
+Vin	Vinput-1 R5-1 
+unnamed_net1	C1-1 R5-2 
+Vbase1	C1-2 R2-2 R1-1 Q1-2 
+Vem1	CE1-2 RE1-2 Q1-1 
+Vcoll1	R8-1 RC1-1 Q1-3 
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/PCB/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..e45cdbe
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include-output.net
@@ -0,0 +1,12 @@
+unnamed_net2	C2-1 R8-2 
+Vbase2	R3-1 C2-2 R4-2 Q2-2 
+Vem2	CE2-2 RE2-2 Q2-1 
+Vout	Cout-2 RL-2 
+VColl2	Q2-3 Cout-1 RC2-1 
+GND	R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 
+Vcc	R3-2 RC1-2 VCC-1 RC2-2 R1-2 
+Vin	Vinput-1 R5-1 
+unnamed_net1	C1-1 R5-2 
+Vbase1	C1-2 R2-2 R1-1 Q1-2 
+Vem1	CE1-2 RE1-2 Q1-1 
+Vcoll1	R8-1 RC1-1 Q1-3 
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..e45cdbe
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort-output.net
@@ -0,0 +1,12 @@
+unnamed_net2	C2-1 R8-2 
+Vbase2	R3-1 C2-2 R4-2 Q2-2 
+Vem2	CE2-2 RE2-2 Q2-1 
+Vout	Cout-2 RL-2 
+VColl2	Q2-3 Cout-1 RC2-1 
+GND	R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 
+Vcc	R3-2 RC1-2 VCC-1 RC2-2 R1-2 
+Vin	Vinput-1 R5-1 
+unnamed_net1	C1-1 R5-2 
+Vbase1	C1-2 R2-2 R1-1 Q1-2 
+Vem1	CE1-2 RE1-2 Q1-1 
+Vcoll1	R8-1 RC1-1 Q1-3 
diff --git a/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/cascade-output.net b/gnetlist/tests/common/outputs/PCB/cascade-output.net
new file mode 100644
index 0000000..68cf477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/cascade-output.net
@@ -0,0 +1,7 @@
+unnamed_net6	AMP2-1 T1-2 
+unnamed_net5	T1-1 MX1-2 
+unnamed_net4	MX1-1 FL1-2 
+unnamed_net3	FL1-1 DEF1-2 
+unnamed_net2	DEF1-1 AMP1-2 
+unnamed_net1	AMP1-1 SOURCE-1 
+GND	DEFAULTS-1 
diff --git a/gnetlist/tests/common/outputs/PCB/cascade.retcode b/gnetlist/tests/common/outputs/PCB/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/multiequal-output.net b/gnetlist/tests/common/outputs/PCB/multiequal-output.net
new file mode 100644
index 0000000..882aee9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/multiequal-output.net
@@ -0,0 +1,2 @@
+GND	V1-2 R1-1 
+unnamed_net1	V1-1 R1-2 
diff --git a/gnetlist/tests/common/outputs/PCB/multiequal.retcode b/gnetlist/tests/common/outputs/PCB/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/netattrib-output.net b/gnetlist/tests/common/outputs/PCB/netattrib-output.net
new file mode 100644
index 0000000..bdaacfa
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/netattrib-output.net
@@ -0,0 +1,5 @@
+unnamed_net1	U300-2 
+netattrib	U200-2 U100-5 
+GND	U300-7 U200-7 U100-7 
+Vcc	U300-14 U200-14 U100-14 
+one	F1-1 U300-1 U200-1 U100-3 
diff --git a/gnetlist/tests/common/outputs/PCB/netattrib.retcode b/gnetlist/tests/common/outputs/PCB/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/powersupply-output.net b/gnetlist/tests/common/outputs/PCB/powersupply-output.net
new file mode 100644
index 0000000..ee5267d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/powersupply-output.net
@@ -0,0 +1,11 @@
+ten	U2-1 R1-2 C3-1 R2-1 
+eleven	U2-2 C4-1 R2-2 
+GND	CONN1-3 
+one	S1-1 CONN1-1 
+five	CONN1-2 T1-2 
+three	T1-1 F1-2 
+two	S1-2 F1-1 
+six	T1-3 U1-4 
+seven	T1-4 U1-3 
+nine	C4-2 C3-2 R1-3 R1-1 C2-2 C1-2 U1-2 
+eight	U2-3 C2-1 C1-1 U1-1 
diff --git a/gnetlist/tests/common/outputs/PCB/powersupply.retcode b/gnetlist/tests/common/outputs/PCB/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCB/singlenet-output.net b/gnetlist/tests/common/outputs/PCB/singlenet-output.net
new file mode 100644
index 0000000..3052c13
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/singlenet-output.net
@@ -0,0 +1,4 @@
+SING_N_2	U100-1 U100-3 
+GND	U100-7 
+Vcc	U100-14 
+SING_N	U100-4 U100-5 U100-10 U100-8 U100-9 U100-6 
diff --git a/gnetlist/tests/common/outputs/PCB/singlenet.retcode b/gnetlist/tests/common/outputs/PCB/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCB/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/.gitignore b/gnetlist/tests/common/outputs/PCBboard/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD-output.net b/gnetlist/tests/common/outputs/PCBboard/JD-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD.retcode b/gnetlist/tests/common/outputs/PCBboard/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Include-output.net b/gnetlist/tests/common/outputs/PCBboard/JD_Include-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Include-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Include.retcode b/gnetlist/tests/common/outputs/PCBboard/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Sort-output.net b/gnetlist/tests/common/outputs/PCBboard/JD_Sort-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Sort-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Sort.retcode b/gnetlist/tests/common/outputs/PCBboard/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/JD_nomunge-output.net b/gnetlist/tests/common/outputs/PCBboard/JD_nomunge-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/JD_nomunge-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/Makefile.am b/gnetlist/tests/common/outputs/PCBboard/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/cascade-output.net b/gnetlist/tests/common/outputs/PCBboard/cascade-output.net
new file mode 100644
index 0000000..65641ae
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/cascade-output.net
@@ -0,0 +1,34 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(cascade-amp,AMP2,unknown)
+PKG_none(cascade-amp,AMP1,unknown)
+PKG_none(cascade-source,SOURCE,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/cascade.retcode b/gnetlist/tests/common/outputs/PCBboard/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/multiequal-output.net b/gnetlist/tests/common/outputs/PCBboard/multiequal-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/multiequal-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/multiequal.retcode b/gnetlist/tests/common/outputs/PCBboard/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/netattrib-output.net b/gnetlist/tests/common/outputs/PCBboard/netattrib-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/netattrib-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/netattrib.retcode b/gnetlist/tests/common/outputs/PCBboard/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/powersupply-output.net b/gnetlist/tests/common/outputs/PCBboard/powersupply-output.net
new file mode 100644
index 0000000..54f4a0b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/powersupply-output.net
@@ -0,0 +1,31 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/powersupply.retcode b/gnetlist/tests/common/outputs/PCBboard/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/PCBboard/singlenet-output.net b/gnetlist/tests/common/outputs/PCBboard/singlenet-output.net
new file mode 100644
index 0000000..4081b3d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/singlenet-output.net
@@ -0,0 +1,71 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(10 270 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+
+# retain backwards compatibility to older versions of PKG_DIL 
+# which did not have 100,60,28 args
+
+        
+              
+        
+              
+        
+              
+	
+	
+	
+	
+Element(0x00 "7400" "U100" "unknown" 220 100 3 100 0x00)
+(
+	Pin(50 50 60 28 "1" 0x101)
+	Pin(50 150 60 28 "2" 0x01)
+	Pin(50 250 60 28 "3" 0x01)
+	Pin(50 350 60 28 "4" 0x01)
+	Pin(50 450 60 28 "5" 0x01)
+	Pin(50 550 60 28 "6" 0x01)
+	Pin(50 650 60 28 "7" 0x01)
+	
+	Pin(350 650 60 28 "8" 0x01)
+	Pin(350 550 60 28 "9" 0x01)
+	Pin(350 450 60 28 "10" 0x01)
+	Pin(350 350 60 28 "11" 0x01)
+	Pin(350 250 60 28 "12" 0x01)
+	Pin(350 150 60 28 "13" 0x01)
+	Pin(350 50 60 28 "14" 0x01)
+	
+	ElementLine(0 0 0 700 10)
+	ElementLine(0 700 400 700 10)
+	ElementLine(400 700 400 0 10)
+	ElementLine(0 0 150 0 10)
+	ElementLine(250 0 400 0 10)
+	ElementArc(200 0 50 50 0 180 10)
+	Mark(50 50)
+)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/PCBboard/singlenet.retcode b/gnetlist/tests/common/outputs/PCBboard/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/PCBboard/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/.gitignore b/gnetlist/tests/common/outputs/allegro/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/allegro/JD-output.net b/gnetlist/tests/common/outputs/allegro/JD-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/JD.retcode b/gnetlist/tests/common/outputs/allegro/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include-output.net b/gnetlist/tests/common/outputs/allegro/JD_Include-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include.retcode b/gnetlist/tests/common/outputs/allegro/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net b/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort.retcode b/gnetlist/tests/common/outputs/allegro/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net b/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
new file mode 100644
index 0000000..5492bf8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/JD_nomunge-output.net
@@ -0,0 +1,42 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! vpulse! pulse 3.3 0 1u 10p 10p 1.25u 2.5u; V1
+! CAPACITOR! 20p; Cm
+! model! model; A1
+! RESISTOR! 1k; Rt
+! PMOS_TRANSISTOR! PMOS_TRANSISTOR; M1
+! LVD! LVD; X1
+! RESISTOR! 1meg; Rlp
+none! VOLTAGE_SOURCE! DC 3.3V; Vdd
+! RESISTOR! 500k; Rlm
+! CAPACITOR! 20p; Cp
+! RESISTOR! 5.6k; Rb
+$NETS
+Vdd1; Rlp.2,
+ M1.B,
+ M1.S,
+ Vdd.1,
+ X1.6
+GND; Cm.2,
+ Cp.2,
+ Rlm.2,
+ Vdd.2,
+ V1.2,
+ Rb.1,
+ X1.7,
+ X1.2
+LVH; Rb.2,
+ M1.D,
+ M1.G,
+ X1.3
+i; V1.1,
+ X1.1
+p; Cp.1,
+ Rt.1,
+ Rlp.1,
+ X1.5
+m; Cm.1,
+ Rlm.1,
+ Rt.2,
+ X1.4
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/Makefile.am b/gnetlist/tests/common/outputs/allegro/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/allegro/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/allegro/SlottedOpamps-output.net
new file mode 100644
index 0000000..e83277e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/SlottedOpamps-output.net
@@ -0,0 +1,17 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! LM324! LM324; U1
+$NETS
+minusin_slot4_pin13_b; U1.13
+plusin_slot4_pin12_a; U1.12
+minusin_slot3_pin_b; U1.9
+plusin_slot3_pin10_a; U1.10
+minusin_slot2_pin6_b; U1.6
+plusin_slot2_pin5_a; U1.5
+samenet_output_c; U1.14,
+ U1.8,
+ U1.7,
+ U1.1
+minusin_slot1_pin_b; U1.2
+plusin_slot1_pin3_a; U1.3
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/allegro/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
new file mode 100644
index 0000000..d48fc78
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp-output.net
@@ -0,0 +1,69 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! CAPACITOR! 2.2uF; Cout
+! RESISTOR! 10; R5
+! RESISTOR! 2.8K; R4
+! RESISTOR! 100; RE2
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! directive! .options TEMP=25; A3
+! RESISTOR! 28K; R3
+! include! include; A2
+! RESISTOR! 100; RE1
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
+! model! model; A1
+! RESISTOR! 2K; R2
+none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
+! RESISTOR! 28K; R1
+! CAPACITOR! 2.2uF; C2
+! CAPACITOR! 1pF; CE2
+! CAPACITOR! 2.2uF; C1
+! CAPACITOR! 1pF; CE1
+! RESISTOR! 1; R8
+none! VOLTAGE_SOURCE! DC 15V; VCC
+! RESISTOR! 1K; RC2
+! RESISTOR! 3.3K; RC1
+! RESISTOR! 100K; RL
+$NETS
+unnamed_net2; C2.1,
+ R8.2
+Vbase2; R3.1,
+ C2.2,
+ R4.2,
+ Q2.2
+Vem2; CE2.2,
+ RE2.2,
+ Q2.1
+Vout; Cout.2,
+ RL.2
+VColl2; Q2.3,
+ Cout.1,
+ RC2.1
+GND; R4.1,
+ CE2.1,
+ RE2.1,
+ VCC.2,
+ Vinput.2,
+ CE1.1,
+ RL.1,
+ RE1.1,
+ R2.1
+Vcc; R3.2,
+ RC1.2,
+ VCC.1,
+ RC2.2,
+ R1.2
+Vin; Vinput.1,
+ R5.1
+unnamed_net1; C1.1,
+ R5.2
+Vbase1; C1.2,
+ R2.2,
+ R1.1,
+ Q1.2
+Vem1; CE1.2,
+ RE1.2,
+ Q1.1
+Vcoll1; R8.1,
+ RC1.1,
+ Q1.3
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/allegro/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..d48fc78
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include-output.net
@@ -0,0 +1,69 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! CAPACITOR! 2.2uF; Cout
+! RESISTOR! 10; R5
+! RESISTOR! 2.8K; R4
+! RESISTOR! 100; RE2
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! directive! .options TEMP=25; A3
+! RESISTOR! 28K; R3
+! include! include; A2
+! RESISTOR! 100; RE1
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
+! model! model; A1
+! RESISTOR! 2K; R2
+none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
+! RESISTOR! 28K; R1
+! CAPACITOR! 2.2uF; C2
+! CAPACITOR! 1pF; CE2
+! CAPACITOR! 2.2uF; C1
+! CAPACITOR! 1pF; CE1
+! RESISTOR! 1; R8
+none! VOLTAGE_SOURCE! DC 15V; VCC
+! RESISTOR! 1K; RC2
+! RESISTOR! 3.3K; RC1
+! RESISTOR! 100K; RL
+$NETS
+unnamed_net2; C2.1,
+ R8.2
+Vbase2; R3.1,
+ C2.2,
+ R4.2,
+ Q2.2
+Vem2; CE2.2,
+ RE2.2,
+ Q2.1
+Vout; Cout.2,
+ RL.2
+VColl2; Q2.3,
+ Cout.1,
+ RC2.1
+GND; R4.1,
+ CE2.1,
+ RE2.1,
+ VCC.2,
+ Vinput.2,
+ CE1.1,
+ RL.1,
+ RE1.1,
+ R2.1
+Vcc; R3.2,
+ RC1.2,
+ VCC.1,
+ RC2.2,
+ R1.2
+Vin; Vinput.1,
+ R5.1
+unnamed_net1; C1.1,
+ R5.2
+Vbase1; C1.2,
+ R2.2,
+ R1.1,
+ Q1.2
+Vem1; CE1.2,
+ RE1.2,
+ Q1.1
+Vcoll1; R8.1,
+ RC1.1,
+ Q1.3
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..d48fc78
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort-output.net
@@ -0,0 +1,69 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! CAPACITOR! 2.2uF; Cout
+! RESISTOR! 10; R5
+! RESISTOR! 2.8K; R4
+! RESISTOR! 100; RE2
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q2
+! directive! .options TEMP=25; A3
+! RESISTOR! 28K; R3
+! include! include; A2
+! RESISTOR! 100; RE1
+! NPN_TRANSISTOR! NPN_TRANSISTOR; Q1
+! model! model; A1
+! RESISTOR! 2K; R2
+none! vsin! DC 1.6V AC 10MV SIN(0 1MV 1KHZ); Vinput
+! RESISTOR! 28K; R1
+! CAPACITOR! 2.2uF; C2
+! CAPACITOR! 1pF; CE2
+! CAPACITOR! 2.2uF; C1
+! CAPACITOR! 1pF; CE1
+! RESISTOR! 1; R8
+none! VOLTAGE_SOURCE! DC 15V; VCC
+! RESISTOR! 1K; RC2
+! RESISTOR! 3.3K; RC1
+! RESISTOR! 100K; RL
+$NETS
+unnamed_net2; C2.1,
+ R8.2
+Vbase2; R3.1,
+ C2.2,
+ R4.2,
+ Q2.2
+Vem2; CE2.2,
+ RE2.2,
+ Q2.1
+Vout; Cout.2,
+ RL.2
+VColl2; Q2.3,
+ Cout.1,
+ RC2.1
+GND; R4.1,
+ CE2.1,
+ RE2.1,
+ VCC.2,
+ Vinput.2,
+ CE1.1,
+ RL.1,
+ RE1.1,
+ R2.1
+Vcc; R3.2,
+ RC1.2,
+ VCC.1,
+ RC2.2,
+ R1.2
+Vin; Vinput.1,
+ R5.1
+unnamed_net1; C1.1,
+ R5.2
+Vbase1; C1.2,
+ R2.2,
+ R1.1,
+ Q1.2
+Vem1; CE1.2,
+ RE1.2,
+ Q1.1
+Vcoll1; R8.1,
+ RC1.1,
+ Q1.3
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/cascade-output.net b/gnetlist/tests/common/outputs/allegro/cascade-output.net
new file mode 100644
index 0000000..9ad1608
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/cascade-output.net
@@ -0,0 +1,25 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! cascade-amp! cascade-amp; AMP2
+none! cascade-amp! cascade-amp; AMP1
+none! cascade-source! cascade-source; SOURCE
+! cascade-defaults-top! cascade-defaults-top; DEFAULTS
+none! cascade-mixer! cascade-mixer; MX1
+none! cascade-defaults! cascade-defaults; DEF1
+none! cascade-transformer! cascade-transformer; T1
+none! cascade-filter! cascade-filter; FL1
+$NETS
+unnamed_net6; AMP2.1,
+ T1.2
+unnamed_net5; T1.1,
+ MX1.2
+unnamed_net4; MX1.1,
+ FL1.2
+unnamed_net3; FL1.1,
+ DEF1.2
+unnamed_net2; DEF1.1,
+ AMP1.2
+unnamed_net1; AMP1.1,
+ SOURCE.1
+GND; DEFAULTS.1
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/cascade.retcode b/gnetlist/tests/common/outputs/allegro/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/multiequal-output.net b/gnetlist/tests/common/outputs/allegro/multiequal-output.net
new file mode 100644
index 0000000..f59daf7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/multiequal-output.net
@@ -0,0 +1,11 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+none! VOLTAGE_SOURCE! DC 1V; V1
+! options! abotol=1e-11; A1
+! RESISTOR! 20; R1
+$NETS
+GND; V1.2,
+ R1.1
+unnamed_net1; V1.1,
+ R1.2
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/multiequal.retcode b/gnetlist/tests/common/outputs/allegro/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/netattrib-output.net b/gnetlist/tests/common/outputs/allegro/netattrib-output.net
new file mode 100644
index 0000000..ac3f34a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/netattrib-output.net
@@ -0,0 +1,21 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! FUSE! FUSE; F1
+DIP14! 7400! 7400; U100
+DIP14! 7404! 7404; U300
+DIP14! 7404! 7404; U200
+$NETS
+unnamed_net1; U300.2
+netattrib; U200.2,
+ U100.5
+GND; U300.7,
+ U200.7,
+ U100.7
+Vcc; U300.14,
+ U200.14,
+ U100.14
+one; F1.1,
+ U300.1,
+ U200.1,
+ U100.3
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/netattrib.retcode b/gnetlist/tests/common/outputs/allegro/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/powersupply-output.net b/gnetlist/tests/common/outputs/allegro/powersupply-output.net
new file mode 100644
index 0000000..a338584
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/powersupply-output.net
@@ -0,0 +1,47 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+! FUSE! FUSE; F1
+! RESISTOR! 220; R2
+! MAINS_CONNECTOR! MAINS_CONNECTOR; CONN1
+! POLARIZED_CAPACITOR! 1uf; C4
+! VARIABLE_RESISTOR! 5k; R1
+! POLARIZED_CAPACITOR! 22uF; C3
+! POLARIZED_CAPACITOR! 0.1uF; C2
+! SPST! SPST; S1
+! POLARIZED_CAPACITOR! 2200uF; C1
+! transformer! transformer; T1
+! LM317! LM317; U2
+! DIODE-BRIDGE! DIODE-BRIDGE; U1
+$NETS
+ten; U2.1,
+ R1.2,
+ C3.1,
+ R2.1
+eleven; U2.2,
+ C4.1,
+ R2.2
+GND; CONN1.3
+one; S1.1,
+ CONN1.1
+five; CONN1.2,
+ T1.2
+three; T1.1,
+ F1.2
+two; S1.2,
+ F1.1
+six; T1.3,
+ U1.4
+seven; T1.4,
+ U1.3
+nine; C4.2,
+ C3.2,
+ R1.3,
+ R1.1,
+ C2.2,
+ C1.2,
+ U1.2
+eight; U2.3,
+ C2.1,
+ C1.1,
+ U1.1
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/powersupply.retcode b/gnetlist/tests/common/outputs/allegro/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/allegro/singlenet-output.net b/gnetlist/tests/common/outputs/allegro/singlenet-output.net
new file mode 100644
index 0000000..b73b3cb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/singlenet-output.net
@@ -0,0 +1,15 @@
+(Allegro netlister by M. Ettus)
+$PACKAGES
+DIP14! 7400! 7400; U100
+$NETS
+SING_N_2; U100.1,
+ U100.3
+GND; U100.7
+Vcc; U100.14
+SING_N; U100.4,
+ U100.5,
+ U100.10,
+ U100.8,
+ U100.9,
+ U100.6
+$END
diff --git a/gnetlist/tests/common/outputs/allegro/singlenet.retcode b/gnetlist/tests/common/outputs/allegro/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/allegro/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/.gitignore b/gnetlist/tests/common/outputs/bae/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/bae/JD-output.net b/gnetlist/tests/common/outputs/bae/JD-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/JD.retcode b/gnetlist/tests/common/outputs/bae/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include-output.net b/gnetlist/tests/common/outputs/bae/JD_Include-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Include-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include.retcode b/gnetlist/tests/common/outputs/bae/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort-output.net b/gnetlist/tests/common/outputs/bae/JD_Sort-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort.retcode b/gnetlist/tests/common/outputs/bae/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net
new file mode 100644
index 0000000..2878a95
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/JD_nomunge-output.net
@@ -0,0 +1,21 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    Cm : unknown;
+    A1 : unknown;
+    Rt : unknown;
+    M1 : unknown;
+    X1 : unknown;
+    Rlp : unknown;
+    Vdd : none;
+    Rlm : unknown;
+    Cp : unknown;
+    Rb : unknown;
+CONNECT
+    /'Vdd1'/ Rlp.2=M1.B=M1.S=Vdd.1=X1.6;
+    /'GND'/ Cm.2=Cp.2=Rlm.2=Vdd.2=V1.2=Rb.1=X1.7=X1.2;
+    /'LVH'/ Rb.2=M1.D=M1.G=X1.3;
+    /'i'/ V1.1=X1.1;
+    /'p'/ Cp.1=Rt.1=Rlp.1=X1.5;
+    /'m'/ Cm.1=Rlm.1=Rt.2=X1.4;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/Makefile.am b/gnetlist/tests/common/outputs/bae/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/bae/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/bae/SlottedOpamps-output.net
new file mode 100644
index 0000000..8327c6e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/SlottedOpamps-output.net
@@ -0,0 +1,14 @@
+LAYOUT board;
+PARTS
+    U1 : unknown;
+CONNECT
+    /'minusin_slot4_pin13_b'/ U1.13;
+    /'plusin_slot4_pin12_a'/ U1.12;
+    /'minusin_slot3_pin_b'/ U1.9;
+    /'plusin_slot3_pin10_a'/ U1.10;
+    /'minusin_slot2_pin6_b'/ U1.6;
+    /'plusin_slot2_pin5_a'/ U1.5;
+    /'samenet_output_c'/ U1.14=U1.8=U1.7=U1.1;
+    /'minusin_slot1_pin_b'/ U1.2;
+    /'plusin_slot1_pin3_a'/ U1.3;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/bae/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net
new file mode 100644
index 0000000..6450391
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp-output.net
@@ -0,0 +1,39 @@
+LAYOUT board;
+PARTS
+    Cout : unknown;
+    R5 : unknown;
+    R4 : unknown;
+    RE2 : unknown;
+    Q2 : unknown;
+    A3 : unknown;
+    R3 : unknown;
+    A2 : unknown;
+    RE1 : unknown;
+    Q1 : unknown;
+    A1 : unknown;
+    R2 : unknown;
+    Vinput : none;
+    R1 : unknown;
+    C2 : unknown;
+    CE2 : unknown;
+    C1 : unknown;
+    CE1 : unknown;
+    R8 : unknown;
+    VCC : none;
+    RC2 : unknown;
+    RC1 : unknown;
+    RL : unknown;
+CONNECT
+    /'unnamed_net2'/ C2.1=R8.2;
+    /'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
+    /'Vem2'/ CE2.2=RE2.2=Q2.1;
+    /'Vout'/ Cout.2=RL.2;
+    /'VColl2'/ Q2.3=Cout.1=RC2.1;
+    /'GND'/ R4.1=CE2.1=RE2.1=VCC.2=Vinput.2=CE1.1=RL.1=RE1.1=R2.1;
+    /'Vcc'/ R3.2=RC1.2=VCC.1=RC2.2=R1.2;
+    /'Vin'/ Vinput.1=R5.1;
+    /'unnamed_net1'/ C1.1=R5.2;
+    /'Vbase1'/ C1.2=R2.2=R1.1=Q1.2;
+    /'Vem1'/ CE1.2=RE1.2=Q1.1;
+    /'Vcoll1'/ R8.1=RC1.1=Q1.3;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/bae/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..6450391
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include-output.net
@@ -0,0 +1,39 @@
+LAYOUT board;
+PARTS
+    Cout : unknown;
+    R5 : unknown;
+    R4 : unknown;
+    RE2 : unknown;
+    Q2 : unknown;
+    A3 : unknown;
+    R3 : unknown;
+    A2 : unknown;
+    RE1 : unknown;
+    Q1 : unknown;
+    A1 : unknown;
+    R2 : unknown;
+    Vinput : none;
+    R1 : unknown;
+    C2 : unknown;
+    CE2 : unknown;
+    C1 : unknown;
+    CE1 : unknown;
+    R8 : unknown;
+    VCC : none;
+    RC2 : unknown;
+    RC1 : unknown;
+    RL : unknown;
+CONNECT
+    /'unnamed_net2'/ C2.1=R8.2;
+    /'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
+    /'Vem2'/ CE2.2=RE2.2=Q2.1;
+    /'Vout'/ Cout.2=RL.2;
+    /'VColl2'/ Q2.3=Cout.1=RC2.1;
+    /'GND'/ R4.1=CE2.1=RE2.1=VCC.2=Vinput.2=CE1.1=RL.1=RE1.1=R2.1;
+    /'Vcc'/ R3.2=RC1.2=VCC.1=RC2.2=R1.2;
+    /'Vin'/ Vinput.1=R5.1;
+    /'unnamed_net1'/ C1.1=R5.2;
+    /'Vbase1'/ C1.2=R2.2=R1.1=Q1.2;
+    /'Vem1'/ CE1.2=RE1.2=Q1.1;
+    /'Vcoll1'/ R8.1=RC1.1=Q1.3;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..6450391
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort-output.net
@@ -0,0 +1,39 @@
+LAYOUT board;
+PARTS
+    Cout : unknown;
+    R5 : unknown;
+    R4 : unknown;
+    RE2 : unknown;
+    Q2 : unknown;
+    A3 : unknown;
+    R3 : unknown;
+    A2 : unknown;
+    RE1 : unknown;
+    Q1 : unknown;
+    A1 : unknown;
+    R2 : unknown;
+    Vinput : none;
+    R1 : unknown;
+    C2 : unknown;
+    CE2 : unknown;
+    C1 : unknown;
+    CE1 : unknown;
+    R8 : unknown;
+    VCC : none;
+    RC2 : unknown;
+    RC1 : unknown;
+    RL : unknown;
+CONNECT
+    /'unnamed_net2'/ C2.1=R8.2;
+    /'Vbase2'/ R3.1=C2.2=R4.2=Q2.2;
+    /'Vem2'/ CE2.2=RE2.2=Q2.1;
+    /'Vout'/ Cout.2=RL.2;
+    /'VColl2'/ Q2.3=Cout.1=RC2.1;
+    /'GND'/ R4.1=CE2.1=RE2.1=VCC.2=Vinput.2=CE1.1=RL.1=RE1.1=R2.1;
+    /'Vcc'/ R3.2=RC1.2=VCC.1=RC2.2=R1.2;
+    /'Vin'/ Vinput.1=R5.1;
+    /'unnamed_net1'/ C1.1=R5.2;
+    /'Vbase1'/ C1.2=R2.2=R1.1=Q1.2;
+    /'Vem1'/ CE1.2=RE1.2=Q1.1;
+    /'Vcoll1'/ R8.1=RC1.1=Q1.3;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/cascade-output.net b/gnetlist/tests/common/outputs/bae/cascade-output.net
new file mode 100644
index 0000000..fbef6eb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/cascade-output.net
@@ -0,0 +1,19 @@
+LAYOUT board;
+PARTS
+    AMP2 : none;
+    AMP1 : none;
+    SOURCE : none;
+    DEFAULTS : unknown;
+    MX1 : none;
+    DEF1 : none;
+    T1 : none;
+    FL1 : none;
+CONNECT
+    /'unnamed_net6'/ AMP2.1=T1.2;
+    /'unnamed_net5'/ T1.1=MX1.2;
+    /'unnamed_net4'/ MX1.1=FL1.2;
+    /'unnamed_net3'/ FL1.1=DEF1.2;
+    /'unnamed_net2'/ DEF1.1=AMP1.2;
+    /'unnamed_net1'/ AMP1.1=SOURCE.1;
+    /'GND'/ DEFAULTS.1;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/cascade.retcode b/gnetlist/tests/common/outputs/bae/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/multiequal-output.net b/gnetlist/tests/common/outputs/bae/multiequal-output.net
new file mode 100644
index 0000000..0cd5f05
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/multiequal-output.net
@@ -0,0 +1,9 @@
+LAYOUT board;
+PARTS
+    V1 : none;
+    A1 : unknown;
+    R1 : unknown;
+CONNECT
+    /'GND'/ V1.2=R1.1;
+    /'unnamed_net1'/ V1.1=R1.2;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/multiequal.retcode b/gnetlist/tests/common/outputs/bae/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/netattrib-output.net b/gnetlist/tests/common/outputs/bae/netattrib-output.net
new file mode 100644
index 0000000..8534472
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/netattrib-output.net
@@ -0,0 +1,13 @@
+LAYOUT board;
+PARTS
+    F1 : unknown;
+    U100 : DIP14;
+    U300 : DIP14;
+    U200 : DIP14;
+CONNECT
+    /'unnamed_net1'/ U300.2;
+    /'netattrib'/ U200.2=U100.5;
+    /'GND'/ U300.7=U200.7=U100.7;
+    /'Vcc'/ U300.14=U200.14=U100.14;
+    /'one'/ F1.1=U300.1=U200.1=U100.3;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/netattrib.retcode b/gnetlist/tests/common/outputs/bae/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/powersupply-output.net b/gnetlist/tests/common/outputs/bae/powersupply-output.net
new file mode 100644
index 0000000..86ab354
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/powersupply-output.net
@@ -0,0 +1,27 @@
+LAYOUT board;
+PARTS
+    F1 : unknown;
+    R2 : unknown;
+    CONN1 : unknown;
+    C4 : unknown;
+    R1 : unknown;
+    C3 : unknown;
+    C2 : unknown;
+    S1 : unknown;
+    C1 : unknown;
+    T1 : unknown;
+    U2 : unknown;
+    U1 : unknown;
+CONNECT
+    /'ten'/ U2.1=R1.2=C3.1=R2.1;
+    /'eleven'/ U2.2=C4.1=R2.2;
+    /'GND'/ CONN1.3;
+    /'one'/ S1.1=CONN1.1;
+    /'five'/ CONN1.2=T1.2;
+    /'three'/ T1.1=F1.2;
+    /'two'/ S1.2=F1.1;
+    /'six'/ T1.3=U1.4;
+    /'seven'/ T1.4=U1.3;
+    /'nine'/ C4.2=C3.2=R1.3=R1.1=C2.2=C1.2=U1.2;
+    /'eight'/ U2.3=C2.1=C1.1=U1.1;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/powersupply.retcode b/gnetlist/tests/common/outputs/bae/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bae/singlenet-output.net b/gnetlist/tests/common/outputs/bae/singlenet-output.net
new file mode 100644
index 0000000..463bb30
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/singlenet-output.net
@@ -0,0 +1,9 @@
+LAYOUT board;
+PARTS
+    U100 : DIP14;
+CONNECT
+    /'SING_N_2'/ U100.1=U100.3;
+    /'GND'/ U100.7;
+    /'Vcc'/ U100.14;
+    /'SING_N'/ U100.4=U100.5=U100.10=U100.8=U100.9=U100.6;
+END.
diff --git a/gnetlist/tests/common/outputs/bae/singlenet.retcode b/gnetlist/tests/common/outputs/bae/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bae/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/.gitignore b/gnetlist/tests/common/outputs/bom/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/bom/JD-output.net b/gnetlist/tests/common/outputs/bom/JD-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/JD.retcode b/gnetlist/tests/common/outputs/bom/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include-output.net b/gnetlist/tests/common/outputs/bom/JD_Include-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Include-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include.retcode b/gnetlist/tests/common/outputs/bom/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort-output.net b/gnetlist/tests/common/outputs/bom/JD_Sort-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort.retcode b/gnetlist/tests/common/outputs/bom/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net
new file mode 100644
index 0000000..e7a17b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/JD_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes	refdes	value	device	
+V1	V1	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	vpulse	
+Cm	Cm	20p	CAPACITOR	
+A1	A1	unknown	model	
+Rt	Rt	1k	RESISTOR	
+M1	M1	unknown	PMOS_TRANSISTOR	
+X1	X1	unknown	LVD	
+Rlp	Rlp	1meg	RESISTOR	
+Vdd	Vdd	DC 3.3V	VOLTAGE_SOURCE	
+Rlm	Rlm	500k	RESISTOR	
+Cp	Cp	20p	CAPACITOR	
+Rb	Rb	5.6k	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/Makefile.am b/gnetlist/tests/common/outputs/bom/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/bom/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/bom/SlottedOpamps-output.net
new file mode 100644
index 0000000..d52328d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/SlottedOpamps-output.net
@@ -0,0 +1,2 @@
+refdes	refdes	value	device	
+U1	U1	unknown	LM324	
diff --git a/gnetlist/tests/common/outputs/bom/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/bom/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net
new file mode 100644
index 0000000..ebb4a75
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp-output.net
@@ -0,0 +1,24 @@
+refdes	refdes	value	device	
+Cout	Cout	2.2uF	CAPACITOR	
+R5	R5	10	RESISTOR	
+R4	R4	2.8K	RESISTOR	
+RE2	RE2	100	RESISTOR	
+Q2	Q2	unknown	NPN_TRANSISTOR	
+A3	A3	.options TEMP=25	directive	
+R3	R3	28K	RESISTOR	
+A2	A2	unknown	include	
+RE1	RE1	100	RESISTOR	
+Q1	Q1	unknown	NPN_TRANSISTOR	
+A1	A1	unknown	model	
+R2	R2	2K	RESISTOR	
+Vinput	Vinput	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	vsin	
+R1	R1	28K	RESISTOR	
+C2	C2	2.2uF	CAPACITOR	
+CE2	CE2	1pF	CAPACITOR	
+C1	C1	2.2uF	CAPACITOR	
+CE1	CE1	1pF	CAPACITOR	
+R8	R8	1	RESISTOR	
+VCC	VCC	DC 15V	VOLTAGE_SOURCE	
+RC2	RC2	1K	RESISTOR	
+RC1	RC1	3.3K	RESISTOR	
+RL	RL	100K	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/bom/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..ebb4a75
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include-output.net
@@ -0,0 +1,24 @@
+refdes	refdes	value	device	
+Cout	Cout	2.2uF	CAPACITOR	
+R5	R5	10	RESISTOR	
+R4	R4	2.8K	RESISTOR	
+RE2	RE2	100	RESISTOR	
+Q2	Q2	unknown	NPN_TRANSISTOR	
+A3	A3	.options TEMP=25	directive	
+R3	R3	28K	RESISTOR	
+A2	A2	unknown	include	
+RE1	RE1	100	RESISTOR	
+Q1	Q1	unknown	NPN_TRANSISTOR	
+A1	A1	unknown	model	
+R2	R2	2K	RESISTOR	
+Vinput	Vinput	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	vsin	
+R1	R1	28K	RESISTOR	
+C2	C2	2.2uF	CAPACITOR	
+CE2	CE2	1pF	CAPACITOR	
+C1	C1	2.2uF	CAPACITOR	
+CE1	CE1	1pF	CAPACITOR	
+R8	R8	1	RESISTOR	
+VCC	VCC	DC 15V	VOLTAGE_SOURCE	
+RC2	RC2	1K	RESISTOR	
+RC1	RC1	3.3K	RESISTOR	
+RL	RL	100K	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..ebb4a75
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort-output.net
@@ -0,0 +1,24 @@
+refdes	refdes	value	device	
+Cout	Cout	2.2uF	CAPACITOR	
+R5	R5	10	RESISTOR	
+R4	R4	2.8K	RESISTOR	
+RE2	RE2	100	RESISTOR	
+Q2	Q2	unknown	NPN_TRANSISTOR	
+A3	A3	.options TEMP=25	directive	
+R3	R3	28K	RESISTOR	
+A2	A2	unknown	include	
+RE1	RE1	100	RESISTOR	
+Q1	Q1	unknown	NPN_TRANSISTOR	
+A1	A1	unknown	model	
+R2	R2	2K	RESISTOR	
+Vinput	Vinput	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	vsin	
+R1	R1	28K	RESISTOR	
+C2	C2	2.2uF	CAPACITOR	
+CE2	CE2	1pF	CAPACITOR	
+C1	C1	2.2uF	CAPACITOR	
+CE1	CE1	1pF	CAPACITOR	
+R8	R8	1	RESISTOR	
+VCC	VCC	DC 15V	VOLTAGE_SOURCE	
+RC2	RC2	1K	RESISTOR	
+RC1	RC1	3.3K	RESISTOR	
+RL	RL	100K	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/cascade-output.net b/gnetlist/tests/common/outputs/bom/cascade-output.net
new file mode 100644
index 0000000..d13c8ae
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/cascade-output.net
@@ -0,0 +1,9 @@
+refdes	refdes	value	device	
+AMP2	AMP2	unknown	cascade-amp	
+AMP1	AMP1	unknown	cascade-amp	
+SOURCE	SOURCE	unknown	cascade-source	
+DEFAULTS	DEFAULTS	unknown	cascade-defaults-top	
+MX1	MX1	unknown	cascade-mixer	
+DEF1	DEF1	unknown	cascade-defaults	
+T1	T1	unknown	cascade-transformer	
+FL1	FL1	unknown	cascade-filter	
diff --git a/gnetlist/tests/common/outputs/bom/cascade.retcode b/gnetlist/tests/common/outputs/bom/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/multiequal-output.net b/gnetlist/tests/common/outputs/bom/multiequal-output.net
new file mode 100644
index 0000000..fa479d6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/multiequal-output.net
@@ -0,0 +1,4 @@
+refdes	refdes	value	device	
+V1	V1	DC 1V	VOLTAGE_SOURCE	
+A1	A1	abotol=1e-11	options	
+R1	R1	20	RESISTOR	
diff --git a/gnetlist/tests/common/outputs/bom/multiequal.retcode b/gnetlist/tests/common/outputs/bom/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/netattrib-output.net b/gnetlist/tests/common/outputs/bom/netattrib-output.net
new file mode 100644
index 0000000..6d12770
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/netattrib-output.net
@@ -0,0 +1,5 @@
+refdes	refdes	value	device	
+F1	F1	unknown	FUSE	
+U100	U100	unknown	7400	
+U300	U300	unknown	7404	
+U200	U200	unknown	7404	
diff --git a/gnetlist/tests/common/outputs/bom/netattrib.retcode b/gnetlist/tests/common/outputs/bom/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/powersupply-output.net b/gnetlist/tests/common/outputs/bom/powersupply-output.net
new file mode 100644
index 0000000..42c7e2f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/powersupply-output.net
@@ -0,0 +1,13 @@
+refdes	refdes	value	device	
+F1	F1	unknown	FUSE	
+R2	R2	220	RESISTOR	
+CONN1	CONN1	unknown	MAINS_CONNECTOR	
+C4	C4	1uf	POLARIZED_CAPACITOR	
+R1	R1	5k	VARIABLE_RESISTOR	
+C3	C3	22uF	POLARIZED_CAPACITOR	
+C2	C2	0.1uF	POLARIZED_CAPACITOR	
+S1	S1	unknown	SPST	
+C1	C1	2200uF	POLARIZED_CAPACITOR	
+T1	T1	unknown	transformer	
+U2	U2	unknown	LM317	
+U1	U1	unknown	DIODE-BRIDGE	
diff --git a/gnetlist/tests/common/outputs/bom/powersupply.retcode b/gnetlist/tests/common/outputs/bom/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom/singlenet-output.net b/gnetlist/tests/common/outputs/bom/singlenet-output.net
new file mode 100644
index 0000000..f4e5a3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/singlenet-output.net
@@ -0,0 +1,2 @@
+refdes	refdes	value	device	
+U100	U100	unknown	7400	
diff --git a/gnetlist/tests/common/outputs/bom/singlenet.retcode b/gnetlist/tests/common/outputs/bom/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/.gitignore b/gnetlist/tests/common/outputs/bom2/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/bom2/JD-output.net b/gnetlist/tests/common/outputs/bom2/JD-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/JD.retcode b/gnetlist/tests/common/outputs/bom2/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include-output.net b/gnetlist/tests/common/outputs/bom2/JD_Include-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include.retcode b/gnetlist/tests/common/outputs/bom2/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net b/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort.retcode b/gnetlist/tests/common/outputs/bom2/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net
new file mode 100644
index 0000000..5c6ad74
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/JD_nomunge-output.net
@@ -0,0 +1,12 @@
+refdes:refdes:value:device
+Rb:Rb:5.6k:RESISTOR
+Cp:Cp:20p:CAPACITOR
+Rlm:Rlm:500k:RESISTOR
+Vdd:Vdd:DC 3.3V:VOLTAGE_SOURCE
+Rlp:Rlp:1meg:RESISTOR
+X1:X1:unknown:LVD
+M1:M1:unknown:PMOS_TRANSISTOR
+Rt:Rt:1k:RESISTOR
+A1:A1:unknown:model
+Cm:Cm:20p:CAPACITOR
+V1:V1:pulse 3.3 0 1u 10p 10p 1.25u 2.5u:vpulse
diff --git a/gnetlist/tests/common/outputs/bom2/Makefile.am b/gnetlist/tests/common/outputs/bom2/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/bom2/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/bom2/SlottedOpamps-output.net
new file mode 100644
index 0000000..a18ba80
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/SlottedOpamps-output.net
@@ -0,0 +1,2 @@
+refdes:refdes:value:device
+U1:U1:unknown:LM324
diff --git a/gnetlist/tests/common/outputs/bom2/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/bom2/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net
new file mode 100644
index 0000000..ed8994a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp-output.net
@@ -0,0 +1,24 @@
+refdes:refdes:value:device
+RL:RL:100K:RESISTOR
+RC1:RC1:3.3K:RESISTOR
+RC2:RC2:1K:RESISTOR
+VCC:VCC:DC 15V:VOLTAGE_SOURCE
+R8:R8:1:RESISTOR
+CE1:CE1:1pF:CAPACITOR
+C1:C1:2.2uF:CAPACITOR
+CE2:CE2:1pF:CAPACITOR
+C2:C2:2.2uF:CAPACITOR
+R1:R1:28K:RESISTOR
+Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin
+R2:R2:2K:RESISTOR
+A1:A1:unknown:model
+Q1:Q1:unknown:NPN_TRANSISTOR
+RE1:RE1:100:RESISTOR
+A2:A2:unknown:include
+R3:R3:28K:RESISTOR
+A3:A3:.options TEMP=25:directive
+Q2:Q2:unknown:NPN_TRANSISTOR
+RE2:RE2:100:RESISTOR
+R4:R4:2.8K:RESISTOR
+R5:R5:10:RESISTOR
+Cout:Cout:2.2uF:CAPACITOR
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/bom2/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..ed8994a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include-output.net
@@ -0,0 +1,24 @@
+refdes:refdes:value:device
+RL:RL:100K:RESISTOR
+RC1:RC1:3.3K:RESISTOR
+RC2:RC2:1K:RESISTOR
+VCC:VCC:DC 15V:VOLTAGE_SOURCE
+R8:R8:1:RESISTOR
+CE1:CE1:1pF:CAPACITOR
+C1:C1:2.2uF:CAPACITOR
+CE2:CE2:1pF:CAPACITOR
+C2:C2:2.2uF:CAPACITOR
+R1:R1:28K:RESISTOR
+Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin
+R2:R2:2K:RESISTOR
+A1:A1:unknown:model
+Q1:Q1:unknown:NPN_TRANSISTOR
+RE1:RE1:100:RESISTOR
+A2:A2:unknown:include
+R3:R3:28K:RESISTOR
+A3:A3:.options TEMP=25:directive
+Q2:Q2:unknown:NPN_TRANSISTOR
+RE2:RE2:100:RESISTOR
+R4:R4:2.8K:RESISTOR
+R5:R5:10:RESISTOR
+Cout:Cout:2.2uF:CAPACITOR
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..ed8994a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort-output.net
@@ -0,0 +1,24 @@
+refdes:refdes:value:device
+RL:RL:100K:RESISTOR
+RC1:RC1:3.3K:RESISTOR
+RC2:RC2:1K:RESISTOR
+VCC:VCC:DC 15V:VOLTAGE_SOURCE
+R8:R8:1:RESISTOR
+CE1:CE1:1pF:CAPACITOR
+C1:C1:2.2uF:CAPACITOR
+CE2:CE2:1pF:CAPACITOR
+C2:C2:2.2uF:CAPACITOR
+R1:R1:28K:RESISTOR
+Vinput:Vinput:DC 1.6V AC 10MV SIN(0 1MV 1KHZ):vsin
+R2:R2:2K:RESISTOR
+A1:A1:unknown:model
+Q1:Q1:unknown:NPN_TRANSISTOR
+RE1:RE1:100:RESISTOR
+A2:A2:unknown:include
+R3:R3:28K:RESISTOR
+A3:A3:.options TEMP=25:directive
+Q2:Q2:unknown:NPN_TRANSISTOR
+RE2:RE2:100:RESISTOR
+R4:R4:2.8K:RESISTOR
+R5:R5:10:RESISTOR
+Cout:Cout:2.2uF:CAPACITOR
diff --git a/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/cascade-output.net b/gnetlist/tests/common/outputs/bom2/cascade-output.net
new file mode 100644
index 0000000..cce44a9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/cascade-output.net
@@ -0,0 +1,9 @@
+refdes:refdes:value:device
+FL1:FL1:unknown:cascade-filter
+T1:T1:unknown:cascade-transformer
+DEF1:DEF1:unknown:cascade-defaults
+MX1:MX1:unknown:cascade-mixer
+DEFAULTS:DEFAULTS:unknown:cascade-defaults-top
+SOURCE:SOURCE:unknown:cascade-source
+AMP1:AMP1:unknown:cascade-amp
+AMP2:AMP2:unknown:cascade-amp
diff --git a/gnetlist/tests/common/outputs/bom2/cascade.retcode b/gnetlist/tests/common/outputs/bom2/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/multiequal-output.net b/gnetlist/tests/common/outputs/bom2/multiequal-output.net
new file mode 100644
index 0000000..a559c42
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/multiequal-output.net
@@ -0,0 +1,4 @@
+refdes:refdes:value:device
+R1:R1:20:RESISTOR
+A1:A1:abotol=1e-11:options
+V1:V1:DC 1V:VOLTAGE_SOURCE
diff --git a/gnetlist/tests/common/outputs/bom2/multiequal.retcode b/gnetlist/tests/common/outputs/bom2/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/netattrib-output.net b/gnetlist/tests/common/outputs/bom2/netattrib-output.net
new file mode 100644
index 0000000..74759b2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/netattrib-output.net
@@ -0,0 +1,5 @@
+refdes:refdes:value:device
+U200:U200:unknown:7404
+U300:U300:unknown:7404
+U100:U100:unknown:7400
+F1:F1:unknown:FUSE
diff --git a/gnetlist/tests/common/outputs/bom2/netattrib.retcode b/gnetlist/tests/common/outputs/bom2/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/powersupply-output.net b/gnetlist/tests/common/outputs/bom2/powersupply-output.net
new file mode 100644
index 0000000..6726452
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/powersupply-output.net
@@ -0,0 +1,13 @@
+refdes:refdes:value:device
+U1:U1:unknown:DIODE-BRIDGE
+U2:U2:unknown:LM317
+T1:T1:unknown:transformer
+C1:C1:2200uF:POLARIZED_CAPACITOR
+S1:S1:unknown:SPST
+C2:C2:0.1uF:POLARIZED_CAPACITOR
+C3:C3:22uF:POLARIZED_CAPACITOR
+R1:R1:5k:VARIABLE_RESISTOR
+C4:C4:1uf:POLARIZED_CAPACITOR
+CONN1:CONN1:unknown:MAINS_CONNECTOR
+R2:R2:220:RESISTOR
+F1:F1:unknown:FUSE
diff --git a/gnetlist/tests/common/outputs/bom2/powersupply.retcode b/gnetlist/tests/common/outputs/bom2/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/bom2/singlenet-output.net b/gnetlist/tests/common/outputs/bom2/singlenet-output.net
new file mode 100644
index 0000000..5a90273
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/singlenet-output.net
@@ -0,0 +1,2 @@
+refdes:refdes:value:device
+U100:U100:unknown:7400
diff --git a/gnetlist/tests/common/outputs/bom2/singlenet.retcode b/gnetlist/tests/common/outputs/bom2/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/bom2/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/.gitignore b/gnetlist/tests/common/outputs/calay/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/calay/JD-output.net b/gnetlist/tests/common/outputs/calay/JD-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/JD.retcode b/gnetlist/tests/common/outputs/calay/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/JD_Include-output.net b/gnetlist/tests/common/outputs/calay/JD_Include-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Include-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/JD_Include.retcode b/gnetlist/tests/common/outputs/calay/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/calay/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Include_nomunge-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/calay/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/JD_Sort-output.net b/gnetlist/tests/common/outputs/calay/JD_Sort-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Sort-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/JD_Sort.retcode b/gnetlist/tests/common/outputs/calay/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/JD_nomunge-output.net b/gnetlist/tests/common/outputs/calay/JD_nomunge-output.net
new file mode 100644
index 0000000..9cb9ab4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/JD_nomunge-output.net
@@ -0,0 +1,6 @@
+/Vdd1	 Rlp(2) M1(B) M1(S) Vdd(1) X1(6);
+/GND	 Cm(2) Cp(2) Rlm(2) Vdd(2) V1(2) Rb(1) X1(7) X1(2);
+/LVH	 Rb(2) M1(D) M1(G) X1(3);
+/i	 V1(1) X1(1);
+/p	 Cp(1) Rt(1) Rlp(1) X1(5);
+/m	 Cm(1) Rlm(1) Rt(2) X1(4);
diff --git a/gnetlist/tests/common/outputs/calay/Makefile.am b/gnetlist/tests/common/outputs/calay/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/calay/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/calay/SlottedOpamps-output.net
new file mode 100644
index 0000000..0ebce2d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/SlottedOpamps-output.net
@@ -0,0 +1,9 @@
+/minusin-slot4-pin13-b	 U1(13);
+/plusin-slot4-pin12-a	 U1(12);
+/minusin-slot3-pin-b	 U1(9);
+/plusin-slot3-pin10-a	 U1(10);
+/minusin-slot2-pin6-b	 U1(6);
+/plusin-slot2-pin5-a	 U1(5);
+/samenet-output-c	 U1(14) U1(8) U1(7) U1(1);
+/minusin-slot1-pin-b	 U1(2);
+/plusin-slot1-pin3-a	 U1(3);
diff --git a/gnetlist/tests/common/outputs/calay/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/calay/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/calay/TwoStageAmp-output.net
new file mode 100644
index 0000000..93c1b80
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp-output.net
@@ -0,0 +1,12 @@
+/unnamed-net2	 C2(1) R8(2);
+/Vbase2	 R3(1) C2(2) R4(2) Q2(2);
+/Vem2	 CE2(2) RE2(2) Q2(1);
+/Vout	 Cout(2) RL(2);
+/VColl2	 Q2(3) Cout(1) RC2(1);
+/GND	 R4(1) CE2(1) RE2(1) VCC(2) Vinput(2) CE1(1) RL(1) RE1(1) R2(1);
+/Vcc	 R3(2) RC1(2) VCC(1) RC2(2) R1(2);
+/Vin	 Vinput(1) R5(1);
+/unnamed-net1	 C1(1) R5(2);
+/Vbase1	 C1(2) R2(2) R1(1) Q1(2);
+/Vem1	 CE1(2) RE1(2) Q1(1);
+/Vcoll1	 R8(1) RC1(1) Q1(3);
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/calay/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..93c1b80
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include-output.net
@@ -0,0 +1,12 @@
+/unnamed-net2	 C2(1) R8(2);
+/Vbase2	 R3(1) C2(2) R4(2) Q2(2);
+/Vem2	 CE2(2) RE2(2) Q2(1);
+/Vout	 Cout(2) RL(2);
+/VColl2	 Q2(3) Cout(1) RC2(1);
+/GND	 R4(1) CE2(1) RE2(1) VCC(2) Vinput(2) CE1(1) RL(1) RE1(1) R2(1);
+/Vcc	 R3(2) RC1(2) VCC(1) RC2(2) R1(2);
+/Vin	 Vinput(1) R5(1);
+/unnamed-net1	 C1(1) R5(2);
+/Vbase1	 C1(2) R2(2) R1(1) Q1(2);
+/Vem1	 CE1(2) RE1(2) Q1(1);
+/Vcoll1	 R8(1) RC1(1) Q1(3);
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..93c1b80
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort-output.net
@@ -0,0 +1,12 @@
+/unnamed-net2	 C2(1) R8(2);
+/Vbase2	 R3(1) C2(2) R4(2) Q2(2);
+/Vem2	 CE2(2) RE2(2) Q2(1);
+/Vout	 Cout(2) RL(2);
+/VColl2	 Q2(3) Cout(1) RC2(1);
+/GND	 R4(1) CE2(1) RE2(1) VCC(2) Vinput(2) CE1(1) RL(1) RE1(1) R2(1);
+/Vcc	 R3(2) RC1(2) VCC(1) RC2(2) R1(2);
+/Vin	 Vinput(1) R5(1);
+/unnamed-net1	 C1(1) R5(2);
+/Vbase1	 C1(2) R2(2) R1(1) Q1(2);
+/Vem1	 CE1(2) RE1(2) Q1(1);
+/Vcoll1	 R8(1) RC1(1) Q1(3);
diff --git a/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/cascade-output.net b/gnetlist/tests/common/outputs/calay/cascade-output.net
new file mode 100644
index 0000000..3a32e9d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/cascade-output.net
@@ -0,0 +1,7 @@
+/unnamed-net6	 AMP2(1) T1(2);
+/unnamed-net5	 T1(1) MX1(2);
+/unnamed-net4	 MX1(1) FL1(2);
+/unnamed-net3	 FL1(1) DEF1(2);
+/unnamed-net2	 DEF1(1) AMP1(2);
+/unnamed-net1	 AMP1(1) SOURCE(1);
+/GND	 DEFAULTS(1);
diff --git a/gnetlist/tests/common/outputs/calay/cascade.retcode b/gnetlist/tests/common/outputs/calay/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/multiequal-output.net b/gnetlist/tests/common/outputs/calay/multiequal-output.net
new file mode 100644
index 0000000..2ccc9de
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/multiequal-output.net
@@ -0,0 +1,2 @@
+/GND	 V1(2) R1(1);
+/unnamed-net1	 V1(1) R1(2);
diff --git a/gnetlist/tests/common/outputs/calay/multiequal.retcode b/gnetlist/tests/common/outputs/calay/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/netattrib-output.net b/gnetlist/tests/common/outputs/calay/netattrib-output.net
new file mode 100644
index 0000000..03968c7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/netattrib-output.net
@@ -0,0 +1,5 @@
+/unnamed-net1	 U300(2);
+/netattrib	 U200(2) U100(5);
+/GND	 U300(7) U200(7) U100(7);
+/Vcc	 U300(14) U200(14) U100(14);
+/one	 F1(1) U300(1) U200(1) U100(3);
diff --git a/gnetlist/tests/common/outputs/calay/netattrib.retcode b/gnetlist/tests/common/outputs/calay/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/powersupply-output.net b/gnetlist/tests/common/outputs/calay/powersupply-output.net
new file mode 100644
index 0000000..ffbfdaa
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/powersupply-output.net
@@ -0,0 +1,11 @@
+/ten	 U2(1) R1(2) C3(1) R2(1);
+/eleven	 U2(2) C4(1) R2(2);
+/GND	 CONN1(3);
+/one	 S1(1) CONN1(1);
+/five	 CONN1(2) T1(2);
+/three	 T1(1) F1(2);
+/two	 S1(2) F1(1);
+/six	 T1(3) U1(4);
+/seven	 T1(4) U1(3);
+/nine	 C4(2) C3(2) R1(3) R1(1) C2(2) C1(2) U1(2);
+/eight	 U2(3) C2(1) C1(1) U1(1);
diff --git a/gnetlist/tests/common/outputs/calay/powersupply.retcode b/gnetlist/tests/common/outputs/calay/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/calay/singlenet-output.net b/gnetlist/tests/common/outputs/calay/singlenet-output.net
new file mode 100644
index 0000000..41c51a4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/singlenet-output.net
@@ -0,0 +1,4 @@
+/SING-N-2	 U100(1) U100(3);
+/GND	 U100(7);
+/Vcc	 U100(14);
+/SING-N	 U100(4) U100(5) U100(10) U100(8) U100(9) U100(6);
diff --git a/gnetlist/tests/common/outputs/calay/singlenet.retcode b/gnetlist/tests/common/outputs/calay/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/calay/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/cascade/.gitignore b/gnetlist/tests/common/outputs/cascade/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/cascade/JD-output.net b/gnetlist/tests/common/outputs/cascade/JD-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/JD.retcode b/gnetlist/tests/common/outputs/cascade/JD.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Include-output.net b/gnetlist/tests/common/outputs/cascade/JD_Include-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Include-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Include.retcode b/gnetlist/tests/common/outputs/cascade/JD_Include.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Include.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Sort-output.net b/gnetlist/tests/common/outputs/cascade/JD_Sort-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Sort-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Sort.retcode b/gnetlist/tests/common/outputs/cascade/JD_Sort.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Sort.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/JD_nomunge-output.net b/gnetlist/tests/common/outputs/cascade/JD_nomunge-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/JD_nomunge-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/Makefile.am b/gnetlist/tests/common/outputs/cascade/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/cascade/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/cascade/SlottedOpamps-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/SlottedOpamps-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/cascade/SlottedOpamps.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/SlottedOpamps.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/cascade/TwoStageAmp-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/cascade/TwoStageAmp.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/cascade-output.net b/gnetlist/tests/common/outputs/cascade/cascade-output.net
new file mode 100644
index 0000000..e11fa3c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/cascade-output.net
@@ -0,0 +1,19 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Initial global defaults
+defaults RIN=50 ROUT=50 RHO=0 
+
+# Source definition
+source C=0 CN=70 BW=1 
+
+# Cascaded system
+AMP1 G=12 NF=5 IIP3=-2 
+defaults RIN=50 ROUT=50 RHO=0.2 
+FL1 G=-5.5 NF=5.5 
+MX1 G=12 NF=15 IIP3=5 
+T1 G=0 NF=0 RIN=50 ROUT=50 
+AMP2 G=10 NF=12 IIP3=12 
+
+# End of netlist created by gEDA/gnetlist
+
diff --git a/gnetlist/tests/common/outputs/cascade/cascade.retcode b/gnetlist/tests/common/outputs/cascade/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/cascade/multiequal-output.net b/gnetlist/tests/common/outputs/cascade/multiequal-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/multiequal-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/multiequal.retcode b/gnetlist/tests/common/outputs/cascade/multiequal.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/multiequal.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/netattrib-output.net b/gnetlist/tests/common/outputs/cascade/netattrib-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/netattrib-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/netattrib.retcode b/gnetlist/tests/common/outputs/cascade/netattrib.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/netattrib.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/powersupply-output.net b/gnetlist/tests/common/outputs/cascade/powersupply-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/powersupply-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/powersupply.retcode b/gnetlist/tests/common/outputs/cascade/powersupply.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/powersupply.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/cascade/singlenet-output.net b/gnetlist/tests/common/outputs/cascade/singlenet-output.net
new file mode 100644
index 0000000..9ae22bf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/singlenet-output.net
@@ -0,0 +1,4 @@
+# Cascade (http://rfcascade.sourceforge.net)
+# Created with gEDA/gnetlist
+
+# Source definition
diff --git a/gnetlist/tests/common/outputs/cascade/singlenet.retcode b/gnetlist/tests/common/outputs/cascade/singlenet.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/cascade/singlenet.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/drc/.gitignore b/gnetlist/tests/common/outputs/drc/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/drc/JD-output.net b/gnetlist/tests/common/outputs/drc/JD-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/JD.retcode b/gnetlist/tests/common/outputs/drc/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/JD_Include-output.net b/gnetlist/tests/common/outputs/drc/JD_Include-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Include-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/JD_Include.retcode b/gnetlist/tests/common/outputs/drc/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/drc/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Include_nomunge-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/drc/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/JD_Sort-output.net b/gnetlist/tests/common/outputs/drc/JD_Sort-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Sort-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/JD_Sort.retcode b/gnetlist/tests/common/outputs/drc/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/JD_nomunge-output.net b/gnetlist/tests/common/outputs/drc/JD_nomunge-output.net
new file mode 100644
index 0000000..8b1b477
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/JD_nomunge-output.net
@@ -0,0 +1,3 @@
+A1 Does not have attribute: value
+M1 Does not have attribute: value
+X1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/Makefile.am b/gnetlist/tests/common/outputs/drc/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/drc/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/drc/SlottedOpamps-output.net
new file mode 100644
index 0000000..a0c88d1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/SlottedOpamps-output.net
@@ -0,0 +1,9 @@
+U1 Does not have attribute: value
+Net minusin_slot4_pin13_b has only 1 connected pin
+Net plusin_slot4_pin12_a has only 1 connected pin
+Net minusin_slot3_pin_b has only 1 connected pin
+Net plusin_slot3_pin10_a has only 1 connected pin
+Net minusin_slot2_pin6_b has only 1 connected pin
+Net plusin_slot2_pin5_a has only 1 connected pin
+Net minusin_slot1_pin_b has only 1 connected pin
+Net plusin_slot1_pin3_a has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/drc/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net
new file mode 100644
index 0000000..aa8646b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp-output.net
@@ -0,0 +1,4 @@
+Q2 Does not have attribute: value
+A2 Does not have attribute: value
+Q1 Does not have attribute: value
+A1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/drc/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..aa8646b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include-output.net
@@ -0,0 +1,4 @@
+Q2 Does not have attribute: value
+A2 Does not have attribute: value
+Q1 Does not have attribute: value
+A1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..aa8646b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort-output.net
@@ -0,0 +1,4 @@
+Q2 Does not have attribute: value
+A2 Does not have attribute: value
+Q1 Does not have attribute: value
+A1 Does not have attribute: value
diff --git a/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/cascade-output.net b/gnetlist/tests/common/outputs/drc/cascade-output.net
new file mode 100644
index 0000000..8792376
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/cascade-output.net
@@ -0,0 +1,9 @@
+AMP2 Does not have attribute: value
+AMP1 Does not have attribute: value
+SOURCE Does not have attribute: value
+DEFAULTS Does not have attribute: value
+MX1 Does not have attribute: value
+DEF1 Does not have attribute: value
+T1 Does not have attribute: value
+FL1 Does not have attribute: value
+Net GND has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/cascade.retcode b/gnetlist/tests/common/outputs/drc/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/multiequal-output.net b/gnetlist/tests/common/outputs/drc/multiequal-output.net
new file mode 100644
index 0000000..e69de29
diff --git a/gnetlist/tests/common/outputs/drc/multiequal.retcode b/gnetlist/tests/common/outputs/drc/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/netattrib-output.net b/gnetlist/tests/common/outputs/drc/netattrib-output.net
new file mode 100644
index 0000000..db5b794
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/netattrib-output.net
@@ -0,0 +1,5 @@
+F1 Does not have attribute: value
+U100 Does not have attribute: value
+U300 Does not have attribute: value
+U200 Does not have attribute: value
+Net unnamed_net1 has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/netattrib.retcode b/gnetlist/tests/common/outputs/drc/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/powersupply-output.net b/gnetlist/tests/common/outputs/drc/powersupply-output.net
new file mode 100644
index 0000000..f29bd92
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/powersupply-output.net
@@ -0,0 +1,7 @@
+F1 Does not have attribute: value
+CONN1 Does not have attribute: value
+S1 Does not have attribute: value
+T1 Does not have attribute: value
+U2 Does not have attribute: value
+U1 Does not have attribute: value
+Net GND has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/powersupply.retcode b/gnetlist/tests/common/outputs/drc/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc/singlenet-output.net b/gnetlist/tests/common/outputs/drc/singlenet-output.net
new file mode 100644
index 0000000..3ad2d65
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/singlenet-output.net
@@ -0,0 +1,3 @@
+U100 Does not have attribute: value
+Net GND has only 1 connected pin
+Net Vcc has only 1 connected pin
diff --git a/gnetlist/tests/common/outputs/drc/singlenet.retcode b/gnetlist/tests/common/outputs/drc/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/.gitignore b/gnetlist/tests/common/outputs/drc2/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/drc2/JD-output.net b/gnetlist/tests/common/outputs/drc2/JD-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/JD.retcode b/gnetlist/tests/common/outputs/drc2/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Include-output.net b/gnetlist/tests/common/outputs/drc2/JD_Include-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Include-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Include.retcode b/gnetlist/tests/common/outputs/drc2/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Sort-output.net b/gnetlist/tests/common/outputs/drc2/JD_Sort-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Sort-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Sort.retcode b/gnetlist/tests/common/outputs/drc2/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/drc2/JD_nomunge-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/JD_nomunge-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/Makefile.am b/gnetlist/tests/common/outputs/drc2/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/drc2/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/drc2/SlottedOpamps-output.net
new file mode 100644
index 0000000..207d06e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/SlottedOpamps-output.net
@@ -0,0 +1,28 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+ERROR: Net 'minusin_slot4_pin13_b' is connected to only one pin: U1:13 .
+ERROR: Net 'plusin_slot4_pin12_a' is connected to only one pin: U1:12 .
+ERROR: Net 'minusin_slot3_pin_b' is connected to only one pin: U1:9 .
+ERROR: Net 'plusin_slot3_pin10_a' is connected to only one pin: U1:10 .
+ERROR: Net 'minusin_slot2_pin6_b' is connected to only one pin: U1:6 .
+ERROR: Net 'plusin_slot2_pin5_a' is connected to only one pin: U1:5 .
+ERROR: Net 'minusin_slot1_pin_b' is connected to only one pin: U1:2 .
+ERROR: Net 'plusin_slot1_pin3_a' is connected to only one pin: U1:3 .
+
+Checking pins without the 'pintype' attribute...
+NOTE: Found pins without the 'pintype' attribute: U1:13 U1:12 U1:9 U1:10 U1:6 U1:5 U1:14 U1:8 U1:7 U1:1 U1:2 U1:3 
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+Found 8 errors.
diff --git a/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/drc2/TwoStageAmp-output.net
new file mode 100644
index 0000000..842374f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+NOTE: Found pins without the 'pintype' attribute: Q2:2 Q2:1 Q2:3 Q1:2 Q1:1 Q1:3 
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/drc2/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..842374f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+NOTE: Found pins without the 'pintype' attribute: Q2:2 Q2:1 Q2:3 Q1:2 Q1:1 Q1:3 
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..842374f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+NOTE: Found pins without the 'pintype' attribute: Q2:2 Q2:1 Q2:3 Q1:2 Q1:1 Q1:3 
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/cascade-output.net b/gnetlist/tests/common/outputs/drc2/cascade-output.net
new file mode 100644
index 0000000..25cbe0f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/cascade-output.net
@@ -0,0 +1,22 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+ERROR: Net 'GND' is connected to only one pin: DEFAULTS:1 .
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+ERROR: Unconnected pin AMP2:2
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+Found 2 errors.
diff --git a/gnetlist/tests/common/outputs/drc2/cascade.retcode b/gnetlist/tests/common/outputs/drc2/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/multiequal-output.net b/gnetlist/tests/common/outputs/drc2/multiequal-output.net
new file mode 100644
index 0000000..110219f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/multiequal-output.net
@@ -0,0 +1,20 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+No errors found. 
diff --git a/gnetlist/tests/common/outputs/drc2/multiequal.retcode b/gnetlist/tests/common/outputs/drc2/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/netattrib-output.net b/gnetlist/tests/common/outputs/drc2/netattrib-output.net
new file mode 100644
index 0000000..7a4e5e0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/netattrib-output.net
@@ -0,0 +1,40 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+ERROR: Net 'unnamed_net1' is connected to only one pin: U300:2 .
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+ERROR: Pin(s) with pintype 'output': U200:2 
+	are connected by net 'netattrib'
+	to pin(s) with pintype 'power': U100:5 
+
+Checking unconnected pins...
+ERROR: Unconnected pin F1:2
+ERROR: Unconnected pin U100:2
+ERROR: Unconnected pin U100:1
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+WARNING: Unused slot 2 of uref U100
+WARNING: Unused slot 3 of uref U100
+WARNING: Unused slot 4 of uref U100
+WARNING: Unused slot 2 of uref U300
+WARNING: Unused slot 3 of uref U300
+WARNING: Unused slot 4 of uref U300
+WARNING: Unused slot 5 of uref U300
+WARNING: Unused slot 6 of uref U300
+WARNING: Unused slot 2 of uref U200
+WARNING: Unused slot 3 of uref U200
+WARNING: Unused slot 4 of uref U200
+WARNING: Unused slot 5 of uref U200
+WARNING: Unused slot 6 of uref U200
+
+Found 13 warnings.
+Found 5 errors.
diff --git a/gnetlist/tests/common/outputs/drc2/netattrib.retcode b/gnetlist/tests/common/outputs/drc2/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/powersupply-output.net b/gnetlist/tests/common/outputs/drc2/powersupply-output.net
new file mode 100644
index 0000000..19c9a5c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/powersupply-output.net
@@ -0,0 +1,21 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+ERROR: Net 'GND' is connected to only one pin: CONN1:3 .
+
+Checking pins without the 'pintype' attribute...
+NOTE: Found pins without the 'pintype' attribute: U2:1 U2:2 U2:3 
+Checking type of pins connected to a net...
+
+Checking unconnected pins...
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+
+No warnings found. 
+Found 1 errors.
diff --git a/gnetlist/tests/common/outputs/drc2/powersupply.retcode b/gnetlist/tests/common/outputs/drc2/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/drc2/singlenet-output.net b/gnetlist/tests/common/outputs/drc2/singlenet-output.net
new file mode 100644
index 0000000..ba21abd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/singlenet-output.net
@@ -0,0 +1,27 @@
+Checking non-numbered parts...
+
+Checking duplicated references...
+
+Checking nets with only one connection...
+ERROR: Net 'GND' is connected to only one pin: U100:7 .
+ERROR: Net 'Vcc' is connected to only one pin: U100:14 .
+
+Checking pins without the 'pintype' attribute...
+
+Checking type of pins connected to a net...
+ERROR: Pin(s) with pintype 'output': U100:8 U100:6 
+	are connected by net 'SING_N'
+	to pin(s) with pintype 'output': U100:8 U100:6 
+
+Checking unconnected pins...
+ERROR: Unconnected pin U100:2
+
+Checking slots...
+
+Checking duplicated slots...
+
+Checking unused slots...
+WARNING: Unused slot 4 of uref U100
+
+Found 1 warnings.
+Found 4 errors.
diff --git a/gnetlist/tests/common/outputs/drc2/singlenet.retcode b/gnetlist/tests/common/outputs/drc2/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/drc2/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/.gitignore b/gnetlist/tests/common/outputs/eagle/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/eagle/JD-output.net b/gnetlist/tests/common/outputs/eagle/JD-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/JD.retcode b/gnetlist/tests/common/outputs/eagle/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include-output.net b/gnetlist/tests/common/outputs/eagle/JD_Include-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include.retcode b/gnetlist/tests/common/outputs/eagle/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net b/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort.retcode b/gnetlist/tests/common/outputs/eagle/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net b/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net
new file mode 100644
index 0000000..df919e4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/JD_nomunge-output.net
@@ -0,0 +1,62 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'pulse 3.3 0 1u 10p 10p 1.25u 2.5u';
+ADD 'Cm' unknown@smd-ipc (1 1);
+VALUE 'Cm' '20p';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'Rt' unknown@smd-ipc (1 1);
+VALUE 'Rt' '1k';
+ADD 'M1' unknown@smd-ipc (1 1);
+VALUE 'M1' 'PMOS_TRANSISTOR';
+ADD 'X1' unknown@smd-ipc (1 1);
+VALUE 'X1' 'LVD';
+ADD 'Rlp' unknown@smd-ipc (1 1);
+VALUE 'Rlp' '1meg';
+ADD 'Vdd' none@smd-ipc (1 1);
+VALUE 'Vdd' 'DC 3.3V';
+ADD 'Rlm' unknown@smd-ipc (1 1);
+VALUE 'Rlm' '500k';
+ADD 'Cp' unknown@smd-ipc (1 1);
+VALUE 'Cp' '20p';
+ADD 'Rb' unknown@smd-ipc (1 1);
+VALUE 'Rb' '5.6k';
+SIGNAL 'VDD1'
+   'Rlp' '2'
+   'M1' 'B'
+   'M1' 'S'
+   'Vdd' '1'
+   'X1' '6'
+;
+SIGNAL 'GND'
+   'Cm' '2'
+   'Cp' '2'
+   'Rlm' '2'
+   'Vdd' '2'
+   'V1' '2'
+   'Rb' '1'
+   'X1' '7'
+   'X1' '2'
+;
+SIGNAL 'LVH'
+   'Rb' '2'
+   'M1' 'D'
+   'M1' 'G'
+   'X1' '3'
+;
+SIGNAL 'I'
+   'V1' '1'
+   'X1' '1'
+;
+SIGNAL 'P'
+   'Cp' '1'
+   'Rt' '1'
+   'Rlp' '1'
+   'X1' '5'
+;
+SIGNAL 'M'
+   'Cm' '1'
+   'Rlm' '1'
+   'Rt' '2'
+   'X1' '4'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/Makefile.am b/gnetlist/tests/common/outputs/eagle/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/eagle/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/eagle/SlottedOpamps-output.net
new file mode 100644
index 0000000..ad5f3e3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/SlottedOpamps-output.net
@@ -0,0 +1,33 @@
+   ;
+ADD 'U1' unknown@smd-ipc (1 1);
+VALUE 'U1' 'LM324';
+SIGNAL 'MINUSIN_SLOT4_PIN13_B'
+   'U1' '13'
+;
+SIGNAL 'PLUSIN_SLOT4_PIN12_A'
+   'U1' '12'
+;
+SIGNAL 'MINUSIN_SLOT3_PIN_B'
+   'U1' '9'
+;
+SIGNAL 'PLUSIN_SLOT3_PIN10_A'
+   'U1' '10'
+;
+SIGNAL 'MINUSIN_SLOT2_PIN6_B'
+   'U1' '6'
+;
+SIGNAL 'PLUSIN_SLOT2_PIN5_A'
+   'U1' '5'
+;
+SIGNAL 'SAMENET_OUTPUT_C'
+   'U1' '14'
+   'U1' '8'
+   'U1' '7'
+   'U1' '1'
+;
+SIGNAL 'MINUSIN_SLOT1_PIN_B'
+   'U1' '2'
+;
+SIGNAL 'PLUSIN_SLOT1_PIN3_A'
+   'U1' '3'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/eagle/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net
new file mode 100644
index 0000000..e4a8277
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp-output.net
@@ -0,0 +1,113 @@
+   ;
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'R4' unknown@smd-ipc (1 1);
+VALUE 'R4' '2.8K';
+ADD 'RE2' unknown@smd-ipc (1 1);
+VALUE 'RE2' '100';
+ADD 'Q2' unknown@smd-ipc (1 1);
+VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'A3' unknown@smd-ipc (1 1);
+VALUE 'A3' '.options TEMP=25';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'A2' unknown@smd-ipc (1 1);
+VALUE 'A2' 'include';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'Vinput' none@smd-ipc (1 1);
+VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
+ADD 'CE1' unknown@smd-ipc (1 1);
+VALUE 'CE1' '1pF';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
+ADD 'RL' unknown@smd-ipc (1 1);
+VALUE 'RL' '100K';
+SIGNAL 'UNNAMED_NET2'
+   'C2' '1'
+   'R8' '2'
+;
+SIGNAL 'VBASE2'
+   'R3' '1'
+   'C2' '2'
+   'R4' '2'
+   'Q2' '2'
+;
+SIGNAL 'VEM2'
+   'CE2' '2'
+   'RE2' '2'
+   'Q2' '1'
+;
+SIGNAL 'VOUT'
+   'Cout' '2'
+   'RL' '2'
+;
+SIGNAL 'VCOLL2'
+   'Q2' '3'
+   'Cout' '1'
+   'RC2' '1'
+;
+SIGNAL 'GND'
+   'R4' '1'
+   'CE2' '1'
+   'RE2' '1'
+   'VCC' '2'
+   'Vinput' '2'
+   'CE1' '1'
+   'RL' '1'
+   'RE1' '1'
+   'R2' '1'
+;
+SIGNAL 'VCC'
+   'R3' '2'
+   'RC1' '2'
+   'VCC' '1'
+   'RC2' '2'
+   'R1' '2'
+;
+SIGNAL 'VIN'
+   'Vinput' '1'
+   'R5' '1'
+;
+SIGNAL 'UNNAMED_NET1'
+   'C1' '1'
+   'R5' '2'
+;
+SIGNAL 'VBASE1'
+   'C1' '2'
+   'R2' '2'
+   'R1' '1'
+   'Q1' '2'
+;
+SIGNAL 'VEM1'
+   'CE1' '2'
+   'RE1' '2'
+   'Q1' '1'
+;
+SIGNAL 'VCOLL1'
+   'R8' '1'
+   'RC1' '1'
+   'Q1' '3'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/eagle/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..e4a8277
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include-output.net
@@ -0,0 +1,113 @@
+   ;
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'R4' unknown@smd-ipc (1 1);
+VALUE 'R4' '2.8K';
+ADD 'RE2' unknown@smd-ipc (1 1);
+VALUE 'RE2' '100';
+ADD 'Q2' unknown@smd-ipc (1 1);
+VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'A3' unknown@smd-ipc (1 1);
+VALUE 'A3' '.options TEMP=25';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'A2' unknown@smd-ipc (1 1);
+VALUE 'A2' 'include';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'Vinput' none@smd-ipc (1 1);
+VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
+ADD 'CE1' unknown@smd-ipc (1 1);
+VALUE 'CE1' '1pF';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
+ADD 'RL' unknown@smd-ipc (1 1);
+VALUE 'RL' '100K';
+SIGNAL 'UNNAMED_NET2'
+   'C2' '1'
+   'R8' '2'
+;
+SIGNAL 'VBASE2'
+   'R3' '1'
+   'C2' '2'
+   'R4' '2'
+   'Q2' '2'
+;
+SIGNAL 'VEM2'
+   'CE2' '2'
+   'RE2' '2'
+   'Q2' '1'
+;
+SIGNAL 'VOUT'
+   'Cout' '2'
+   'RL' '2'
+;
+SIGNAL 'VCOLL2'
+   'Q2' '3'
+   'Cout' '1'
+   'RC2' '1'
+;
+SIGNAL 'GND'
+   'R4' '1'
+   'CE2' '1'
+   'RE2' '1'
+   'VCC' '2'
+   'Vinput' '2'
+   'CE1' '1'
+   'RL' '1'
+   'RE1' '1'
+   'R2' '1'
+;
+SIGNAL 'VCC'
+   'R3' '2'
+   'RC1' '2'
+   'VCC' '1'
+   'RC2' '2'
+   'R1' '2'
+;
+SIGNAL 'VIN'
+   'Vinput' '1'
+   'R5' '1'
+;
+SIGNAL 'UNNAMED_NET1'
+   'C1' '1'
+   'R5' '2'
+;
+SIGNAL 'VBASE1'
+   'C1' '2'
+   'R2' '2'
+   'R1' '1'
+   'Q1' '2'
+;
+SIGNAL 'VEM1'
+   'CE1' '2'
+   'RE1' '2'
+   'Q1' '1'
+;
+SIGNAL 'VCOLL1'
+   'R8' '1'
+   'RC1' '1'
+   'Q1' '3'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..e4a8277
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort-output.net
@@ -0,0 +1,113 @@
+   ;
+ADD 'Cout' unknown@smd-ipc (1 1);
+VALUE 'Cout' '2.2uF';
+ADD 'R5' unknown@smd-ipc (1 1);
+VALUE 'R5' '10';
+ADD 'R4' unknown@smd-ipc (1 1);
+VALUE 'R4' '2.8K';
+ADD 'RE2' unknown@smd-ipc (1 1);
+VALUE 'RE2' '100';
+ADD 'Q2' unknown@smd-ipc (1 1);
+VALUE 'Q2' 'NPN_TRANSISTOR';
+ADD 'A3' unknown@smd-ipc (1 1);
+VALUE 'A3' '.options TEMP=25';
+ADD 'R3' unknown@smd-ipc (1 1);
+VALUE 'R3' '28K';
+ADD 'A2' unknown@smd-ipc (1 1);
+VALUE 'A2' 'include';
+ADD 'RE1' unknown@smd-ipc (1 1);
+VALUE 'RE1' '100';
+ADD 'Q1' unknown@smd-ipc (1 1);
+VALUE 'Q1' 'NPN_TRANSISTOR';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'model';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '2K';
+ADD 'Vinput' none@smd-ipc (1 1);
+VALUE 'Vinput' 'DC 1.6V AC 10MV SIN(0 1MV 1KHZ)';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '28K';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '2.2uF';
+ADD 'CE2' unknown@smd-ipc (1 1);
+VALUE 'CE2' '1pF';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2.2uF';
+ADD 'CE1' unknown@smd-ipc (1 1);
+VALUE 'CE1' '1pF';
+ADD 'R8' unknown@smd-ipc (1 1);
+VALUE 'R8' '1';
+ADD 'VCC' none@smd-ipc (1 1);
+VALUE 'VCC' 'DC 15V';
+ADD 'RC2' unknown@smd-ipc (1 1);
+VALUE 'RC2' '1K';
+ADD 'RC1' unknown@smd-ipc (1 1);
+VALUE 'RC1' '3.3K';
+ADD 'RL' unknown@smd-ipc (1 1);
+VALUE 'RL' '100K';
+SIGNAL 'UNNAMED_NET2'
+   'C2' '1'
+   'R8' '2'
+;
+SIGNAL 'VBASE2'
+   'R3' '1'
+   'C2' '2'
+   'R4' '2'
+   'Q2' '2'
+;
+SIGNAL 'VEM2'
+   'CE2' '2'
+   'RE2' '2'
+   'Q2' '1'
+;
+SIGNAL 'VOUT'
+   'Cout' '2'
+   'RL' '2'
+;
+SIGNAL 'VCOLL2'
+   'Q2' '3'
+   'Cout' '1'
+   'RC2' '1'
+;
+SIGNAL 'GND'
+   'R4' '1'
+   'CE2' '1'
+   'RE2' '1'
+   'VCC' '2'
+   'Vinput' '2'
+   'CE1' '1'
+   'RL' '1'
+   'RE1' '1'
+   'R2' '1'
+;
+SIGNAL 'VCC'
+   'R3' '2'
+   'RC1' '2'
+   'VCC' '1'
+   'RC2' '2'
+   'R1' '2'
+;
+SIGNAL 'VIN'
+   'Vinput' '1'
+   'R5' '1'
+;
+SIGNAL 'UNNAMED_NET1'
+   'C1' '1'
+   'R5' '2'
+;
+SIGNAL 'VBASE1'
+   'C1' '2'
+   'R2' '2'
+   'R1' '1'
+   'Q1' '2'
+;
+SIGNAL 'VEM1'
+   'CE1' '2'
+   'RE1' '2'
+   'Q1' '1'
+;
+SIGNAL 'VCOLL1'
+   'R8' '1'
+   'RC1' '1'
+   'Q1' '3'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/cascade-output.net b/gnetlist/tests/common/outputs/eagle/cascade-output.net
new file mode 100644
index 0000000..e94f679
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/cascade-output.net
@@ -0,0 +1,44 @@
+   ;
+ADD 'AMP2' none@smd-ipc (1 1);
+VALUE 'AMP2' 'cascade-amp';
+ADD 'AMP1' none@smd-ipc (1 1);
+VALUE 'AMP1' 'cascade-amp';
+ADD 'SOURCE' none@smd-ipc (1 1);
+VALUE 'SOURCE' 'cascade-source';
+ADD 'DEFAULTS' unknown@smd-ipc (1 1);
+VALUE 'DEFAULTS' 'cascade-defaults-top';
+ADD 'MX1' none@smd-ipc (1 1);
+VALUE 'MX1' 'cascade-mixer';
+ADD 'DEF1' none@smd-ipc (1 1);
+VALUE 'DEF1' 'cascade-defaults';
+ADD 'T1' none@smd-ipc (1 1);
+VALUE 'T1' 'cascade-transformer';
+ADD 'FL1' none@smd-ipc (1 1);
+VALUE 'FL1' 'cascade-filter';
+SIGNAL 'UNNAMED_NET6'
+   'AMP2' '1'
+   'T1' '2'
+;
+SIGNAL 'UNNAMED_NET5'
+   'T1' '1'
+   'MX1' '2'
+;
+SIGNAL 'UNNAMED_NET4'
+   'MX1' '1'
+   'FL1' '2'
+;
+SIGNAL 'UNNAMED_NET3'
+   'FL1' '1'
+   'DEF1' '2'
+;
+SIGNAL 'UNNAMED_NET2'
+   'DEF1' '1'
+   'AMP1' '2'
+;
+SIGNAL 'UNNAMED_NET1'
+   'AMP1' '1'
+   'SOURCE' '1'
+;
+SIGNAL 'GND'
+   'DEFAULTS' '1'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/cascade.retcode b/gnetlist/tests/common/outputs/eagle/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/multiequal-output.net b/gnetlist/tests/common/outputs/eagle/multiequal-output.net
new file mode 100644
index 0000000..978d0da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/multiequal-output.net
@@ -0,0 +1,15 @@
+   ;
+ADD 'V1' none@smd-ipc (1 1);
+VALUE 'V1' 'DC 1V';
+ADD 'A1' unknown@smd-ipc (1 1);
+VALUE 'A1' 'abotol=1e-11';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '20';
+SIGNAL 'GND'
+   'V1' '2'
+   'R1' '1'
+;
+SIGNAL 'UNNAMED_NET1'
+   'V1' '1'
+   'R1' '2'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/multiequal.retcode b/gnetlist/tests/common/outputs/eagle/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/netattrib-output.net b/gnetlist/tests/common/outputs/eagle/netattrib-output.net
new file mode 100644
index 0000000..4ab78c3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/netattrib-output.net
@@ -0,0 +1,32 @@
+   ;
+ADD 'F1' unknown@smd-ipc (1 1);
+VALUE 'F1' 'FUSE';
+ADD 'U100' DIP14@smd-ipc (1 1);
+VALUE 'U100' '7400';
+ADD 'U300' DIP14@smd-ipc (1 1);
+VALUE 'U300' '7404';
+ADD 'U200' DIP14@smd-ipc (1 1);
+VALUE 'U200' '7404';
+SIGNAL 'UNNAMED_NET1'
+   'U300' '2'
+;
+SIGNAL 'NETATTRIB'
+   'U200' '2'
+   'U100' '5'
+;
+SIGNAL 'GND'
+   'U300' '7'
+   'U200' '7'
+   'U100' '7'
+;
+SIGNAL 'VCC'
+   'U300' '14'
+   'U200' '14'
+   'U100' '14'
+;
+SIGNAL 'ONE'
+   'F1' '1'
+   'U300' '1'
+   'U200' '1'
+   'U100' '3'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/netattrib.retcode b/gnetlist/tests/common/outputs/eagle/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/powersupply-output.net b/gnetlist/tests/common/outputs/eagle/powersupply-output.net
new file mode 100644
index 0000000..16e8ae8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/powersupply-output.net
@@ -0,0 +1,78 @@
+   ;
+ADD 'F1' unknown@smd-ipc (1 1);
+VALUE 'F1' 'FUSE';
+ADD 'R2' unknown@smd-ipc (1 1);
+VALUE 'R2' '220';
+ADD 'CONN1' unknown@smd-ipc (1 1);
+VALUE 'CONN1' 'MAINS_CONNECTOR';
+ADD 'C4' unknown@smd-ipc (1 1);
+VALUE 'C4' '1uf';
+ADD 'R1' unknown@smd-ipc (1 1);
+VALUE 'R1' '5k';
+ADD 'C3' unknown@smd-ipc (1 1);
+VALUE 'C3' '22uF';
+ADD 'C2' unknown@smd-ipc (1 1);
+VALUE 'C2' '0.1uF';
+ADD 'S1' unknown@smd-ipc (1 1);
+VALUE 'S1' 'SPST';
+ADD 'C1' unknown@smd-ipc (1 1);
+VALUE 'C1' '2200uF';
+ADD 'T1' unknown@smd-ipc (1 1);
+VALUE 'T1' 'transformer';
+ADD 'U2' unknown@smd-ipc (1 1);
+VALUE 'U2' 'LM317';
+ADD 'U1' unknown@smd-ipc (1 1);
+VALUE 'U1' 'DIODE-BRIDGE';
+SIGNAL 'TEN'
+   'U2' '1'
+   'R1' '2'
+   'C3' '1'
+   'R2' '1'
+;
+SIGNAL 'ELEVEN'
+   'U2' '2'
+   'C4' '1'
+   'R2' '2'
+;
+SIGNAL 'GND'
+   'CONN1' '3'
+;
+SIGNAL 'ONE'
+   'S1' '1'
+   'CONN1' '1'
+;
+SIGNAL 'FIVE'
+   'CONN1' '2'
+   'T1' '2'
+;
+SIGNAL 'THREE'
+   'T1' '1'
+   'F1' '2'
+;
+SIGNAL 'TWO'
+   'S1' '2'
+   'F1' '1'
+;
+SIGNAL 'SIX'
+   'T1' '3'
+   'U1' '4'
+;
+SIGNAL 'SEVEN'
+   'T1' '4'
+   'U1' '3'
+;
+SIGNAL 'NINE'
+   'C4' '2'
+   'C3' '2'
+   'R1' '3'
+   'R1' '1'
+   'C2' '2'
+   'C1' '2'
+   'U1' '2'
+;
+SIGNAL 'EIGHT'
+   'U2' '3'
+   'C2' '1'
+   'C1' '1'
+   'U1' '1'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/powersupply.retcode b/gnetlist/tests/common/outputs/eagle/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/eagle/singlenet-output.net b/gnetlist/tests/common/outputs/eagle/singlenet-output.net
new file mode 100644
index 0000000..8755cd5
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/singlenet-output.net
@@ -0,0 +1,21 @@
+   ;
+ADD 'U100' DIP14@smd-ipc (1 1);
+VALUE 'U100' '7400';
+SIGNAL 'SING_N_2'
+   'U100' '1'
+   'U100' '3'
+;
+SIGNAL 'GND'
+   'U100' '7'
+;
+SIGNAL 'VCC'
+   'U100' '14'
+;
+SIGNAL 'SING_N'
+   'U100' '4'
+   'U100' '5'
+   'U100' '10'
+   'U100' '8'
+   'U100' '9'
+   'U100' '6'
+;
diff --git a/gnetlist/tests/common/outputs/eagle/singlenet.retcode b/gnetlist/tests/common/outputs/eagle/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/eagle/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/.gitignore b/gnetlist/tests/common/outputs/futurenet2/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD-output.net b/gnetlist/tests/common/outputs/futurenet2/JD-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD.retcode b/gnetlist/tests/common/outputs/futurenet2/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include.retcode b/gnetlist/tests/common/outputs/futurenet2/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort.retcode b/gnetlist/tests/common/outputs/futurenet2/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net
new file mode 100644
index 0000000..10530f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/JD_nomunge-output.net
@@ -0,0 +1,92 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,I,1-1,5,23,1
+)
+(SYM,2
+DATA,2,CM
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,M,1-1,5,23,1
+)
+(SYM,3
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,4
+DATA,2,RT
+DATA,3,1k
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,M,1-1,5,23,2
+)
+(SYM,5
+DATA,2,M1
+DATA,3,PMOS_TRANSISTOR
+DATA,4,unknown
+PIN,,LVH,1-1,5,23,G
+PIN,,LVH,1-1,5,23,D
+PIN,,VDD1,1-1,5,23,B
+PIN,,VDD1,1-1,5,23,S
+)
+(SYM,6
+DATA,2,X1
+DATA,3,LVD
+DATA,4,unknown
+PIN,,GND,1-1,5,23,7
+PIN,,VDD1,1-1,5,23,6
+PIN,,GND,1-1,5,23,2
+PIN,,LVH,1-1,5,23,3
+PIN,,I,1-1,5,23,1
+PIN,,P,1-1,5,23,5
+PIN,,M,1-1,5,23,4
+)
+(SYM,7
+DATA,2,RLP
+DATA,3,1meg
+DATA,4,unknown
+PIN,,P,1-1,5,23,1
+PIN,,VDD1,1-1,5,23,2
+)
+(SYM,8
+DATA,2,VDD
+DATA,3,DC 3.3V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VDD1,1-1,5,23,1
+)
+(SYM,9
+DATA,2,RLM
+DATA,3,500k
+DATA,4,unknown
+PIN,,M,1-1,5,23,1
+PIN,,GND,1-1,5,23,2
+)
+(SYM,10
+DATA,2,CP
+DATA,3,20p
+DATA,4,unknown
+PIN,,GND,1-1,5,23,2
+PIN,,P,1-1,5,23,1
+)
+(SYM,11
+DATA,2,RB
+DATA,3,5.6k
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,LVH,1-1,5,23,2
+)
+)
+SIG,VDD1,1-1,5,VDD1
+SIG,GND,1-1,5,GND
+SIG,LVH,1-1,5,LVH
+SIG,I,1-1,5,I
+SIG,P,1-1,5,P
+SIG,M,1-1,5,M
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/Makefile.am b/gnetlist/tests/common/outputs/futurenet2/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/futurenet2/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/futurenet2/SlottedOpamps-output.net
new file mode 100644
index 0000000..e69de29
diff --git a/gnetlist/tests/common/outputs/futurenet2/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/futurenet2/SlottedOpamps.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/SlottedOpamps.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net
new file mode 100644
index 0000000..8ed0786
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp-output.net
@@ -0,0 +1,173 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,COUT
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
+)
+(SYM,2
+DATA,2,R5
+DATA,3,10
+DATA,4,unknown
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
+)
+(SYM,3
+DATA,2,R4
+DATA,3,2.8K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+)
+(SYM,4
+DATA,2,RE2
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
+)
+(SYM,5
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
+)
+(SYM,6
+DATA,2,A3
+DATA,3,.options TEMP=25
+DATA,4,unknown
+)
+(SYM,7
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,8
+DATA,2,A2
+DATA,3,include
+DATA,4,unknown
+)
+(SYM,9
+DATA,2,RE1
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+)
+(SYM,10
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
+)
+(SYM,11
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,12
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
+)
+(SYM,13
+DATA,2,VINPUT
+DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+)
+(SYM,14
+DATA,2,R1
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,15
+DATA,2,C2
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
+)
+(SYM,16
+DATA,2,CE2
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,17
+DATA,2,C1
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,18
+DATA,2,CE1
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,19
+DATA,2,R8
+DATA,3,1
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
+)
+(SYM,20
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,21
+DATA,2,RC2
+DATA,3,1K
+DATA,4,unknown
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,22
+DATA,2,RC1
+DATA,3,3.3K
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,23
+DATA,2,RL
+DATA,3,100K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+)
+)
+SIG,NET2,1-1,5,NET2
+SIG,VBASE2,1-1,5,VBASE2
+SIG,VEM2,1-1,5,VEM2
+SIG,VOUT,1-1,5,VOUT
+SIG,VCOLL2,1-1,5,VCOLL2
+SIG,GND,1-1,5,GND
+SIG,VCC,1-1,5,VCC
+SIG,VIN,1-1,5,VIN
+SIG,NET1,1-1,5,NET1
+SIG,VBASE1,1-1,5,VBASE1
+SIG,VEM1,1-1,5,VEM1
+SIG,VCOLL1,1-1,5,VCOLL1
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..8ed0786
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include-output.net
@@ -0,0 +1,173 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,COUT
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
+)
+(SYM,2
+DATA,2,R5
+DATA,3,10
+DATA,4,unknown
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
+)
+(SYM,3
+DATA,2,R4
+DATA,3,2.8K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+)
+(SYM,4
+DATA,2,RE2
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
+)
+(SYM,5
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
+)
+(SYM,6
+DATA,2,A3
+DATA,3,.options TEMP=25
+DATA,4,unknown
+)
+(SYM,7
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,8
+DATA,2,A2
+DATA,3,include
+DATA,4,unknown
+)
+(SYM,9
+DATA,2,RE1
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+)
+(SYM,10
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
+)
+(SYM,11
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,12
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
+)
+(SYM,13
+DATA,2,VINPUT
+DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+)
+(SYM,14
+DATA,2,R1
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,15
+DATA,2,C2
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
+)
+(SYM,16
+DATA,2,CE2
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,17
+DATA,2,C1
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,18
+DATA,2,CE1
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,19
+DATA,2,R8
+DATA,3,1
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
+)
+(SYM,20
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,21
+DATA,2,RC2
+DATA,3,1K
+DATA,4,unknown
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,22
+DATA,2,RC1
+DATA,3,3.3K
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,23
+DATA,2,RL
+DATA,3,100K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+)
+)
+SIG,NET2,1-1,5,NET2
+SIG,VBASE2,1-1,5,VBASE2
+SIG,VEM2,1-1,5,VEM2
+SIG,VOUT,1-1,5,VOUT
+SIG,VCOLL2,1-1,5,VCOLL2
+SIG,GND,1-1,5,GND
+SIG,VCC,1-1,5,VCC
+SIG,VIN,1-1,5,VIN
+SIG,NET1,1-1,5,NET1
+SIG,VBASE1,1-1,5,VBASE1
+SIG,VEM1,1-1,5,VEM1
+SIG,VCOLL1,1-1,5,VCOLL1
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..8ed0786
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort-output.net
@@ -0,0 +1,173 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,COUT
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VOUT,1-1,5,23,2
+PIN,,VCOLL2,1-1,5,23,1
+)
+(SYM,2
+DATA,2,R5
+DATA,3,10
+DATA,4,unknown
+PIN,,VIN,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
+)
+(SYM,3
+DATA,2,R4
+DATA,3,2.8K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE2,1-1,5,23,2
+)
+(SYM,4
+DATA,2,RE2
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM2,1-1,5,23,2
+)
+(SYM,5
+DATA,2,Q2
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,VEM2,1-1,5,23,1
+PIN,,VCOLL2,1-1,5,23,3
+)
+(SYM,6
+DATA,2,A3
+DATA,3,.options TEMP=25
+DATA,4,unknown
+)
+(SYM,7
+DATA,2,R3
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,8
+DATA,2,A2
+DATA,3,include
+DATA,4,unknown
+)
+(SYM,9
+DATA,2,RE1
+DATA,3,100
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VEM1,1-1,5,23,2
+)
+(SYM,10
+DATA,2,Q1
+DATA,3,NPN_TRANSISTOR
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,VEM1,1-1,5,23,1
+PIN,,VCOLL1,1-1,5,23,3
+)
+(SYM,11
+DATA,2,A1
+DATA,3,model
+DATA,4,unknown
+)
+(SYM,12
+DATA,2,R2
+DATA,3,2K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VBASE1,1-1,5,23,2
+)
+(SYM,13
+DATA,2,VINPUT
+DATA,3,DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VIN,1-1,5,23,1
+)
+(SYM,14
+DATA,2,R1
+DATA,3,28K
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,15
+DATA,2,C2
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE2,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
+)
+(SYM,16
+DATA,2,CE2
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM2,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,17
+DATA,2,C1
+DATA,3,2.2uF
+DATA,4,unknown
+PIN,,VBASE1,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,18
+DATA,2,CE1
+DATA,3,1pF
+DATA,4,unknown
+PIN,,VEM1,1-1,5,23,2
+PIN,,GND,1-1,5,23,1
+)
+(SYM,19
+DATA,2,R8
+DATA,3,1
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,NET2,1-1,5,23,2
+)
+(SYM,20
+DATA,2,VCC
+DATA,3,DC 15V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,VCC,1-1,5,23,1
+)
+(SYM,21
+DATA,2,RC2
+DATA,3,1K
+DATA,4,unknown
+PIN,,VCOLL2,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,22
+DATA,2,RC1
+DATA,3,3.3K
+DATA,4,unknown
+PIN,,VCOLL1,1-1,5,23,1
+PIN,,VCC,1-1,5,23,2
+)
+(SYM,23
+DATA,2,RL
+DATA,3,100K
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,VOUT,1-1,5,23,2
+)
+)
+SIG,NET2,1-1,5,NET2
+SIG,VBASE2,1-1,5,VBASE2
+SIG,VEM2,1-1,5,VEM2
+SIG,VOUT,1-1,5,VOUT
+SIG,VCOLL2,1-1,5,VCOLL2
+SIG,GND,1-1,5,GND
+SIG,VCC,1-1,5,VCC
+SIG,VIN,1-1,5,VIN
+SIG,NET1,1-1,5,NET1
+SIG,VBASE1,1-1,5,VBASE1
+SIG,VEM1,1-1,5,VEM1
+SIG,VCOLL1,1-1,5,VCOLL1
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/cascade-output.net b/gnetlist/tests/common/outputs/futurenet2/cascade-output.net
new file mode 100644
index 0000000..0dac53a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/cascade-output.net
@@ -0,0 +1,65 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,AMP2
+DATA,3,cascade-amp
+DATA,4,none
+PIN,,#f,1-1,5,23,2
+PIN,,NET6,1-1,5,23,1
+)
+(SYM,2
+DATA,2,AMP1
+DATA,3,cascade-amp
+DATA,4,none
+PIN,,NET2,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,3
+DATA,2,SOURCE
+DATA,3,cascade-source
+DATA,4,none
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,4
+DATA,2,DEFAULTS
+DATA,3,cascade-defaults-top
+DATA,4,unknown
+PIN,,GND,1-1,5,23,unknown
+)
+(SYM,5
+DATA,2,MX1
+DATA,3,cascade-mixer
+DATA,4,none
+PIN,,NET5,1-1,5,23,2
+PIN,,NET4,1-1,5,23,1
+)
+(SYM,6
+DATA,2,DEF1
+DATA,3,cascade-defaults
+DATA,4,none
+PIN,,NET3,1-1,5,23,2
+PIN,,NET2,1-1,5,23,1
+)
+(SYM,7
+DATA,2,T1
+DATA,3,cascade-transformer
+DATA,4,none
+PIN,,NET6,1-1,5,23,2
+PIN,,NET5,1-1,5,23,1
+)
+(SYM,8
+DATA,2,FL1
+DATA,3,cascade-filter
+DATA,4,none
+PIN,,NET4,1-1,5,23,2
+PIN,,NET3,1-1,5,23,1
+)
+)
+SIG,NET6,1-1,5,NET6
+SIG,NET5,1-1,5,NET5
+SIG,NET4,1-1,5,NET4
+SIG,NET3,1-1,5,NET3
+SIG,NET2,1-1,5,NET2
+SIG,NET1,1-1,5,NET1
+SIG,GND,1-1,5,GND
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/cascade.retcode b/gnetlist/tests/common/outputs/futurenet2/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net b/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net
new file mode 100644
index 0000000..6f5b71a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/multiequal-output.net
@@ -0,0 +1,25 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,V1
+DATA,3,DC 1V
+DATA,4,none
+PIN,,GND,1-1,5,23,2
+PIN,,NET1,1-1,5,23,1
+)
+(SYM,2
+DATA,2,A1
+DATA,3,abotol=1e-11
+DATA,4,unknown
+)
+(SYM,3
+DATA,2,R1
+DATA,3,20
+DATA,4,unknown
+PIN,,GND,1-1,5,23,1
+PIN,,NET1,1-1,5,23,2
+)
+)
+SIG,GND,1-1,5,GND
+SIG,NET1,1-1,5,NET1
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/multiequal.retcode b/gnetlist/tests/common/outputs/futurenet2/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net b/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net
new file mode 100644
index 0000000..1cf6d8d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/netattrib-output.net
@@ -0,0 +1,45 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,F1
+DATA,3,FUSE
+DATA,4,unknown
+PIN,,#f,1-1,5,23,2
+PIN,,ONE,1-1,5,23,1
+)
+(SYM,2
+DATA,2,U100
+DATA,3,7400
+DATA,4,DIP14
+PIN,,NETATTRI,1-1,5,23,unknown
+PIN,,GND,1-1,5,23,unknown
+PIN,,VCC,1-1,5,23,unknown
+PIN,,#f,1-1,5,23,1
+PIN,,#f,1-1,5,23,2
+PIN,,ONE,1-1,5,23,3
+)
+(SYM,3
+DATA,2,U300
+DATA,3,7404
+DATA,4,DIP14
+PIN,,VCC,1-1,5,23,unknown
+PIN,,GND,1-1,5,23,unknown
+PIN,,NET1,1-1,5,23,2
+PIN,,ONE,1-1,5,23,1
+)
+(SYM,4
+DATA,2,U200
+DATA,3,7404
+DATA,4,DIP14
+PIN,,VCC,1-1,5,23,unknown
+PIN,,GND,1-1,5,23,unknown
+PIN,,NETATTRI,1-1,5,23,2
+PIN,,ONE,1-1,5,23,1
+)
+)
+SIG,NET1,1-1,5,NET1
+SIG,NETATTRI,1-1,5,NETATTRI
+SIG,GND,1-1,5,GND
+SIG,VCC,1-1,5,VCC
+SIG,ONE,1-1,5,ONE
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/netattrib.retcode b/gnetlist/tests/common/outputs/futurenet2/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net b/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net
new file mode 100644
index 0000000..d63b98c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/powersupply-output.net
@@ -0,0 +1,106 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,F1
+DATA,3,FUSE
+DATA,4,unknown
+PIN,,THREE,1-1,5,23,2
+PIN,,TWO,1-1,5,23,1
+)
+(SYM,2
+DATA,2,R2
+DATA,3,220
+DATA,4,unknown
+PIN,,TEN,1-1,5,23,1
+PIN,,ELEVEN,1-1,5,23,2
+)
+(SYM,3
+DATA,2,CONN1
+DATA,3,MAINS_CONNECTOR
+DATA,4,unknown
+PIN,,GND,1-1,5,23,3
+PIN,,FIVE,1-1,5,23,2
+PIN,,ONE,1-1,5,23,1
+)
+(SYM,4
+DATA,2,C4
+DATA,3,1uf
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,2
+PIN,,ELEVEN,1-1,5,23,1
+)
+(SYM,5
+DATA,2,R1
+DATA,3,5k
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,1
+PIN,,TEN,1-1,5,23,2
+PIN,,NINE,1-1,5,23,3
+)
+(SYM,6
+DATA,2,C3
+DATA,3,22uF
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,2
+PIN,,TEN,1-1,5,23,1
+)
+(SYM,7
+DATA,2,C2
+DATA,3,0.1uF
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,2
+PIN,,EIGHT,1-1,5,23,1
+)
+(SYM,8
+DATA,2,S1
+DATA,3,SPST
+DATA,4,unknown
+PIN,,ONE,1-1,5,23,1
+PIN,,TWO,1-1,5,23,2
+)
+(SYM,9
+DATA,2,C1
+DATA,3,2200uF
+DATA,4,unknown
+PIN,,NINE,1-1,5,23,2
+PIN,,EIGHT,1-1,5,23,1
+)
+(SYM,10
+DATA,2,T1
+DATA,3,transformer
+DATA,4,unknown
+PIN,,SIX,1-1,5,23,3
+PIN,,SEVEN,1-1,5,23,4
+PIN,,THREE,1-1,5,23,1
+PIN,,FIVE,1-1,5,23,2
+)
+(SYM,11
+DATA,2,U2
+DATA,3,LM317
+DATA,4,unknown
+PIN,,TEN,1-1,5,23,1
+PIN,,EIGHT,1-1,5,23,3
+PIN,,ELEVEN,1-1,5,23,2
+)
+(SYM,12
+DATA,2,U1
+DATA,3,DIODE-BRIDGE
+DATA,4,unknown
+PIN,,SIX,1-1,5,23,4
+PIN,,SEVEN,1-1,5,23,3
+PIN,,NINE,1-1,5,23,2
+PIN,,EIGHT,1-1,5,23,1
+)
+)
+SIG,TEN,1-1,5,TEN
+SIG,ELEVEN,1-1,5,ELEVEN
+SIG,GND,1-1,5,GND
+SIG,ONE,1-1,5,ONE
+SIG,FIVE,1-1,5,FIVE
+SIG,THREE,1-1,5,THREE
+SIG,TWO,1-1,5,TWO
+SIG,SIX,1-1,5,SIX
+SIG,SEVEN,1-1,5,SEVEN
+SIG,NINE,1-1,5,NINE
+SIG,EIGHT,1-1,5,EIGHT
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/powersupply.retcode b/gnetlist/tests/common/outputs/futurenet2/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/futurenet2/singlenet-output.net b/gnetlist/tests/common/outputs/futurenet2/singlenet-output.net
new file mode 100644
index 0000000..fcb2812
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/singlenet-output.net
@@ -0,0 +1,28 @@
+PINLIST,2
+(DRAWING,GEDA.PIN,1-1
+(SYM,1
+DATA,2,U100
+DATA,3,7400
+DATA,4,DIP14
+PIN,,GND,1-1,5,23,unknown
+PIN,,VCC,1-1,5,23,unknown
+PIN,,SING_N,1-1,5,23,9
+PIN,,SING_N,1-1,5,23,10
+PIN,,SING_N,1-1,5,23,8
+PIN,,GND,1-1,5,23,unknown
+PIN,,VCC,1-1,5,23,unknown
+PIN,,SING_N_2,1-1,5,23,1
+PIN,,#f,1-1,5,23,2
+PIN,,SING_N_2,1-1,5,23,3
+PIN,,GND,1-1,5,23,unknown
+PIN,,VCC,1-1,5,23,unknown
+PIN,,SING_N,1-1,5,23,4
+PIN,,SING_N,1-1,5,23,5
+PIN,,SING_N,1-1,5,23,6
+)
+)
+SIG,SING_N_2,1-1,5,SING_N_2
+SIG,GND,1-1,5,GND
+SIG,VCC,1-1,5,VCC
+SIG,SING_N,1-1,5,SING_N
+)
diff --git a/gnetlist/tests/common/outputs/futurenet2/singlenet.retcode b/gnetlist/tests/common/outputs/futurenet2/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/futurenet2/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/.gitignore b/gnetlist/tests/common/outputs/geda/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/geda/JD-output.net b/gnetlist/tests/common/outputs/geda/JD-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/JD.retcode b/gnetlist/tests/common/outputs/geda/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include-output.net b/gnetlist/tests/common/outputs/geda/JD_Include-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Include-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include.retcode b/gnetlist/tests/common/outputs/geda/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort-output.net b/gnetlist/tests/common/outputs/geda/JD_Sort-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort.retcode b/gnetlist/tests/common/outputs/geda/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net b/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net
new file mode 100644
index 0000000..b885bfb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/JD_nomunge-output.net
@@ -0,0 +1,39 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=vpulse
+Cm device=CAPACITOR
+A1 device=model
+Rt device=RESISTOR
+M1 device=PMOS_TRANSISTOR
+X1 device=LVD
+Rlp device=RESISTOR
+Vdd device=VOLTAGE_SOURCE
+Rlm device=RESISTOR
+Cp device=CAPACITOR
+Rb device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+Vdd1 : Rlp 2, M1 B, M1 S, Vdd 1, X1 6 
+GND : Cm 2, Cp 2, Rlm 2, Vdd 2, V1 2, Rb 1, X1 7, X1 2 
+LVH : Rb 2, M1 D, M1 G, X1 3 
+i : V1 1, X1 1 
+p : Cp 1, Rt 1, Rlp 1, X1 5 
+m : Cm 1, Rlm 1, Rt 2, X1 4 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/Makefile.am b/gnetlist/tests/common/outputs/geda/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/geda/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/geda/SlottedOpamps-output.net
new file mode 100644
index 0000000..42c848f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/SlottedOpamps-output.net
@@ -0,0 +1,32 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+U1 device=LM324
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+minusin_slot4_pin13_b : U1 13 
+plusin_slot4_pin12_a : U1 12 
+minusin_slot3_pin_b : U1 9 
+plusin_slot3_pin10_a : U1 10 
+minusin_slot2_pin6_b : U1 6 
+plusin_slot2_pin5_a : U1 5 
+samenet_output_c : U1 14, U1 8, U1 7, U1 1 
+minusin_slot1_pin_b : U1 2 
+plusin_slot1_pin3_a : U1 3 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/geda/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net
new file mode 100644
index 0000000..c595660
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp-output.net
@@ -0,0 +1,57 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+Cout device=CAPACITOR
+R5 device=RESISTOR
+R4 device=RESISTOR
+RE2 device=RESISTOR
+Q2 device=NPN_TRANSISTOR
+A3 device=directive
+R3 device=RESISTOR
+A2 device=include
+RE1 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
+A1 device=model
+R2 device=RESISTOR
+Vinput device=vsin
+R1 device=RESISTOR
+C2 device=CAPACITOR
+CE2 device=CAPACITOR
+C1 device=CAPACITOR
+CE1 device=CAPACITOR
+R8 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
+RC2 device=RESISTOR
+RC1 device=RESISTOR
+RL device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+unnamed_net2 : C2 1, R8 2 
+Vbase2 : R3 1, C2 2, R4 2, Q2 2 
+Vem2 : CE2 2, RE2 2, Q2 1 
+Vout : Cout 2, RL 2 
+VColl2 : Q2 3, Cout 1, RC2 1 
+GND : R4 1, CE2 1, RE2 1, VCC 2, Vinput 2, CE1 1, RL 1, RE1 1, R2 1 
+Vcc : R3 2, RC1 2, VCC 1, RC2 2, R1 2 
+Vin : Vinput 1, R5 1 
+unnamed_net1 : C1 1, R5 2 
+Vbase1 : C1 2, R2 2, R1 1, Q1 2 
+Vem1 : CE1 2, RE1 2, Q1 1 
+Vcoll1 : R8 1, RC1 1, Q1 3 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/geda/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..c595660
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include-output.net
@@ -0,0 +1,57 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+Cout device=CAPACITOR
+R5 device=RESISTOR
+R4 device=RESISTOR
+RE2 device=RESISTOR
+Q2 device=NPN_TRANSISTOR
+A3 device=directive
+R3 device=RESISTOR
+A2 device=include
+RE1 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
+A1 device=model
+R2 device=RESISTOR
+Vinput device=vsin
+R1 device=RESISTOR
+C2 device=CAPACITOR
+CE2 device=CAPACITOR
+C1 device=CAPACITOR
+CE1 device=CAPACITOR
+R8 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
+RC2 device=RESISTOR
+RC1 device=RESISTOR
+RL device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+unnamed_net2 : C2 1, R8 2 
+Vbase2 : R3 1, C2 2, R4 2, Q2 2 
+Vem2 : CE2 2, RE2 2, Q2 1 
+Vout : Cout 2, RL 2 
+VColl2 : Q2 3, Cout 1, RC2 1 
+GND : R4 1, CE2 1, RE2 1, VCC 2, Vinput 2, CE1 1, RL 1, RE1 1, R2 1 
+Vcc : R3 2, RC1 2, VCC 1, RC2 2, R1 2 
+Vin : Vinput 1, R5 1 
+unnamed_net1 : C1 1, R5 2 
+Vbase1 : C1 2, R2 2, R1 1, Q1 2 
+Vem1 : CE1 2, RE1 2, Q1 1 
+Vcoll1 : R8 1, RC1 1, Q1 3 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..c595660
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort-output.net
@@ -0,0 +1,57 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+Cout device=CAPACITOR
+R5 device=RESISTOR
+R4 device=RESISTOR
+RE2 device=RESISTOR
+Q2 device=NPN_TRANSISTOR
+A3 device=directive
+R3 device=RESISTOR
+A2 device=include
+RE1 device=RESISTOR
+Q1 device=NPN_TRANSISTOR
+A1 device=model
+R2 device=RESISTOR
+Vinput device=vsin
+R1 device=RESISTOR
+C2 device=CAPACITOR
+CE2 device=CAPACITOR
+C1 device=CAPACITOR
+CE1 device=CAPACITOR
+R8 device=RESISTOR
+VCC device=VOLTAGE_SOURCE
+RC2 device=RESISTOR
+RC1 device=RESISTOR
+RL device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+unnamed_net2 : C2 1, R8 2 
+Vbase2 : R3 1, C2 2, R4 2, Q2 2 
+Vem2 : CE2 2, RE2 2, Q2 1 
+Vout : Cout 2, RL 2 
+VColl2 : Q2 3, Cout 1, RC2 1 
+GND : R4 1, CE2 1, RE2 1, VCC 2, Vinput 2, CE1 1, RL 1, RE1 1, R2 1 
+Vcc : R3 2, RC1 2, VCC 1, RC2 2, R1 2 
+Vin : Vinput 1, R5 1 
+unnamed_net1 : C1 1, R5 2 
+Vbase1 : C1 2, R2 2, R1 1, Q1 2 
+Vem1 : CE1 2, RE1 2, Q1 1 
+Vcoll1 : R8 1, RC1 1, Q1 3 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/cascade-output.net b/gnetlist/tests/common/outputs/geda/cascade-output.net
new file mode 100644
index 0000000..f868cb3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/cascade-output.net
@@ -0,0 +1,37 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+AMP2 device=cascade-amp
+AMP1 device=cascade-amp
+SOURCE device=cascade-source
+DEFAULTS device=cascade-defaults-top
+MX1 device=cascade-mixer
+DEF1 device=cascade-defaults
+T1 device=cascade-transformer
+FL1 device=cascade-filter
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+unnamed_net6 : AMP2 1, T1 2 
+unnamed_net5 : T1 1, MX1 2 
+unnamed_net4 : MX1 1, FL1 2 
+unnamed_net3 : FL1 1, DEF1 2 
+unnamed_net2 : DEF1 1, AMP1 2 
+unnamed_net1 : AMP1 1, SOURCE 1 
+GND : DEFAULTS 1 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/cascade.retcode b/gnetlist/tests/common/outputs/geda/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/multiequal-output.net b/gnetlist/tests/common/outputs/geda/multiequal-output.net
new file mode 100644
index 0000000..a723140
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/multiequal-output.net
@@ -0,0 +1,27 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+V1 device=VOLTAGE_SOURCE
+A1 device=options
+R1 device=RESISTOR
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+GND : V1 2, R1 1 
+unnamed_net1 : V1 1, R1 2 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/multiequal.retcode b/gnetlist/tests/common/outputs/geda/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/netattrib-output.net b/gnetlist/tests/common/outputs/geda/netattrib-output.net
new file mode 100644
index 0000000..684efb0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/netattrib-output.net
@@ -0,0 +1,32 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+F1 device=FUSE
+U100 device=7400
+U300 device=7404
+U200 device=7404
+
+END components
+
+START renamed-nets
+
+two -> one
+
+END renamed-nets
+
+START nets
+
+unnamed_net1 : U300 2 
+netattrib : U200 2, U100 5 
+GND : U300 7, U200 7, U100 7 
+Vcc : U300 14, U200 14, U100 14 
+one : F1 1, U300 1, U200 1, U100 3 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/netattrib.retcode b/gnetlist/tests/common/outputs/geda/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/powersupply-output.net b/gnetlist/tests/common/outputs/geda/powersupply-output.net
new file mode 100644
index 0000000..3471ddb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/powersupply-output.net
@@ -0,0 +1,46 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+F1 device=FUSE
+R2 device=RESISTOR
+CONN1 device=MAINS_CONNECTOR
+C4 device=POLARIZED_CAPACITOR
+R1 device=VARIABLE_RESISTOR
+C3 device=POLARIZED_CAPACITOR
+C2 device=POLARIZED_CAPACITOR
+S1 device=SPST
+C1 device=POLARIZED_CAPACITOR
+T1 device=transformer
+U2 device=LM317
+U1 device=DIODE-BRIDGE
+
+END components
+
+START renamed-nets
+
+four -> GND
+
+END renamed-nets
+
+START nets
+
+ten : U2 1, R1 2, C3 1, R2 1 
+eleven : U2 2, C4 1, R2 2 
+GND : CONN1 3 
+one : S1 1, CONN1 1 
+five : CONN1 2, T1 2 
+three : T1 1, F1 2 
+two : S1 2, F1 1 
+six : T1 3, U1 4 
+seven : T1 4, U1 3 
+nine : C4 2, C3 2, R1 3, R1 1, C2 2, C1 2, U1 2 
+eight : U2 3, C2 1, C1 1, U1 1 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/powersupply.retcode b/gnetlist/tests/common/outputs/geda/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/geda/singlenet-output.net b/gnetlist/tests/common/outputs/geda/singlenet-output.net
new file mode 100644
index 0000000..e557791
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/singlenet-output.net
@@ -0,0 +1,27 @@
+START header
+
+gEDA's netlist format
+Created specifically for testing of gnetlist
+
+END header
+
+START components
+
+U100 device=7400
+
+END components
+
+START renamed-nets
+
+
+END renamed-nets
+
+START nets
+
+SING_N_2 : U100 1, U100 3 
+GND : U100 7 
+Vcc : U100 14 
+SING_N : U100 4, U100 5, U100 10, U100 8, U100 9, U100 6 
+
+END nets
+
diff --git a/gnetlist/tests/common/outputs/geda/singlenet.retcode b/gnetlist/tests/common/outputs/geda/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/geda/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/.gitignore b/gnetlist/tests/common/outputs/gossip/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/gossip/JD-output.net b/gnetlist/tests/common/outputs/gossip/JD-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/JD.retcode b/gnetlist/tests/common/outputs/gossip/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include-output.net b/gnetlist/tests/common/outputs/gossip/JD_Include-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include.retcode b/gnetlist/tests/common/outputs/gossip/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net b/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort.retcode b/gnetlist/tests/common/outputs/gossip/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net
new file mode 100644
index 0000000..3417249
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/JD_nomunge-output.net
@@ -0,0 +1,19 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (Vdd1 GND LVH i p m))
+   (V1)
+   (Cm)
+   (A1)
+   (Rt)
+   (M1)
+   (X1)
+   (Rlp)
+   (Vdd)
+   (Rlm)
+   (Cp)
+   (Rb)
diff --git a/gnetlist/tests/common/outputs/gossip/Makefile.am b/gnetlist/tests/common/outputs/gossip/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/gossip/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/gossip/SlottedOpamps-output.net
new file mode 100644
index 0000000..3860661
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/SlottedOpamps-output.net
@@ -0,0 +1,9 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (minusin_slot4_pin13_b plusin_slot4_pin12_a minusin_slot3_pin_b plusin_slot3_pin10_a minusin_slot2_pin6_b plusin_slot2_pin5_a samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a))
+   (U1)
diff --git a/gnetlist/tests/common/outputs/gossip/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/gossip/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net
new file mode 100644
index 0000000..e75132d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp-output.net
@@ -0,0 +1,31 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
+   (Cout)
+   (R5)
+   (R4)
+   (RE2)
+   (Q2)
+   (A3)
+   (R3)
+   (A2)
+   (RE1)
+   (Q1)
+   (A1)
+   (R2)
+   (Vinput)
+   (R1)
+   (C2)
+   (CE2)
+   (C1)
+   (CE1)
+   (R8)
+   (VCC)
+   (RC2)
+   (RC1)
+   (RL)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/gossip/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..e75132d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include-output.net
@@ -0,0 +1,31 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
+   (Cout)
+   (R5)
+   (R4)
+   (RE2)
+   (Q2)
+   (A3)
+   (R3)
+   (A2)
+   (RE1)
+   (Q1)
+   (A1)
+   (R2)
+   (Vinput)
+   (R1)
+   (C2)
+   (CE2)
+   (C1)
+   (CE1)
+   (R8)
+   (VCC)
+   (RC2)
+   (RC1)
+   (RL)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..e75132d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort-output.net
@@ -0,0 +1,31 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (unnamed_net2 Vbase2 Vem2 Vout VColl2 GND Vcc Vin unnamed_net1 Vbase1 Vem1 Vcoll1))
+   (Cout)
+   (R5)
+   (R4)
+   (RE2)
+   (Q2)
+   (A3)
+   (R3)
+   (A2)
+   (RE1)
+   (Q1)
+   (A1)
+   (R2)
+   (Vinput)
+   (R1)
+   (C2)
+   (CE2)
+   (C1)
+   (CE1)
+   (R8)
+   (VCC)
+   (RC2)
+   (RC1)
+   (RL)
diff --git a/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/cascade-output.net b/gnetlist/tests/common/outputs/gossip/cascade-output.net
new file mode 100644
index 0000000..66837c8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/cascade-output.net
@@ -0,0 +1,16 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (unnamed_net6 unnamed_net5 unnamed_net4 unnamed_net3 unnamed_net2 unnamed_net1 GND))
+   (AMP2)
+   (AMP1)
+   (SOURCE)
+   (DEFAULTS)
+   (MX1)
+   (DEF1)
+   (T1)
+   (FL1)
diff --git a/gnetlist/tests/common/outputs/gossip/cascade.retcode b/gnetlist/tests/common/outputs/gossip/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/multiequal-output.net b/gnetlist/tests/common/outputs/gossip/multiequal-output.net
new file mode 100644
index 0000000..d40c383
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/multiequal-output.net
@@ -0,0 +1,11 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (GND unnamed_net1))
+   (V1)
+   (A1)
+   (R1)
diff --git a/gnetlist/tests/common/outputs/gossip/multiequal.retcode b/gnetlist/tests/common/outputs/gossip/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/netattrib-output.net b/gnetlist/tests/common/outputs/gossip/netattrib-output.net
new file mode 100644
index 0000000..6ab10f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/netattrib-output.net
@@ -0,0 +1,12 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (unnamed_net1 netattrib GND Vcc one))
+   (F1)
+   (U100)
+   (U300)
+   (U200)
diff --git a/gnetlist/tests/common/outputs/gossip/netattrib.retcode b/gnetlist/tests/common/outputs/gossip/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/powersupply-output.net b/gnetlist/tests/common/outputs/gossip/powersupply-output.net
new file mode 100644
index 0000000..4398267
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/powersupply-output.net
@@ -0,0 +1,20 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (ten eleven GND one five three two six seven nine eight))
+   (F1)
+   (R2)
+   (CONN1)
+   (C4)
+   (R1)
+   (C3)
+   (C2)
+   (S1)
+   (C1)
+   (T1)
+   (U2)
+   (U1)
diff --git a/gnetlist/tests/common/outputs/gossip/powersupply.retcode b/gnetlist/tests/common/outputs/gossip/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gossip/singlenet-output.net b/gnetlist/tests/common/outputs/gossip/singlenet-output.net
new file mode 100644
index 0000000..bba6423
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/singlenet-output.net
@@ -0,0 +1,9 @@
+;; Gossip Netlist Created by gNetlist
+
+;; Created By Matt Ettus <matt@xxxxxxxxx>
+;; Libraries:
+
+(use-library unknown *)
+(define-block (not found (
+(signals (SING_N_2 GND Vcc SING_N))
+   (U100)
diff --git a/gnetlist/tests/common/outputs/gossip/singlenet.retcode b/gnetlist/tests/common/outputs/gossip/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gossip/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/.gitignore b/gnetlist/tests/common/outputs/gsch2pcb/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD.retcode b/gnetlist/tests/common/outputs/gsch2pcb/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include.retcode b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort.retcode b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
new file mode 100644
index 0000000..5b0eab2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/JD_nomunge-output.net
@@ -0,0 +1,42 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+PKG_unknown(unknown,Cm,20p)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,Rt,1k)
+PKG_unknown(unknown,M1,unknown)
+PKG_unknown(unknown,X1,unknown)
+PKG_unknown(unknown,Rlp,1meg)
+PKG_none(none,Vdd,DC 3.3V)
+PKG_unknown(unknown,Rlm,500k)
+PKG_unknown(unknown,Cp,20p)
+PKG_unknown(unknown,Rb,5.6k)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/Makefile.am b/gnetlist/tests/common/outputs/gsch2pcb/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
new file mode 100644
index 0000000..371310a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps-output.net
@@ -0,0 +1,32 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,U1,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
new file mode 100644
index 0000000..4098d3d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp-output.net
@@ -0,0 +1,54 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,Q1,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,R2,2K)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,R8,1)
+PKG_none(none,VCC,DC 15V)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,RL,100K)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..4098d3d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include-output.net
@@ -0,0 +1,54 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,Q1,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,R2,2K)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,R8,1)
+PKG_none(none,VCC,DC 15V)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,RL,100K)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..4098d3d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort-output.net
@@ -0,0 +1,54 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,Cout,2.2uF)
+PKG_unknown(unknown,R5,10)
+PKG_unknown(unknown,R4,2.8K)
+PKG_unknown(unknown,RE2,100)
+PKG_unknown(unknown,Q2,unknown)
+PKG_unknown(unknown,A3,.options TEMP=25)
+PKG_unknown(unknown,R3,28K)
+PKG_unknown(unknown,A2,unknown)
+PKG_unknown(unknown,RE1,100)
+PKG_unknown(unknown,Q1,unknown)
+PKG_unknown(unknown,A1,unknown)
+PKG_unknown(unknown,R2,2K)
+PKG_none(none,Vinput,DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+PKG_unknown(unknown,R1,28K)
+PKG_unknown(unknown,C2,2.2uF)
+PKG_unknown(unknown,CE2,1pF)
+PKG_unknown(unknown,C1,2.2uF)
+PKG_unknown(unknown,CE1,1pF)
+PKG_unknown(unknown,R8,1)
+PKG_none(none,VCC,DC 15V)
+PKG_unknown(unknown,RC2,1K)
+PKG_unknown(unknown,RC1,3.3K)
+PKG_unknown(unknown,RL,100K)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
new file mode 100644
index 0000000..e8f8a0a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/cascade-output.net
@@ -0,0 +1,39 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,AMP2,unknown)
+PKG_none(none,AMP1,unknown)
+PKG_none(none,SOURCE,unknown)
+PKG_unknown(unknown,DEFAULTS,unknown)
+PKG_none(none,MX1,unknown)
+PKG_none(none,DEF1,unknown)
+PKG_none(none,T1,unknown)
+PKG_none(none,FL1,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/cascade.retcode b/gnetlist/tests/common/outputs/gsch2pcb/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
new file mode 100644
index 0000000..89423f3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/multiequal-output.net
@@ -0,0 +1,34 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_none(none,V1,DC 1V)
+PKG_unknown(unknown,A1,abotol=1e-11)
+PKG_unknown(unknown,R1,20)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/multiequal.retcode b/gnetlist/tests/common/outputs/gsch2pcb/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
new file mode 100644
index 0000000..bb87af6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/netattrib-output.net
@@ -0,0 +1,35 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,F1,unknown)
+PKG_DIP14(DIP14,U100,unknown)
+PKG_DIP14(DIP14,U300,unknown)
+PKG_DIP14(DIP14,U200,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/netattrib.retcode b/gnetlist/tests/common/outputs/gsch2pcb/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
new file mode 100644
index 0000000..28efa25
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/powersupply-output.net
@@ -0,0 +1,43 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_unknown(unknown,F1,unknown)
+PKG_unknown(unknown,R2,220)
+PKG_unknown(unknown,CONN1,unknown)
+PKG_unknown(unknown,C4,1uf)
+PKG_unknown(unknown,R1,5k)
+PKG_unknown(unknown,C3,22uF)
+PKG_unknown(unknown,C2,0.1uF)
+PKG_unknown(unknown,S1,unknown)
+PKG_unknown(unknown,C1,2200uF)
+PKG_unknown(unknown,T1,unknown)
+PKG_unknown(unknown,U2,unknown)
+PKG_unknown(unknown,U1,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/powersupply.retcode b/gnetlist/tests/common/outputs/gsch2pcb/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
new file mode 100644
index 0000000..f424bb0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/singlenet-output.net
@@ -0,0 +1,32 @@
+# release: pcb 1.6.3
+PCB("" 6000 5000)
+Grid(10 0 0)
+Cursor(0 0 3)
+Flags(0x000000d0)
+Groups("1,2,3,s:4,5,6,c:7:8:")
+Styles("Signal,10,40,20:Power,25,60,35:Fat,40,60,35:Skinny,8,36,20")
+PKG_DIP14(DIP14,U100,unknown)
+Layer(1 "solder")
+(
+)
+Layer(2 "GND-sldr")
+(
+)
+Layer(3 "Vcc-sldr")
+(
+)
+Layer(4 "component")
+(
+)
+Layer(5 "GND-comp")
+(
+)
+Layer(6 "Vcc-comp")
+(
+)
+Layer(7 "unused")
+(
+)
+Layer(8 "unused")
+(
+)
diff --git a/gnetlist/tests/common/outputs/gsch2pcb/singlenet.retcode b/gnetlist/tests/common/outputs/gsch2pcb/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/gsch2pcb/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/.gitignore b/gnetlist/tests/common/outputs/mathematica/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/mathematica/JD-output.net b/gnetlist/tests/common/outputs/mathematica/JD-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/JD.retcode b/gnetlist/tests/common/outputs/mathematica/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include.retcode b/gnetlist/tests/common/outputs/mathematica/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort.retcode b/gnetlist/tests/common/outputs/mathematica/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net b/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net
new file mode 100644
index 0000000..1b203f4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/JD_nomunge-output.net
@@ -0,0 +1,78 @@
+v["Rlp","2"]=v["Vdd1"];
+v["M1","B"]=v["Vdd1"];
+v["M1","S"]=v["Vdd1"];
+v["Vdd","1"]=v["Vdd1"];
+v["X1","6"]=v["Vdd1"];
+v["Cm","2"]=v["GND"];
+v["Cp","2"]=v["GND"];
+v["Rlm","2"]=v["GND"];
+v["Vdd","2"]=v["GND"];
+v["V1","2"]=v["GND"];
+v["Rb","1"]=v["GND"];
+v["X1","7"]=v["GND"];
+v["X1","2"]=v["GND"];
+v["Rb","2"]=v["LVH"];
+v["M1","D"]=v["LVH"];
+v["M1","G"]=v["LVH"];
+v["X1","3"]=v["LVH"];
+v["V1","1"]=v["i"];
+v["X1","1"]=v["i"];
+v["Cp","1"]=v["p"];
+v["Rt","1"]=v["p"];
+v["Rlp","1"]=v["p"];
+v["X1","5"]=v["p"];
+v["Cm","1"]=v["m"];
+v["Rlm","1"]=v["m"];
+v["Rt","2"]=v["m"];
+v["X1","4"]=v["m"];
+nodeEquations={
+i["Rlp","2"]+i["M1","B"]+i["M1","S"]+i["Vdd","1"]+i["X1","6"]==0,
+i["Rb","2"]+i["M1","D"]+i["M1","G"]+i["X1","3"]==0,
+i["V1","1"]+i["X1","1"]==0,
+i["Cp","1"]+i["Rt","1"]+i["Rlp","1"]+i["X1","5"]==0,
+i["Cm","1"]+i["Rlm","1"]+i["Rt","2"]+i["X1","4"]==0};
+modelEquations={
+vpulse[value->pulse 3.3 0 1u 10p 10p 1.25u 2.5u]["V1"],
+capacitor[value->20p]["Cm"],
+model[value->a1]["A1"],
+resistor[value->1k]["Rt"],
+pmos_transistor[value->m1]["M1"],
+lvd[value->x1]["X1"],
+resistor[value->1meg]["Rlp"],
+voltage_source[value->DC 3.3V]["Vdd"],
+resistor[value->500k]["Rlm"],
+capacitor[value->20p]["Cp"],
+resistor[value->5.6k]["Rb"]};
+variables={
+v["Vdd1"],
+v["LVH"],
+v["i"],
+v["p"],
+v["m"],
+i["Rlp","2"],
+i["M1","B"],
+i["M1","S"],
+i["Vdd","1"],
+i["X1","6"],
+i["Cm","2"],
+i["Cp","2"],
+i["Rlm","2"],
+i["Vdd","2"],
+i["V1","2"],
+i["Rb","1"],
+i["X1","7"],
+i["X1","2"],
+i["Rb","2"],
+i["M1","D"],
+i["M1","G"],
+i["X1","3"],
+i["V1","1"],
+i["X1","1"],
+i["Cp","1"],
+i["Rt","1"],
+i["Rlp","1"],
+i["X1","5"],
+i["Cm","1"],
+i["Rlm","1"],
+i["Rt","2"],
+i["X1","4"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/Makefile.am b/gnetlist/tests/common/outputs/mathematica/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/mathematica/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/mathematica/SlottedOpamps-output.net
new file mode 100644
index 0000000..8975d7e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/SlottedOpamps-output.net
@@ -0,0 +1,46 @@
+v["U1","13"]=v["minusin_slot4_pin13_b"];
+v["U1","12"]=v["plusin_slot4_pin12_a"];
+v["U1","9"]=v["minusin_slot3_pin_b"];
+v["U1","10"]=v["plusin_slot3_pin10_a"];
+v["U1","6"]=v["minusin_slot2_pin6_b"];
+v["U1","5"]=v["plusin_slot2_pin5_a"];
+v["U1","14"]=v["samenet_output_c"];
+v["U1","8"]=v["samenet_output_c"];
+v["U1","7"]=v["samenet_output_c"];
+v["U1","1"]=v["samenet_output_c"];
+v["U1","2"]=v["minusin_slot1_pin_b"];
+v["U1","3"]=v["plusin_slot1_pin3_a"];
+nodeEquations={
+i["U1","13"]==0,
+i["U1","12"]==0,
+i["U1","9"]==0,
+i["U1","10"]==0,
+i["U1","6"]==0,
+i["U1","5"]==0,
+i["U1","14"]+i["U1","8"]+i["U1","7"]+i["U1","1"]==0,
+i["U1","2"]==0,
+i["U1","3"]==0};
+modelEquations={
+lm324[value->u1]["U1"]};
+variables={
+v["minusin_slot4_pin13_b"],
+v["plusin_slot4_pin12_a"],
+v["minusin_slot3_pin_b"],
+v["plusin_slot3_pin10_a"],
+v["minusin_slot2_pin6_b"],
+v["plusin_slot2_pin5_a"],
+v["samenet_output_c"],
+v["minusin_slot1_pin_b"],
+v["plusin_slot1_pin3_a"],
+i["U1","13"],
+i["U1","12"],
+i["U1","9"],
+i["U1","10"],
+i["U1","6"],
+i["U1","5"],
+i["U1","14"],
+i["U1","8"],
+i["U1","7"],
+i["U1","1"],
+i["U1","2"],
+i["U1","3"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/mathematica/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net
new file mode 100644
index 0000000..b6e4434
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp-output.net
@@ -0,0 +1,132 @@
+v["C2","1"]=v["unnamed_net2"];
+v["R8","2"]=v["unnamed_net2"];
+v["R3","1"]=v["Vbase2"];
+v["C2","2"]=v["Vbase2"];
+v["R4","2"]=v["Vbase2"];
+v["Q2","2"]=v["Vbase2"];
+v["CE2","2"]=v["Vem2"];
+v["RE2","2"]=v["Vem2"];
+v["Q2","1"]=v["Vem2"];
+v["Cout","2"]=v["Vout"];
+v["RL","2"]=v["Vout"];
+v["Q2","3"]=v["VColl2"];
+v["Cout","1"]=v["VColl2"];
+v["RC2","1"]=v["VColl2"];
+v["R4","1"]=v["GND"];
+v["CE2","1"]=v["GND"];
+v["RE2","1"]=v["GND"];
+v["VCC","2"]=v["GND"];
+v["Vinput","2"]=v["GND"];
+v["CE1","1"]=v["GND"];
+v["RL","1"]=v["GND"];
+v["RE1","1"]=v["GND"];
+v["R2","1"]=v["GND"];
+v["R3","2"]=v["Vcc"];
+v["RC1","2"]=v["Vcc"];
+v["VCC","1"]=v["Vcc"];
+v["RC2","2"]=v["Vcc"];
+v["R1","2"]=v["Vcc"];
+v["Vinput","1"]=v["Vin"];
+v["R5","1"]=v["Vin"];
+v["C1","1"]=v["unnamed_net1"];
+v["R5","2"]=v["unnamed_net1"];
+v["C1","2"]=v["Vbase1"];
+v["R2","2"]=v["Vbase1"];
+v["R1","1"]=v["Vbase1"];
+v["Q1","2"]=v["Vbase1"];
+v["CE1","2"]=v["Vem1"];
+v["RE1","2"]=v["Vem1"];
+v["Q1","1"]=v["Vem1"];
+v["R8","1"]=v["Vcoll1"];
+v["RC1","1"]=v["Vcoll1"];
+v["Q1","3"]=v["Vcoll1"];
+nodeEquations={
+i["C2","1"]+i["R8","2"]==0,
+i["R3","1"]+i["C2","2"]+i["R4","2"]+i["Q2","2"]==0,
+i["CE2","2"]+i["RE2","2"]+i["Q2","1"]==0,
+i["Cout","2"]+i["RL","2"]==0,
+i["Q2","3"]+i["Cout","1"]+i["RC2","1"]==0,
+i["R3","2"]+i["RC1","2"]+i["VCC","1"]+i["RC2","2"]+i["R1","2"]==0,
+i["Vinput","1"]+i["R5","1"]==0,
+i["C1","1"]+i["R5","2"]==0,
+i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
+i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
+i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
+modelEquations={
+capacitor[value->2.2uF]["Cout"],
+resistor[value->10]["R5"],
+resistor[value->2.8K]["R4"],
+resistor[value->100]["RE2"],
+npn_transistor[value->q2]["Q2"],
+directive[value->.options TEMP=25]["A3"],
+resistor[value->28K]["R3"],
+include[value->a2]["A2"],
+resistor[value->100]["RE1"],
+npn_transistor[value->q1]["Q1"],
+model[value->a1]["A1"],
+resistor[value->2K]["R2"],
+vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
+resistor[value->28K]["R1"],
+capacitor[value->2.2uF]["C2"],
+capacitor[value->1pF]["CE2"],
+capacitor[value->2.2uF]["C1"],
+capacitor[value->1pF]["CE1"],
+resistor[value->1]["R8"],
+voltage_source[value->DC 15V]["VCC"],
+resistor[value->1K]["RC2"],
+resistor[value->3.3K]["RC1"],
+resistor[value->100K]["RL"]};
+variables={
+v["unnamed_net2"],
+v["Vbase2"],
+v["Vem2"],
+v["Vout"],
+v["VColl2"],
+v["Vcc"],
+v["Vin"],
+v["unnamed_net1"],
+v["Vbase1"],
+v["Vem1"],
+v["Vcoll1"],
+i["C2","1"],
+i["R8","2"],
+i["R3","1"],
+i["C2","2"],
+i["R4","2"],
+i["Q2","2"],
+i["CE2","2"],
+i["RE2","2"],
+i["Q2","1"],
+i["Cout","2"],
+i["RL","2"],
+i["Q2","3"],
+i["Cout","1"],
+i["RC2","1"],
+i["R4","1"],
+i["CE2","1"],
+i["RE2","1"],
+i["VCC","2"],
+i["Vinput","2"],
+i["CE1","1"],
+i["RL","1"],
+i["RE1","1"],
+i["R2","1"],
+i["R3","2"],
+i["RC1","2"],
+i["VCC","1"],
+i["RC2","2"],
+i["R1","2"],
+i["Vinput","1"],
+i["R5","1"],
+i["C1","1"],
+i["R5","2"],
+i["C1","2"],
+i["R2","2"],
+i["R1","1"],
+i["Q1","2"],
+i["CE1","2"],
+i["RE1","2"],
+i["Q1","1"],
+i["R8","1"],
+i["RC1","1"],
+i["Q1","3"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..b6e4434
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include-output.net
@@ -0,0 +1,132 @@
+v["C2","1"]=v["unnamed_net2"];
+v["R8","2"]=v["unnamed_net2"];
+v["R3","1"]=v["Vbase2"];
+v["C2","2"]=v["Vbase2"];
+v["R4","2"]=v["Vbase2"];
+v["Q2","2"]=v["Vbase2"];
+v["CE2","2"]=v["Vem2"];
+v["RE2","2"]=v["Vem2"];
+v["Q2","1"]=v["Vem2"];
+v["Cout","2"]=v["Vout"];
+v["RL","2"]=v["Vout"];
+v["Q2","3"]=v["VColl2"];
+v["Cout","1"]=v["VColl2"];
+v["RC2","1"]=v["VColl2"];
+v["R4","1"]=v["GND"];
+v["CE2","1"]=v["GND"];
+v["RE2","1"]=v["GND"];
+v["VCC","2"]=v["GND"];
+v["Vinput","2"]=v["GND"];
+v["CE1","1"]=v["GND"];
+v["RL","1"]=v["GND"];
+v["RE1","1"]=v["GND"];
+v["R2","1"]=v["GND"];
+v["R3","2"]=v["Vcc"];
+v["RC1","2"]=v["Vcc"];
+v["VCC","1"]=v["Vcc"];
+v["RC2","2"]=v["Vcc"];
+v["R1","2"]=v["Vcc"];
+v["Vinput","1"]=v["Vin"];
+v["R5","1"]=v["Vin"];
+v["C1","1"]=v["unnamed_net1"];
+v["R5","2"]=v["unnamed_net1"];
+v["C1","2"]=v["Vbase1"];
+v["R2","2"]=v["Vbase1"];
+v["R1","1"]=v["Vbase1"];
+v["Q1","2"]=v["Vbase1"];
+v["CE1","2"]=v["Vem1"];
+v["RE1","2"]=v["Vem1"];
+v["Q1","1"]=v["Vem1"];
+v["R8","1"]=v["Vcoll1"];
+v["RC1","1"]=v["Vcoll1"];
+v["Q1","3"]=v["Vcoll1"];
+nodeEquations={
+i["C2","1"]+i["R8","2"]==0,
+i["R3","1"]+i["C2","2"]+i["R4","2"]+i["Q2","2"]==0,
+i["CE2","2"]+i["RE2","2"]+i["Q2","1"]==0,
+i["Cout","2"]+i["RL","2"]==0,
+i["Q2","3"]+i["Cout","1"]+i["RC2","1"]==0,
+i["R3","2"]+i["RC1","2"]+i["VCC","1"]+i["RC2","2"]+i["R1","2"]==0,
+i["Vinput","1"]+i["R5","1"]==0,
+i["C1","1"]+i["R5","2"]==0,
+i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
+i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
+i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
+modelEquations={
+capacitor[value->2.2uF]["Cout"],
+resistor[value->10]["R5"],
+resistor[value->2.8K]["R4"],
+resistor[value->100]["RE2"],
+npn_transistor[value->q2]["Q2"],
+directive[value->.options TEMP=25]["A3"],
+resistor[value->28K]["R3"],
+include[value->a2]["A2"],
+resistor[value->100]["RE1"],
+npn_transistor[value->q1]["Q1"],
+model[value->a1]["A1"],
+resistor[value->2K]["R2"],
+vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
+resistor[value->28K]["R1"],
+capacitor[value->2.2uF]["C2"],
+capacitor[value->1pF]["CE2"],
+capacitor[value->2.2uF]["C1"],
+capacitor[value->1pF]["CE1"],
+resistor[value->1]["R8"],
+voltage_source[value->DC 15V]["VCC"],
+resistor[value->1K]["RC2"],
+resistor[value->3.3K]["RC1"],
+resistor[value->100K]["RL"]};
+variables={
+v["unnamed_net2"],
+v["Vbase2"],
+v["Vem2"],
+v["Vout"],
+v["VColl2"],
+v["Vcc"],
+v["Vin"],
+v["unnamed_net1"],
+v["Vbase1"],
+v["Vem1"],
+v["Vcoll1"],
+i["C2","1"],
+i["R8","2"],
+i["R3","1"],
+i["C2","2"],
+i["R4","2"],
+i["Q2","2"],
+i["CE2","2"],
+i["RE2","2"],
+i["Q2","1"],
+i["Cout","2"],
+i["RL","2"],
+i["Q2","3"],
+i["Cout","1"],
+i["RC2","1"],
+i["R4","1"],
+i["CE2","1"],
+i["RE2","1"],
+i["VCC","2"],
+i["Vinput","2"],
+i["CE1","1"],
+i["RL","1"],
+i["RE1","1"],
+i["R2","1"],
+i["R3","2"],
+i["RC1","2"],
+i["VCC","1"],
+i["RC2","2"],
+i["R1","2"],
+i["Vinput","1"],
+i["R5","1"],
+i["C1","1"],
+i["R5","2"],
+i["C1","2"],
+i["R2","2"],
+i["R1","1"],
+i["Q1","2"],
+i["CE1","2"],
+i["RE1","2"],
+i["Q1","1"],
+i["R8","1"],
+i["RC1","1"],
+i["Q1","3"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..b6e4434
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort-output.net
@@ -0,0 +1,132 @@
+v["C2","1"]=v["unnamed_net2"];
+v["R8","2"]=v["unnamed_net2"];
+v["R3","1"]=v["Vbase2"];
+v["C2","2"]=v["Vbase2"];
+v["R4","2"]=v["Vbase2"];
+v["Q2","2"]=v["Vbase2"];
+v["CE2","2"]=v["Vem2"];
+v["RE2","2"]=v["Vem2"];
+v["Q2","1"]=v["Vem2"];
+v["Cout","2"]=v["Vout"];
+v["RL","2"]=v["Vout"];
+v["Q2","3"]=v["VColl2"];
+v["Cout","1"]=v["VColl2"];
+v["RC2","1"]=v["VColl2"];
+v["R4","1"]=v["GND"];
+v["CE2","1"]=v["GND"];
+v["RE2","1"]=v["GND"];
+v["VCC","2"]=v["GND"];
+v["Vinput","2"]=v["GND"];
+v["CE1","1"]=v["GND"];
+v["RL","1"]=v["GND"];
+v["RE1","1"]=v["GND"];
+v["R2","1"]=v["GND"];
+v["R3","2"]=v["Vcc"];
+v["RC1","2"]=v["Vcc"];
+v["VCC","1"]=v["Vcc"];
+v["RC2","2"]=v["Vcc"];
+v["R1","2"]=v["Vcc"];
+v["Vinput","1"]=v["Vin"];
+v["R5","1"]=v["Vin"];
+v["C1","1"]=v["unnamed_net1"];
+v["R5","2"]=v["unnamed_net1"];
+v["C1","2"]=v["Vbase1"];
+v["R2","2"]=v["Vbase1"];
+v["R1","1"]=v["Vbase1"];
+v["Q1","2"]=v["Vbase1"];
+v["CE1","2"]=v["Vem1"];
+v["RE1","2"]=v["Vem1"];
+v["Q1","1"]=v["Vem1"];
+v["R8","1"]=v["Vcoll1"];
+v["RC1","1"]=v["Vcoll1"];
+v["Q1","3"]=v["Vcoll1"];
+nodeEquations={
+i["C2","1"]+i["R8","2"]==0,
+i["R3","1"]+i["C2","2"]+i["R4","2"]+i["Q2","2"]==0,
+i["CE2","2"]+i["RE2","2"]+i["Q2","1"]==0,
+i["Cout","2"]+i["RL","2"]==0,
+i["Q2","3"]+i["Cout","1"]+i["RC2","1"]==0,
+i["R3","2"]+i["RC1","2"]+i["VCC","1"]+i["RC2","2"]+i["R1","2"]==0,
+i["Vinput","1"]+i["R5","1"]==0,
+i["C1","1"]+i["R5","2"]==0,
+i["C1","2"]+i["R2","2"]+i["R1","1"]+i["Q1","2"]==0,
+i["CE1","2"]+i["RE1","2"]+i["Q1","1"]==0,
+i["R8","1"]+i["RC1","1"]+i["Q1","3"]==0};
+modelEquations={
+capacitor[value->2.2uF]["Cout"],
+resistor[value->10]["R5"],
+resistor[value->2.8K]["R4"],
+resistor[value->100]["RE2"],
+npn_transistor[value->q2]["Q2"],
+directive[value->.options TEMP=25]["A3"],
+resistor[value->28K]["R3"],
+include[value->a2]["A2"],
+resistor[value->100]["RE1"],
+npn_transistor[value->q1]["Q1"],
+model[value->a1]["A1"],
+resistor[value->2K]["R2"],
+vsin[value->DC 1.6V AC 10MV SIN(0 1MV 1KHZ)]["Vinput"],
+resistor[value->28K]["R1"],
+capacitor[value->2.2uF]["C2"],
+capacitor[value->1pF]["CE2"],
+capacitor[value->2.2uF]["C1"],
+capacitor[value->1pF]["CE1"],
+resistor[value->1]["R8"],
+voltage_source[value->DC 15V]["VCC"],
+resistor[value->1K]["RC2"],
+resistor[value->3.3K]["RC1"],
+resistor[value->100K]["RL"]};
+variables={
+v["unnamed_net2"],
+v["Vbase2"],
+v["Vem2"],
+v["Vout"],
+v["VColl2"],
+v["Vcc"],
+v["Vin"],
+v["unnamed_net1"],
+v["Vbase1"],
+v["Vem1"],
+v["Vcoll1"],
+i["C2","1"],
+i["R8","2"],
+i["R3","1"],
+i["C2","2"],
+i["R4","2"],
+i["Q2","2"],
+i["CE2","2"],
+i["RE2","2"],
+i["Q2","1"],
+i["Cout","2"],
+i["RL","2"],
+i["Q2","3"],
+i["Cout","1"],
+i["RC2","1"],
+i["R4","1"],
+i["CE2","1"],
+i["RE2","1"],
+i["VCC","2"],
+i["Vinput","2"],
+i["CE1","1"],
+i["RL","1"],
+i["RE1","1"],
+i["R2","1"],
+i["R3","2"],
+i["RC1","2"],
+i["VCC","1"],
+i["RC2","2"],
+i["R1","2"],
+i["Vinput","1"],
+i["R5","1"],
+i["C1","1"],
+i["R5","2"],
+i["C1","2"],
+i["R2","2"],
+i["R1","1"],
+i["Q1","2"],
+i["CE1","2"],
+i["RE1","2"],
+i["Q1","1"],
+i["R8","1"],
+i["RC1","1"],
+i["Q1","3"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/cascade-output.net b/gnetlist/tests/common/outputs/mathematica/cascade-output.net
new file mode 100644
index 0000000..c154417
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/cascade-output.net
@@ -0,0 +1,49 @@
+v["AMP2","1"]=v["unnamed_net6"];
+v["T1","2"]=v["unnamed_net6"];
+v["T1","1"]=v["unnamed_net5"];
+v["MX1","2"]=v["unnamed_net5"];
+v["MX1","1"]=v["unnamed_net4"];
+v["FL1","2"]=v["unnamed_net4"];
+v["FL1","1"]=v["unnamed_net3"];
+v["DEF1","2"]=v["unnamed_net3"];
+v["DEF1","1"]=v["unnamed_net2"];
+v["AMP1","2"]=v["unnamed_net2"];
+v["AMP1","1"]=v["unnamed_net1"];
+v["SOURCE","1"]=v["unnamed_net1"];
+v["DEFAULTS","1"]=v["GND"];
+nodeEquations={
+i["AMP2","1"]+i["T1","2"]==0,
+i["T1","1"]+i["MX1","2"]==0,
+i["MX1","1"]+i["FL1","2"]==0,
+i["FL1","1"]+i["DEF1","2"]==0,
+i["DEF1","1"]+i["AMP1","2"]==0,
+i["AMP1","1"]+i["SOURCE","1"]==0};
+modelEquations={
+cascade-amp[value->amp2]["AMP2"],
+cascade-amp[value->amp1]["AMP1"],
+cascade-source[value->source]["SOURCE"],
+cascade-defaults-top[value->defaults]["DEFAULTS"],
+cascade-mixer[value->mx1]["MX1"],
+cascade-defaults[value->def1]["DEF1"],
+cascade-transformer[value->t1]["T1"],
+cascade-filter[value->fl1]["FL1"]};
+variables={
+v["unnamed_net6"],
+v["unnamed_net5"],
+v["unnamed_net4"],
+v["unnamed_net3"],
+v["unnamed_net2"],
+v["unnamed_net1"],
+i["AMP2","1"],
+i["T1","2"],
+i["T1","1"],
+i["MX1","2"],
+i["MX1","1"],
+i["FL1","2"],
+i["FL1","1"],
+i["DEF1","2"],
+i["DEF1","1"],
+i["AMP1","2"],
+i["AMP1","1"],
+i["SOURCE","1"],
+i["DEFAULTS","1"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/cascade.retcode b/gnetlist/tests/common/outputs/mathematica/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/multiequal-output.net b/gnetlist/tests/common/outputs/mathematica/multiequal-output.net
new file mode 100644
index 0000000..bc10b94
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/multiequal-output.net
@@ -0,0 +1,16 @@
+v["V1","2"]=v["GND"];
+v["R1","1"]=v["GND"];
+v["V1","1"]=v["unnamed_net1"];
+v["R1","2"]=v["unnamed_net1"];
+nodeEquations={
+i["V1","1"]+i["R1","2"]==0};
+modelEquations={
+voltage_source[value->DC 1V]["V1"],
+options[value->abotol=1e-11]["A1"],
+resistor[value->20]["R1"]};
+variables={
+v["unnamed_net1"],
+i["V1","2"],
+i["R1","1"],
+i["V1","1"],
+i["R1","2"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/multiequal.retcode b/gnetlist/tests/common/outputs/mathematica/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/netattrib-output.net b/gnetlist/tests/common/outputs/mathematica/netattrib-output.net
new file mode 100644
index 0000000..d83c0b1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/netattrib-output.net
@@ -0,0 +1,41 @@
+v["U300","2"]=v["unnamed_net1"];
+v["U200","2"]=v["netattrib"];
+v["U100","5"]=v["netattrib"];
+v["U300","7"]=v["GND"];
+v["U200","7"]=v["GND"];
+v["U100","7"]=v["GND"];
+v["U300","14"]=v["Vcc"];
+v["U200","14"]=v["Vcc"];
+v["U100","14"]=v["Vcc"];
+v["F1","1"]=v["one"];
+v["U300","1"]=v["one"];
+v["U200","1"]=v["one"];
+v["U100","3"]=v["one"];
+nodeEquations={
+i["U300","2"]==0,
+i["U200","2"]+i["U100","5"]==0,
+i["U300","14"]+i["U200","14"]+i["U100","14"]==0,
+i["F1","1"]+i["U300","1"]+i["U200","1"]+i["U100","3"]==0};
+modelEquations={
+fuse[value->f1]["F1"],
+7400[value->u100]["U100"],
+7404[value->u300]["U300"],
+7404[value->u200]["U200"]};
+variables={
+v["unnamed_net1"],
+v["netattrib"],
+v["Vcc"],
+v["one"],
+i["U300","2"],
+i["U200","2"],
+i["U100","5"],
+i["U300","7"],
+i["U200","7"],
+i["U100","7"],
+i["U300","14"],
+i["U200","14"],
+i["U100","14"],
+i["F1","1"],
+i["U300","1"],
+i["U200","1"],
+i["U100","3"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/netattrib.retcode b/gnetlist/tests/common/outputs/mathematica/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/powersupply-output.net b/gnetlist/tests/common/outputs/mathematica/powersupply-output.net
new file mode 100644
index 0000000..ae09c90
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/powersupply-output.net
@@ -0,0 +1,97 @@
+v["U2","1"]=v["ten"];
+v["R1","2"]=v["ten"];
+v["C3","1"]=v["ten"];
+v["R2","1"]=v["ten"];
+v["U2","2"]=v["eleven"];
+v["C4","1"]=v["eleven"];
+v["R2","2"]=v["eleven"];
+v["CONN1","3"]=v["GND"];
+v["S1","1"]=v["one"];
+v["CONN1","1"]=v["one"];
+v["CONN1","2"]=v["five"];
+v["T1","2"]=v["five"];
+v["T1","1"]=v["three"];
+v["F1","2"]=v["three"];
+v["S1","2"]=v["two"];
+v["F1","1"]=v["two"];
+v["T1","3"]=v["six"];
+v["U1","4"]=v["six"];
+v["T1","4"]=v["seven"];
+v["U1","3"]=v["seven"];
+v["C4","2"]=v["nine"];
+v["C3","2"]=v["nine"];
+v["R1","3"]=v["nine"];
+v["R1","1"]=v["nine"];
+v["C2","2"]=v["nine"];
+v["C1","2"]=v["nine"];
+v["U1","2"]=v["nine"];
+v["U2","3"]=v["eight"];
+v["C2","1"]=v["eight"];
+v["C1","1"]=v["eight"];
+v["U1","1"]=v["eight"];
+nodeEquations={
+i["U2","1"]+i["R1","2"]+i["C3","1"]+i["R2","1"]==0,
+i["U2","2"]+i["C4","1"]+i["R2","2"]==0,
+i["S1","1"]+i["CONN1","1"]==0,
+i["CONN1","2"]+i["T1","2"]==0,
+i["T1","1"]+i["F1","2"]==0,
+i["S1","2"]+i["F1","1"]==0,
+i["T1","3"]+i["U1","4"]==0,
+i["T1","4"]+i["U1","3"]==0,
+i["C4","2"]+i["C3","2"]+i["R1","3"]+i["R1","1"]+i["C2","2"]+i["C1","2"]+i["U1","2"]==0,
+i["U2","3"]+i["C2","1"]+i["C1","1"]+i["U1","1"]==0};
+modelEquations={
+fuse[value->f1]["F1"],
+resistor[value->220]["R2"],
+mains_connector[value->conn1]["CONN1"],
+polarized_capacitor[value->1uf]["C4"],
+variable_resistor[value->5k]["R1"],
+polarized_capacitor[value->22uF]["C3"],
+polarized_capacitor[value->0.1uF]["C2"],
+spst[value->s1]["S1"],
+polarized_capacitor[value->2200uF]["C1"],
+transformer[value->t1]["T1"],
+lm317[value->u2]["U2"],
+diode-bridge[value->u1]["U1"]};
+variables={
+v["ten"],
+v["eleven"],
+v["one"],
+v["five"],
+v["three"],
+v["two"],
+v["six"],
+v["seven"],
+v["nine"],
+v["eight"],
+i["U2","1"],
+i["R1","2"],
+i["C3","1"],
+i["R2","1"],
+i["U2","2"],
+i["C4","1"],
+i["R2","2"],
+i["CONN1","3"],
+i["S1","1"],
+i["CONN1","1"],
+i["CONN1","2"],
+i["T1","2"],
+i["T1","1"],
+i["F1","2"],
+i["S1","2"],
+i["F1","1"],
+i["T1","3"],
+i["U1","4"],
+i["T1","4"],
+i["U1","3"],
+i["C4","2"],
+i["C3","2"],
+i["R1","3"],
+i["R1","1"],
+i["C2","2"],
+i["C1","2"],
+i["U1","2"],
+i["U2","3"],
+i["C2","1"],
+i["C1","1"],
+i["U1","1"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/powersupply.retcode b/gnetlist/tests/common/outputs/mathematica/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/mathematica/singlenet-output.net b/gnetlist/tests/common/outputs/mathematica/singlenet-output.net
new file mode 100644
index 0000000..0cb3d1c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/singlenet-output.net
@@ -0,0 +1,30 @@
+v["U100","1"]=v["SING_N_2"];
+v["U100","3"]=v["SING_N_2"];
+v["U100","7"]=v["GND"];
+v["U100","14"]=v["Vcc"];
+v["U100","4"]=v["SING_N"];
+v["U100","5"]=v["SING_N"];
+v["U100","10"]=v["SING_N"];
+v["U100","8"]=v["SING_N"];
+v["U100","9"]=v["SING_N"];
+v["U100","6"]=v["SING_N"];
+nodeEquations={
+i["U100","1"]+i["U100","3"]==0,
+i["U100","14"]==0,
+i["U100","4"]+i["U100","5"]+i["U100","10"]+i["U100","8"]+i["U100","9"]+i["U100","6"]==0};
+modelEquations={
+7400[value->u100]["U100"]};
+variables={
+v["SING_N_2"],
+v["Vcc"],
+v["SING_N"],
+i["U100","1"],
+i["U100","3"],
+i["U100","7"],
+i["U100","14"],
+i["U100","4"],
+i["U100","5"],
+i["U100","10"],
+i["U100","8"],
+i["U100","9"],
+i["U100","6"]};
diff --git a/gnetlist/tests/common/outputs/mathematica/singlenet.retcode b/gnetlist/tests/common/outputs/mathematica/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/mathematica/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/.gitignore b/gnetlist/tests/common/outputs/maxascii/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/maxascii/JD-output.net b/gnetlist/tests/common/outputs/maxascii/JD-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/JD.retcode b/gnetlist/tests/common/outputs/maxascii/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include.retcode b/gnetlist/tests/common/outputs/maxascii/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort.retcode b/gnetlist/tests/common/outputs/maxascii/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net b/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net
new file mode 100644
index 0000000..b98bead
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/JD_nomunge-output.net
@@ -0,0 +1,27 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP Cm	"unknown"
+*COMP A1	"unknown"
+*COMP Rt	"unknown"
+*COMP M1	"unknown"
+*COMP X1	"unknown"
+*COMP Rlp	"unknown"
+*COMP Vdd	"none"
+*COMP Rlm	"unknown"
+*COMP Cp	"unknown"
+*COMP Rb	"unknown"
+*NET "Vdd1"
+*NET "Vdd1" Rlp."2" M1."B" M1."S" Vdd."1" X1."6"
+*NET "GND"
+*NET "GND" Cm."2" Cp."2" Rlm."2" Vdd."2" V1."2" Rb."1" X1."7" X1."2"
+*NET "LVH"
+*NET "LVH" Rb."2" M1."D" M1."G" X1."3"
+*NET "i"
+*NET "i" V1."1" X1."1"
+*NET "p"
+*NET "p" Cp."1" Rt."1" Rlp."1" X1."5"
+*NET "m"
+*NET "m" Cm."1" Rlm."1" Rt."2" X1."4"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/Makefile.am b/gnetlist/tests/common/outputs/maxascii/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/maxascii/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/maxascii/SlottedOpamps-output.net
new file mode 100644
index 0000000..2383c2e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/SlottedOpamps-output.net
@@ -0,0 +1,23 @@
+*OrCAD
+*START
+*COMP U1	"unknown"
+*NET "minusin_slot4_pin13_b"
+*NET "minusin_slot4_pin13_b" U1."13"
+*NET "plusin_slot4_pin12_a"
+*NET "plusin_slot4_pin12_a" U1."12"
+*NET "minusin_slot3_pin_b"
+*NET "minusin_slot3_pin_b" U1."9"
+*NET "plusin_slot3_pin10_a"
+*NET "plusin_slot3_pin10_a" U1."10"
+*NET "minusin_slot2_pin6_b"
+*NET "minusin_slot2_pin6_b" U1."6"
+*NET "plusin_slot2_pin5_a"
+*NET "plusin_slot2_pin5_a" U1."5"
+*NET "samenet_output_c"
+*NET "samenet_output_c" U1."14" U1."8" U1."7" U1."1"
+*NET "minusin_slot1_pin_b"
+*NET "minusin_slot1_pin_b" U1."2"
+*NET "plusin_slot1_pin3_a"
+*NET "plusin_slot1_pin3_a" U1."3"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/maxascii/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net
new file mode 100644
index 0000000..2a0eb09
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp-output.net
@@ -0,0 +1,51 @@
+*OrCAD
+*START
+*COMP Cout	"unknown"
+*COMP R5	"unknown"
+*COMP R4	"unknown"
+*COMP RE2	"unknown"
+*COMP Q2	"unknown"
+*COMP A3	"unknown"
+*COMP R3	"unknown"
+*COMP A2	"unknown"
+*COMP RE1	"unknown"
+*COMP Q1	"unknown"
+*COMP A1	"unknown"
+*COMP R2	"unknown"
+*COMP Vinput	"none"
+*COMP R1	"unknown"
+*COMP C2	"unknown"
+*COMP CE2	"unknown"
+*COMP C1	"unknown"
+*COMP CE1	"unknown"
+*COMP R8	"unknown"
+*COMP VCC	"none"
+*COMP RC2	"unknown"
+*COMP RC1	"unknown"
+*COMP RL	"unknown"
+*NET "unnamed_net2"
+*NET "unnamed_net2" C2."1" R8."2"
+*NET "Vbase2"
+*NET "Vbase2" R3."1" C2."2" R4."2" Q2."2"
+*NET "Vem2"
+*NET "Vem2" CE2."2" RE2."2" Q2."1"
+*NET "Vout"
+*NET "Vout" Cout."2" RL."2"
+*NET "VColl2"
+*NET "VColl2" Q2."3" Cout."1" RC2."1"
+*NET "GND"
+*NET "GND" R4."1" CE2."1" RE2."1" VCC."2" Vinput."2" CE1."1" RL."1" RE1."1" R2."1"
+*NET "Vcc"
+*NET "Vcc" R3."2" RC1."2" VCC."1" RC2."2" R1."2"
+*NET "Vin"
+*NET "Vin" Vinput."1" R5."1"
+*NET "unnamed_net1"
+*NET "unnamed_net1" C1."1" R5."2"
+*NET "Vbase1"
+*NET "Vbase1" C1."2" R2."2" R1."1" Q1."2"
+*NET "Vem1"
+*NET "Vem1" CE1."2" RE1."2" Q1."1"
+*NET "Vcoll1"
+*NET "Vcoll1" R8."1" RC1."1" Q1."3"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..2a0eb09
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include-output.net
@@ -0,0 +1,51 @@
+*OrCAD
+*START
+*COMP Cout	"unknown"
+*COMP R5	"unknown"
+*COMP R4	"unknown"
+*COMP RE2	"unknown"
+*COMP Q2	"unknown"
+*COMP A3	"unknown"
+*COMP R3	"unknown"
+*COMP A2	"unknown"
+*COMP RE1	"unknown"
+*COMP Q1	"unknown"
+*COMP A1	"unknown"
+*COMP R2	"unknown"
+*COMP Vinput	"none"
+*COMP R1	"unknown"
+*COMP C2	"unknown"
+*COMP CE2	"unknown"
+*COMP C1	"unknown"
+*COMP CE1	"unknown"
+*COMP R8	"unknown"
+*COMP VCC	"none"
+*COMP RC2	"unknown"
+*COMP RC1	"unknown"
+*COMP RL	"unknown"
+*NET "unnamed_net2"
+*NET "unnamed_net2" C2."1" R8."2"
+*NET "Vbase2"
+*NET "Vbase2" R3."1" C2."2" R4."2" Q2."2"
+*NET "Vem2"
+*NET "Vem2" CE2."2" RE2."2" Q2."1"
+*NET "Vout"
+*NET "Vout" Cout."2" RL."2"
+*NET "VColl2"
+*NET "VColl2" Q2."3" Cout."1" RC2."1"
+*NET "GND"
+*NET "GND" R4."1" CE2."1" RE2."1" VCC."2" Vinput."2" CE1."1" RL."1" RE1."1" R2."1"
+*NET "Vcc"
+*NET "Vcc" R3."2" RC1."2" VCC."1" RC2."2" R1."2"
+*NET "Vin"
+*NET "Vin" Vinput."1" R5."1"
+*NET "unnamed_net1"
+*NET "unnamed_net1" C1."1" R5."2"
+*NET "Vbase1"
+*NET "Vbase1" C1."2" R2."2" R1."1" Q1."2"
+*NET "Vem1"
+*NET "Vem1" CE1."2" RE1."2" Q1."1"
+*NET "Vcoll1"
+*NET "Vcoll1" R8."1" RC1."1" Q1."3"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..2a0eb09
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort-output.net
@@ -0,0 +1,51 @@
+*OrCAD
+*START
+*COMP Cout	"unknown"
+*COMP R5	"unknown"
+*COMP R4	"unknown"
+*COMP RE2	"unknown"
+*COMP Q2	"unknown"
+*COMP A3	"unknown"
+*COMP R3	"unknown"
+*COMP A2	"unknown"
+*COMP RE1	"unknown"
+*COMP Q1	"unknown"
+*COMP A1	"unknown"
+*COMP R2	"unknown"
+*COMP Vinput	"none"
+*COMP R1	"unknown"
+*COMP C2	"unknown"
+*COMP CE2	"unknown"
+*COMP C1	"unknown"
+*COMP CE1	"unknown"
+*COMP R8	"unknown"
+*COMP VCC	"none"
+*COMP RC2	"unknown"
+*COMP RC1	"unknown"
+*COMP RL	"unknown"
+*NET "unnamed_net2"
+*NET "unnamed_net2" C2."1" R8."2"
+*NET "Vbase2"
+*NET "Vbase2" R3."1" C2."2" R4."2" Q2."2"
+*NET "Vem2"
+*NET "Vem2" CE2."2" RE2."2" Q2."1"
+*NET "Vout"
+*NET "Vout" Cout."2" RL."2"
+*NET "VColl2"
+*NET "VColl2" Q2."3" Cout."1" RC2."1"
+*NET "GND"
+*NET "GND" R4."1" CE2."1" RE2."1" VCC."2" Vinput."2" CE1."1" RL."1" RE1."1" R2."1"
+*NET "Vcc"
+*NET "Vcc" R3."2" RC1."2" VCC."1" RC2."2" R1."2"
+*NET "Vin"
+*NET "Vin" Vinput."1" R5."1"
+*NET "unnamed_net1"
+*NET "unnamed_net1" C1."1" R5."2"
+*NET "Vbase1"
+*NET "Vbase1" C1."2" R2."2" R1."1" Q1."2"
+*NET "Vem1"
+*NET "Vem1" CE1."2" RE1."2" Q1."1"
+*NET "Vcoll1"
+*NET "Vcoll1" R8."1" RC1."1" Q1."3"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/cascade-output.net b/gnetlist/tests/common/outputs/maxascii/cascade-output.net
new file mode 100644
index 0000000..626660d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/cascade-output.net
@@ -0,0 +1,26 @@
+*OrCAD
+*START
+*COMP AMP2	"none"
+*COMP AMP1	"none"
+*COMP SOURCE	"none"
+*COMP DEFAULTS	"unknown"
+*COMP MX1	"none"
+*COMP DEF1	"none"
+*COMP T1	"none"
+*COMP FL1	"none"
+*NET "unnamed_net6"
+*NET "unnamed_net6" AMP2."1" T1."2"
+*NET "unnamed_net5"
+*NET "unnamed_net5" T1."1" MX1."2"
+*NET "unnamed_net4"
+*NET "unnamed_net4" MX1."1" FL1."2"
+*NET "unnamed_net3"
+*NET "unnamed_net3" FL1."1" DEF1."2"
+*NET "unnamed_net2"
+*NET "unnamed_net2" DEF1."1" AMP1."2"
+*NET "unnamed_net1"
+*NET "unnamed_net1" AMP1."1" SOURCE."1"
+*NET "GND"
+*NET "GND" DEFAULTS."1"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/cascade.retcode b/gnetlist/tests/common/outputs/maxascii/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/multiequal-output.net b/gnetlist/tests/common/outputs/maxascii/multiequal-output.net
new file mode 100644
index 0000000..5e0d9f7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/multiequal-output.net
@@ -0,0 +1,11 @@
+*OrCAD
+*START
+*COMP V1	"none"
+*COMP A1	"unknown"
+*COMP R1	"unknown"
+*NET "GND"
+*NET "GND" V1."2" R1."1"
+*NET "unnamed_net1"
+*NET "unnamed_net1" V1."1" R1."2"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/multiequal.retcode b/gnetlist/tests/common/outputs/maxascii/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/netattrib-output.net b/gnetlist/tests/common/outputs/maxascii/netattrib-output.net
new file mode 100644
index 0000000..e5bfeb3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/netattrib-output.net
@@ -0,0 +1,18 @@
+*OrCAD
+*START
+*COMP F1	"unknown"
+*COMP U100	"DIP14"
+*COMP U300	"DIP14"
+*COMP U200	"DIP14"
+*NET "unnamed_net1"
+*NET "unnamed_net1" U300."2"
+*NET "netattrib"
+*NET "netattrib" U200."2" U100."5"
+*NET "GND"
+*NET "GND" U300."7" U200."7" U100."7"
+*NET "Vcc"
+*NET "Vcc" U300."14" U200."14" U100."14"
+*NET "one"
+*NET "one" F1."1" U300."1" U200."1" U100."3"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/netattrib.retcode b/gnetlist/tests/common/outputs/maxascii/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/powersupply-output.net b/gnetlist/tests/common/outputs/maxascii/powersupply-output.net
new file mode 100644
index 0000000..dd9b9bd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/powersupply-output.net
@@ -0,0 +1,38 @@
+*OrCAD
+*START
+*COMP F1	"unknown"
+*COMP R2	"unknown"
+*COMP CONN1	"unknown"
+*COMP C4	"unknown"
+*COMP R1	"unknown"
+*COMP C3	"unknown"
+*COMP C2	"unknown"
+*COMP S1	"unknown"
+*COMP C1	"unknown"
+*COMP T1	"unknown"
+*COMP U2	"unknown"
+*COMP U1	"unknown"
+*NET "ten"
+*NET "ten" U2."1" R1."2" C3."1" R2."1"
+*NET "eleven"
+*NET "eleven" U2."2" C4."1" R2."2"
+*NET "GND"
+*NET "GND" CONN1."3"
+*NET "one"
+*NET "one" S1."1" CONN1."1"
+*NET "five"
+*NET "five" CONN1."2" T1."2"
+*NET "three"
+*NET "three" T1."1" F1."2"
+*NET "two"
+*NET "two" S1."2" F1."1"
+*NET "six"
+*NET "six" T1."3" U1."4"
+*NET "seven"
+*NET "seven" T1."4" U1."3"
+*NET "nine"
+*NET "nine" C4."2" C3."2" R1."3" R1."1" C2."2" C1."2" U1."2"
+*NET "eight"
+*NET "eight" U2."3" C2."1" C1."1" U1."1"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/powersupply.retcode b/gnetlist/tests/common/outputs/maxascii/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/maxascii/singlenet-output.net b/gnetlist/tests/common/outputs/maxascii/singlenet-output.net
new file mode 100644
index 0000000..b6d7f82
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/singlenet-output.net
@@ -0,0 +1,13 @@
+*OrCAD
+*START
+*COMP U100	"DIP14"
+*NET "SING_N_2"
+*NET "SING_N_2" U100."1" U100."3"
+*NET "GND"
+*NET "GND" U100."7"
+*NET "Vcc"
+*NET "Vcc" U100."14"
+*NET "SING_N"
+*NET "SING_N" U100."4" U100."5" U100."10" U100."8" U100."9" U100."6"
+
+*END
diff --git a/gnetlist/tests/common/outputs/maxascii/singlenet.retcode b/gnetlist/tests/common/outputs/maxascii/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/maxascii/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/.gitignore b/gnetlist/tests/common/outputs/osmond/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/osmond/JD-output.net b/gnetlist/tests/common/outputs/osmond/JD-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/JD.retcode b/gnetlist/tests/common/outputs/osmond/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include-output.net b/gnetlist/tests/common/outputs/osmond/JD_Include-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include.retcode b/gnetlist/tests/common/outputs/osmond/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net b/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort.retcode b/gnetlist/tests/common/outputs/osmond/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net b/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net
new file mode 100644
index 0000000..36c7463
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/JD_nomunge-output.net
@@ -0,0 +1,23 @@
+Part none { Name V1 }
+Part unknown { Name Cm }
+Part unknown { Name A1 }
+Part unknown { Name Rt }
+Part unknown { Name M1 }
+Part unknown { Name X1 }
+Part unknown { Name Rlp }
+Part none { Name Vdd }
+Part unknown { Name Rlm }
+Part unknown { Name Cp }
+Part unknown { Name Rb }
+Signal "Vdd1"
+  { Rlp-2 M1-B M1-S Vdd-1 X1-6 }
+Signal "GND"
+  { Cm-2 Cp-2 Rlm-2 Vdd-2 V1-2 Rb-1 X1-7 X1-2 }
+Signal "LVH"
+  { Rb-2 M1-D M1-G X1-3 }
+Signal "i"
+  { V1-1 X1-1 }
+Signal "p"
+  { Cp-1 Rt-1 Rlp-1 X1-5 }
+Signal "m"
+  { Cm-1 Rlm-1 Rt-2 X1-4 }
diff --git a/gnetlist/tests/common/outputs/osmond/Makefile.am b/gnetlist/tests/common/outputs/osmond/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/osmond/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/osmond/SlottedOpamps-output.net
new file mode 100644
index 0000000..de0769e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/SlottedOpamps-output.net
@@ -0,0 +1,19 @@
+Part unknown { Name U1 }
+Signal "minusin_slot4_pin13_b"
+  { U1-13 }
+Signal "plusin_slot4_pin12_a"
+  { U1-12 }
+Signal "minusin_slot3_pin_b"
+  { U1-9 }
+Signal "plusin_slot3_pin10_a"
+  { U1-10 }
+Signal "minusin_slot2_pin6_b"
+  { U1-6 }
+Signal "plusin_slot2_pin5_a"
+  { U1-5 }
+Signal "samenet_output_c"
+  { U1-14 U1-8 U1-7 U1-1 }
+Signal "minusin_slot1_pin_b"
+  { U1-2 }
+Signal "plusin_slot1_pin3_a"
+  { U1-3 }
diff --git a/gnetlist/tests/common/outputs/osmond/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/osmond/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net
new file mode 100644
index 0000000..a5ee1e7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp-output.net
@@ -0,0 +1,47 @@
+Part unknown { Name Cout }
+Part unknown { Name R5 }
+Part unknown { Name R4 }
+Part unknown { Name RE2 }
+Part unknown { Name Q2 }
+Part unknown { Name A3 }
+Part unknown { Name R3 }
+Part unknown { Name A2 }
+Part unknown { Name RE1 }
+Part unknown { Name Q1 }
+Part unknown { Name A1 }
+Part unknown { Name R2 }
+Part none { Name Vinput }
+Part unknown { Name R1 }
+Part unknown { Name C2 }
+Part unknown { Name CE2 }
+Part unknown { Name C1 }
+Part unknown { Name CE1 }
+Part unknown { Name R8 }
+Part none { Name VCC }
+Part unknown { Name RC2 }
+Part unknown { Name RC1 }
+Part unknown { Name RL }
+Signal "unnamed_net2"
+  { C2-1 R8-2 }
+Signal "Vbase2"
+  { R3-1 C2-2 R4-2 Q2-2 }
+Signal "Vem2"
+  { CE2-2 RE2-2 Q2-1 }
+Signal "Vout"
+  { Cout-2 RL-2 }
+Signal "VColl2"
+  { Q2-3 Cout-1 RC2-1 }
+Signal "GND"
+  { R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 }
+Signal "Vcc"
+  { R3-2 RC1-2 VCC-1 RC2-2 R1-2 }
+Signal "Vin"
+  { Vinput-1 R5-1 }
+Signal "unnamed_net1"
+  { C1-1 R5-2 }
+Signal "Vbase1"
+  { C1-2 R2-2 R1-1 Q1-2 }
+Signal "Vem1"
+  { CE1-2 RE1-2 Q1-1 }
+Signal "Vcoll1"
+  { R8-1 RC1-1 Q1-3 }
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/osmond/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..a5ee1e7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include-output.net
@@ -0,0 +1,47 @@
+Part unknown { Name Cout }
+Part unknown { Name R5 }
+Part unknown { Name R4 }
+Part unknown { Name RE2 }
+Part unknown { Name Q2 }
+Part unknown { Name A3 }
+Part unknown { Name R3 }
+Part unknown { Name A2 }
+Part unknown { Name RE1 }
+Part unknown { Name Q1 }
+Part unknown { Name A1 }
+Part unknown { Name R2 }
+Part none { Name Vinput }
+Part unknown { Name R1 }
+Part unknown { Name C2 }
+Part unknown { Name CE2 }
+Part unknown { Name C1 }
+Part unknown { Name CE1 }
+Part unknown { Name R8 }
+Part none { Name VCC }
+Part unknown { Name RC2 }
+Part unknown { Name RC1 }
+Part unknown { Name RL }
+Signal "unnamed_net2"
+  { C2-1 R8-2 }
+Signal "Vbase2"
+  { R3-1 C2-2 R4-2 Q2-2 }
+Signal "Vem2"
+  { CE2-2 RE2-2 Q2-1 }
+Signal "Vout"
+  { Cout-2 RL-2 }
+Signal "VColl2"
+  { Q2-3 Cout-1 RC2-1 }
+Signal "GND"
+  { R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 }
+Signal "Vcc"
+  { R3-2 RC1-2 VCC-1 RC2-2 R1-2 }
+Signal "Vin"
+  { Vinput-1 R5-1 }
+Signal "unnamed_net1"
+  { C1-1 R5-2 }
+Signal "Vbase1"
+  { C1-2 R2-2 R1-1 Q1-2 }
+Signal "Vem1"
+  { CE1-2 RE1-2 Q1-1 }
+Signal "Vcoll1"
+  { R8-1 RC1-1 Q1-3 }
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..a5ee1e7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort-output.net
@@ -0,0 +1,47 @@
+Part unknown { Name Cout }
+Part unknown { Name R5 }
+Part unknown { Name R4 }
+Part unknown { Name RE2 }
+Part unknown { Name Q2 }
+Part unknown { Name A3 }
+Part unknown { Name R3 }
+Part unknown { Name A2 }
+Part unknown { Name RE1 }
+Part unknown { Name Q1 }
+Part unknown { Name A1 }
+Part unknown { Name R2 }
+Part none { Name Vinput }
+Part unknown { Name R1 }
+Part unknown { Name C2 }
+Part unknown { Name CE2 }
+Part unknown { Name C1 }
+Part unknown { Name CE1 }
+Part unknown { Name R8 }
+Part none { Name VCC }
+Part unknown { Name RC2 }
+Part unknown { Name RC1 }
+Part unknown { Name RL }
+Signal "unnamed_net2"
+  { C2-1 R8-2 }
+Signal "Vbase2"
+  { R3-1 C2-2 R4-2 Q2-2 }
+Signal "Vem2"
+  { CE2-2 RE2-2 Q2-1 }
+Signal "Vout"
+  { Cout-2 RL-2 }
+Signal "VColl2"
+  { Q2-3 Cout-1 RC2-1 }
+Signal "GND"
+  { R4-1 CE2-1 RE2-1 VCC-2 Vinput-2 CE1-1 RL-1 RE1-1 R2-1 }
+Signal "Vcc"
+  { R3-2 RC1-2 VCC-1 RC2-2 R1-2 }
+Signal "Vin"
+  { Vinput-1 R5-1 }
+Signal "unnamed_net1"
+  { C1-1 R5-2 }
+Signal "Vbase1"
+  { C1-2 R2-2 R1-1 Q1-2 }
+Signal "Vem1"
+  { CE1-2 RE1-2 Q1-1 }
+Signal "Vcoll1"
+  { R8-1 RC1-1 Q1-3 }
diff --git a/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/cascade-output.net b/gnetlist/tests/common/outputs/osmond/cascade-output.net
new file mode 100644
index 0000000..e282543
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/cascade-output.net
@@ -0,0 +1,22 @@
+Part none { Name AMP2 }
+Part none { Name AMP1 }
+Part none { Name SOURCE }
+Part unknown { Name DEFAULTS }
+Part none { Name MX1 }
+Part none { Name DEF1 }
+Part none { Name T1 }
+Part none { Name FL1 }
+Signal "unnamed_net6"
+  { AMP2-1 T1-2 }
+Signal "unnamed_net5"
+  { T1-1 MX1-2 }
+Signal "unnamed_net4"
+  { MX1-1 FL1-2 }
+Signal "unnamed_net3"
+  { FL1-1 DEF1-2 }
+Signal "unnamed_net2"
+  { DEF1-1 AMP1-2 }
+Signal "unnamed_net1"
+  { AMP1-1 SOURCE-1 }
+Signal "GND"
+  { DEFAULTS-1 }
diff --git a/gnetlist/tests/common/outputs/osmond/cascade.retcode b/gnetlist/tests/common/outputs/osmond/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/multiequal-output.net b/gnetlist/tests/common/outputs/osmond/multiequal-output.net
new file mode 100644
index 0000000..f692926
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/multiequal-output.net
@@ -0,0 +1,7 @@
+Part none { Name V1 }
+Part unknown { Name A1 }
+Part unknown { Name R1 }
+Signal "GND"
+  { V1-2 R1-1 }
+Signal "unnamed_net1"
+  { V1-1 R1-2 }
diff --git a/gnetlist/tests/common/outputs/osmond/multiequal.retcode b/gnetlist/tests/common/outputs/osmond/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/netattrib-output.net b/gnetlist/tests/common/outputs/osmond/netattrib-output.net
new file mode 100644
index 0000000..5a73ae9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/netattrib-output.net
@@ -0,0 +1,14 @@
+Part unknown { Name F1 }
+Part DIP14 { Name U100 }
+Part DIP14 { Name U300 }
+Part DIP14 { Name U200 }
+Signal "unnamed_net1"
+  { U300-2 }
+Signal "netattrib"
+  { U200-2 U100-5 }
+Signal "GND"
+  { U300-7 U200-7 U100-7 }
+Signal "Vcc"
+  { U300-14 U200-14 U100-14 }
+Signal "one"
+  { F1-1 U300-1 U200-1 U100-3 }
diff --git a/gnetlist/tests/common/outputs/osmond/netattrib.retcode b/gnetlist/tests/common/outputs/osmond/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/powersupply-output.net b/gnetlist/tests/common/outputs/osmond/powersupply-output.net
new file mode 100644
index 0000000..aee49b2
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/powersupply-output.net
@@ -0,0 +1,34 @@
+Part unknown { Name F1 }
+Part unknown { Name R2 }
+Part unknown { Name CONN1 }
+Part unknown { Name C4 }
+Part unknown { Name R1 }
+Part unknown { Name C3 }
+Part unknown { Name C2 }
+Part unknown { Name S1 }
+Part unknown { Name C1 }
+Part unknown { Name T1 }
+Part unknown { Name U2 }
+Part unknown { Name U1 }
+Signal "ten"
+  { U2-1 R1-2 C3-1 R2-1 }
+Signal "eleven"
+  { U2-2 C4-1 R2-2 }
+Signal "GND"
+  { CONN1-3 }
+Signal "one"
+  { S1-1 CONN1-1 }
+Signal "five"
+  { CONN1-2 T1-2 }
+Signal "three"
+  { T1-1 F1-2 }
+Signal "two"
+  { S1-2 F1-1 }
+Signal "six"
+  { T1-3 U1-4 }
+Signal "seven"
+  { T1-4 U1-3 }
+Signal "nine"
+  { C4-2 C3-2 R1-3 R1-1 C2-2 C1-2 U1-2 }
+Signal "eight"
+  { U2-3 C2-1 C1-1 U1-1 }
diff --git a/gnetlist/tests/common/outputs/osmond/powersupply.retcode b/gnetlist/tests/common/outputs/osmond/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/osmond/singlenet-output.net b/gnetlist/tests/common/outputs/osmond/singlenet-output.net
new file mode 100644
index 0000000..f802d7f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/singlenet-output.net
@@ -0,0 +1,9 @@
+Part DIP14 { Name U100 }
+Signal "SING_N_2"
+  { U100-1 U100-3 }
+Signal "GND"
+  { U100-7 }
+Signal "Vcc"
+  { U100-14 }
+Signal "SING_N"
+  { U100-4 U100-5 U100-10 U100-8 U100-9 U100-6 }
diff --git a/gnetlist/tests/common/outputs/osmond/singlenet.retcode b/gnetlist/tests/common/outputs/osmond/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/osmond/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/.gitignore b/gnetlist/tests/common/outputs/pads/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/pads/JD-output.net b/gnetlist/tests/common/outputs/pads/JD-output.net
new file mode 100644
index 0000000..f3a5213
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD.retcode b/gnetlist/tests/common/outputs/pads/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include-output.net b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
new file mode 100644
index 0000000..f3a5213
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Include-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include.retcode b/gnetlist/tests/common/outputs/pads/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..f3a5213
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
new file mode 100644
index 0000000..f3a5213
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort.retcode b/gnetlist/tests/common/outputs/pads/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..f3a5213
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net b/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net
new file mode 100644
index 0000000..c4fc30c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/JD_nomunge-output.net
@@ -0,0 +1,30 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+CM	unknown
+A1	unknown
+RT	unknown
+M1	unknown
+X1	unknown
+RLP	unknown
+VDD	none
+RLM	unknown
+CP	unknown
+RB	unknown
+
+*NET*
+*SIGNAL* VDD1
+ RLP.2 M1.B M1.S VDD.1 X1.6
+*SIGNAL* GND
+ CM.2 CP.2 RLM.2 VDD.2 V1.2 RB.1 X1.7 X1.2
+*SIGNAL* LVH
+ RB.2 M1.D M1.G X1.3
+*SIGNAL* I
+ V1.1 X1.1
+*SIGNAL* P
+ CP.1 RT.1 RLP.1 X1.5
+*SIGNAL* M
+ CM.1 RLM.1 RT.2 X1.4
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/Makefile.am b/gnetlist/tests/common/outputs/pads/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
new file mode 100644
index 0000000..2031be3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/SlottedOpamps-output.net
@@ -0,0 +1,26 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U1	unknown
+
+*NET*
+*SIGNAL* MINUSIN_SLOT4_PIN13_B
+ U1.13
+*SIGNAL* PLUSIN_SLOT4_PIN12_A
+ U1.12
+*SIGNAL* MINUSIN_SLOT3_PIN_B
+ U1.9
+*SIGNAL* PLUSIN_SLOT3_PIN10_A
+ U1.10
+*SIGNAL* MINUSIN_SLOT2_PIN6_B
+ U1.6
+*SIGNAL* PLUSIN_SLOT2_PIN5_A
+ U1.5
+*SIGNAL* SAMENET_OUTPUT_C
+ U1.14 U1.8 U1.7 U1.1
+*SIGNAL* MINUSIN_SLOT1_PIN_B
+ U1.2
+*SIGNAL* PLUSIN_SLOT1_PIN3_A
+ U1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/pads/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
new file mode 100644
index 0000000..f443d47
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp-output.net
@@ -0,0 +1,54 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/pads/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..f443d47
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include-output.net
@@ -0,0 +1,54 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..f443d47
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort-output.net
@@ -0,0 +1,54 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+COUT	unknown
+R5	unknown
+R4	unknown
+RE2	unknown
+Q2	unknown
+A3	unknown
+R3	unknown
+A2	unknown
+RE1	unknown
+Q1	unknown
+A1	unknown
+R2	unknown
+VINPUT	none
+R1	unknown
+C2	unknown
+CE2	unknown
+C1	unknown
+CE1	unknown
+R8	unknown
+VCC	none
+RC2	unknown
+RC1	unknown
+RL	unknown
+
+*NET*
+*SIGNAL* UNNAMED_NET2
+ C2.1 R8.2
+*SIGNAL* VBASE2
+ R3.1 C2.2 R4.2 Q2.2
+*SIGNAL* VEM2
+ CE2.2 RE2.2 Q2.1
+*SIGNAL* VOUT
+ COUT.2 RL.2
+*SIGNAL* VCOLL2
+ Q2.3 COUT.1 RC2.1
+*SIGNAL* GND
+ R4.1 CE2.1 RE2.1 VCC.2 VINPUT.2 CE1.1 RL.1 RE1.1 R2.1
+*SIGNAL* VCC
+ R3.2 RC1.2 VCC.1 RC2.2 R1.2
+*SIGNAL* VIN
+ VINPUT.1 R5.1
+*SIGNAL* UNNAMED_NET1
+ C1.1 R5.2
+*SIGNAL* VBASE1
+ C1.2 R2.2 R1.1 Q1.2
+*SIGNAL* VEM1
+ CE1.2 RE1.2 Q1.1
+*SIGNAL* VCOLL1
+ R8.1 RC1.1 Q1.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/cascade-output.net b/gnetlist/tests/common/outputs/pads/cascade-output.net
new file mode 100644
index 0000000..52c4cd5
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/cascade-output.net
@@ -0,0 +1,29 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+AMP2	none
+AMP1	none
+SOURCE	none
+DEFAULTS	unknown
+MX1	none
+DEF1	none
+T1	none
+FL1	none
+
+*NET*
+*SIGNAL* UNNAMED_NET6
+ AMP2.1 T1.2
+*SIGNAL* UNNAMED_NET5
+ T1.1 MX1.2
+*SIGNAL* UNNAMED_NET4
+ MX1.1 FL1.2
+*SIGNAL* UNNAMED_NET3
+ FL1.1 DEF1.2
+*SIGNAL* UNNAMED_NET2
+ DEF1.1 AMP1.2
+*SIGNAL* UNNAMED_NET1
+ AMP1.1 SOURCE.1
+*SIGNAL* GND
+ DEFAULTS.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/cascade.retcode b/gnetlist/tests/common/outputs/pads/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/multiequal-output.net b/gnetlist/tests/common/outputs/pads/multiequal-output.net
new file mode 100644
index 0000000..d325973
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/multiequal-output.net
@@ -0,0 +1,14 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+V1	none
+A1	unknown
+R1	unknown
+
+*NET*
+*SIGNAL* GND
+ V1.2 R1.1
+*SIGNAL* UNNAMED_NET1
+ V1.1 R1.2
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/multiequal.retcode b/gnetlist/tests/common/outputs/pads/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/netattrib-output.net b/gnetlist/tests/common/outputs/pads/netattrib-output.net
new file mode 100644
index 0000000..332cf53
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/netattrib-output.net
@@ -0,0 +1,21 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+U100	DIP14
+U300	DIP14
+U200	DIP14
+
+*NET*
+*SIGNAL* UNNAMED_NET1
+ U300.2
+*SIGNAL* NETATTRIB
+ U200.2 U100.5
+*SIGNAL* GND
+ U300.7 U200.7 U100.7
+*SIGNAL* VCC
+ U300.14 U200.14 U100.14
+*SIGNAL* ONE
+ F1.1 U300.1 U200.1 U100.3
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/netattrib.retcode b/gnetlist/tests/common/outputs/pads/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/powersupply-output.net b/gnetlist/tests/common/outputs/pads/powersupply-output.net
new file mode 100644
index 0000000..3aa5cd9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/powersupply-output.net
@@ -0,0 +1,41 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+F1	unknown
+R2	unknown
+CONN1	unknown
+C4	unknown
+R1	unknown
+C3	unknown
+C2	unknown
+S1	unknown
+C1	unknown
+T1	unknown
+U2	unknown
+U1	unknown
+
+*NET*
+*SIGNAL* TEN
+ U2.1 R1.2 C3.1 R2.1
+*SIGNAL* ELEVEN
+ U2.2 C4.1 R2.2
+*SIGNAL* GND
+ CONN1.3
+*SIGNAL* ONE
+ S1.1 CONN1.1
+*SIGNAL* FIVE
+ CONN1.2 T1.2
+*SIGNAL* THREE
+ T1.1 F1.2
+*SIGNAL* TWO
+ S1.2 F1.1
+*SIGNAL* SIX
+ T1.3 U1.4
+*SIGNAL* SEVEN
+ T1.4 U1.3
+*SIGNAL* NINE
+ C4.2 C3.2 R1.3 R1.1 C2.2 C1.2 U1.2
+*SIGNAL* EIGHT
+ U2.3 C2.1 C1.1 U1.1
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/powersupply.retcode b/gnetlist/tests/common/outputs/pads/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pads/singlenet-output.net b/gnetlist/tests/common/outputs/pads/singlenet-output.net
new file mode 100644
index 0000000..db44a14
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/singlenet-output.net
@@ -0,0 +1,16 @@
+!PADS-POWERPCB-V3.0-MILS!
+
+*PART*
+U100	DIP14
+
+*NET*
+*SIGNAL* SING_N_2
+ U100.1 U100.3
+*SIGNAL* GND
+ U100.7
+*SIGNAL* VCC
+ U100.14
+*SIGNAL* SING_N
+ U100.4 U100.5 U100.10 U100.8 U100.9 U100.6
+
+*END*
diff --git a/gnetlist/tests/common/outputs/pads/singlenet.retcode b/gnetlist/tests/common/outputs/pads/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pads/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/.gitignore b/gnetlist/tests/common/outputs/partslist1/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/partslist1/JD-output.net b/gnetlist/tests/common/outputs/partslist1/JD-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/JD.retcode b/gnetlist/tests/common/outputs/partslist1/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Include-output.net b/gnetlist/tests/common/outputs/partslist1/JD_Include-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Include-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Include.retcode b/gnetlist/tests/common/outputs/partslist1/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Sort-output.net b/gnetlist/tests/common/outputs/partslist1/JD_Sort-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Sort-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Sort.retcode b/gnetlist/tests/common/outputs/partslist1/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/JD_nomunge-output.net b/gnetlist/tests/common/outputs/partslist1/JD_nomunge-output.net
new file mode 100644
index 0000000..eb4ccbd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/JD_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rt	RESISTOR	1k	unknown	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+X1	LVD	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/Makefile.am b/gnetlist/tests/common/outputs/partslist1/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/partslist1/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/partslist1/SlottedOpamps-output.net
new file mode 100644
index 0000000..c359e1a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/SlottedOpamps-output.net
@@ -0,0 +1,4 @@
+.START
+..refdes	device	value	footprint	quantity
+U1	LM324	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/partslist1/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp-output.net
new file mode 100644
index 0000000..fd26fe0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R1	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R5	RESISTOR	10	unknown	1
+R8	RESISTOR	1	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..fd26fe0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R1	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R5	RESISTOR	10	unknown	1
+R8	RESISTOR	1	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..fd26fe0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	model	unknown	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R1	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R5	RESISTOR	10	unknown	1
+R8	RESISTOR	1	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/cascade-output.net b/gnetlist/tests/common/outputs/partslist1/cascade-output.net
new file mode 100644
index 0000000..6df12ff
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/cascade-output.net
@@ -0,0 +1,11 @@
+.START
+..refdes	device	value	footprint	quantity
+AMP1	cascade-amp	unknown	none	1
+AMP2	cascade-amp	unknown	none	1
+DEF1	cascade-defaults	unknown	none	1
+DEFAULTS	cascade-defaults-top	unknown	unknown	1
+FL1	cascade-filter	unknown	none	1
+MX1	cascade-mixer	unknown	none	1
+SOURCE	cascade-source	unknown	none	1
+T1	cascade-transformer	unknown	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/cascade.retcode b/gnetlist/tests/common/outputs/partslist1/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/multiequal-output.net b/gnetlist/tests/common/outputs/partslist1/multiequal-output.net
new file mode 100644
index 0000000..c444b03
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/multiequal-output.net
@@ -0,0 +1,6 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	options	abotol=1e-11	unknown	1
+R1	RESISTOR	20	unknown	1
+V1	VOLTAGE_SOURCE	DC 1V	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/multiequal.retcode b/gnetlist/tests/common/outputs/partslist1/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/netattrib-output.net b/gnetlist/tests/common/outputs/partslist1/netattrib-output.net
new file mode 100644
index 0000000..5793b52
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/netattrib-output.net
@@ -0,0 +1,7 @@
+.START
+..refdes	device	value	footprint	quantity
+F1	FUSE	unknown	unknown	1
+U100	7400	unknown	DIP14	1
+U200	7404	unknown	DIP14	1
+U300	7404	unknown	DIP14	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/netattrib.retcode b/gnetlist/tests/common/outputs/partslist1/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/powersupply-output.net b/gnetlist/tests/common/outputs/partslist1/powersupply-output.net
new file mode 100644
index 0000000..48545b9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/powersupply-output.net
@@ -0,0 +1,15 @@
+.START
+..refdes	device	value	footprint	quantity
+C1	POLARIZED_CAPACITOR	2200uF	unknown	1
+C2	POLARIZED_CAPACITOR	0.1uF	unknown	1
+C3	POLARIZED_CAPACITOR	22uF	unknown	1
+C4	POLARIZED_CAPACITOR	1uf	unknown	1
+CONN1	MAINS_CONNECTOR	unknown	unknown	1
+F1	FUSE	unknown	unknown	1
+R1	VARIABLE_RESISTOR	5k	unknown	1
+R2	RESISTOR	220	unknown	1
+S1	SPST	unknown	unknown	1
+T1	transformer	unknown	unknown	1
+U1	DIODE-BRIDGE	unknown	unknown	1
+U2	LM317	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/powersupply.retcode b/gnetlist/tests/common/outputs/partslist1/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist1/singlenet-output.net b/gnetlist/tests/common/outputs/partslist1/singlenet-output.net
new file mode 100644
index 0000000..68fac3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/singlenet-output.net
@@ -0,0 +1,4 @@
+.START
+..refdes	device	value	footprint	quantity
+U100	7400	unknown	DIP14	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist1/singlenet.retcode b/gnetlist/tests/common/outputs/partslist1/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist1/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/.gitignore b/gnetlist/tests/common/outputs/partslist2/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/partslist2/JD-output.net b/gnetlist/tests/common/outputs/partslist2/JD-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/JD.retcode b/gnetlist/tests/common/outputs/partslist2/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Include-output.net b/gnetlist/tests/common/outputs/partslist2/JD_Include-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Include-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Include.retcode b/gnetlist/tests/common/outputs/partslist2/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Sort-output.net b/gnetlist/tests/common/outputs/partslist2/JD_Sort-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Sort-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Sort.retcode b/gnetlist/tests/common/outputs/partslist2/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/JD_nomunge-output.net b/gnetlist/tests/common/outputs/partslist2/JD_nomunge-output.net
new file mode 100644
index 0000000..351af79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/JD_nomunge-output.net
@@ -0,0 +1,14 @@
+.START
+..refdes	device	value	footprint	quantity
+Cm	CAPACITOR	20p	unknown	1
+Cp	CAPACITOR	20p	unknown	1
+X1	LVD	unknown	unknown	1
+A1	model	unknown	unknown	1
+M1	PMOS_TRANSISTOR	unknown	unknown	1
+Rt	RESISTOR	1k	unknown	1
+Rlp	RESISTOR	1meg	unknown	1
+Rb	RESISTOR	5.6k	unknown	1
+Rlm	RESISTOR	500k	unknown	1
+Vdd	VOLTAGE_SOURCE	DC 3.3V	none	1
+V1	vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/Makefile.am b/gnetlist/tests/common/outputs/partslist2/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/partslist2/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/partslist2/SlottedOpamps-output.net
new file mode 100644
index 0000000..c359e1a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/SlottedOpamps-output.net
@@ -0,0 +1,4 @@
+.START
+..refdes	device	value	footprint	quantity
+U1	LM324	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/partslist2/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp-output.net
new file mode 100644
index 0000000..d778c08
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+A1	model	unknown	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R8	RESISTOR	1	unknown	1
+R5	RESISTOR	10	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R1	RESISTOR	28K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..d778c08
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+A1	model	unknown	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R8	RESISTOR	1	unknown	1
+R5	RESISTOR	10	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R1	RESISTOR	28K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..d778c08
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort-output.net
@@ -0,0 +1,25 @@
+.START
+..refdes	device	value	footprint	quantity
+CE1	CAPACITOR	1pF	unknown	1
+CE2	CAPACITOR	1pF	unknown	1
+C1	CAPACITOR	2.2uF	unknown	1
+C2	CAPACITOR	2.2uF	unknown	1
+Cout	CAPACITOR	2.2uF	unknown	1
+A3	directive	.options TEMP=25	unknown	1
+A1	model	unknown	unknown	1
+Q1	NPN_TRANSISTOR	unknown	unknown	1
+Q2	NPN_TRANSISTOR	unknown	unknown	1
+R8	RESISTOR	1	unknown	1
+R5	RESISTOR	10	unknown	1
+RE1	RESISTOR	100	unknown	1
+RE2	RESISTOR	100	unknown	1
+RL	RESISTOR	100K	unknown	1
+RC2	RESISTOR	1K	unknown	1
+R4	RESISTOR	2.8K	unknown	1
+R1	RESISTOR	28K	unknown	1
+R3	RESISTOR	28K	unknown	1
+R2	RESISTOR	2K	unknown	1
+RC1	RESISTOR	3.3K	unknown	1
+VCC	VOLTAGE_SOURCE	DC 15V	none	1
+Vinput	vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/cascade-output.net b/gnetlist/tests/common/outputs/partslist2/cascade-output.net
new file mode 100644
index 0000000..6df12ff
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/cascade-output.net
@@ -0,0 +1,11 @@
+.START
+..refdes	device	value	footprint	quantity
+AMP1	cascade-amp	unknown	none	1
+AMP2	cascade-amp	unknown	none	1
+DEF1	cascade-defaults	unknown	none	1
+DEFAULTS	cascade-defaults-top	unknown	unknown	1
+FL1	cascade-filter	unknown	none	1
+MX1	cascade-mixer	unknown	none	1
+SOURCE	cascade-source	unknown	none	1
+T1	cascade-transformer	unknown	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/cascade.retcode b/gnetlist/tests/common/outputs/partslist2/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/multiequal-output.net b/gnetlist/tests/common/outputs/partslist2/multiequal-output.net
new file mode 100644
index 0000000..c444b03
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/multiequal-output.net
@@ -0,0 +1,6 @@
+.START
+..refdes	device	value	footprint	quantity
+A1	options	abotol=1e-11	unknown	1
+R1	RESISTOR	20	unknown	1
+V1	VOLTAGE_SOURCE	DC 1V	none	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/multiequal.retcode b/gnetlist/tests/common/outputs/partslist2/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/netattrib-output.net b/gnetlist/tests/common/outputs/partslist2/netattrib-output.net
new file mode 100644
index 0000000..a73db1b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/netattrib-output.net
@@ -0,0 +1,7 @@
+.START
+..refdes	device	value	footprint	quantity
+U100	7400	unknown	DIP14	1
+U200	7404	unknown	DIP14	1
+U300	7404	unknown	DIP14	1
+F1	FUSE	unknown	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/netattrib.retcode b/gnetlist/tests/common/outputs/partslist2/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/powersupply-output.net b/gnetlist/tests/common/outputs/partslist2/powersupply-output.net
new file mode 100644
index 0000000..84c2737
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/powersupply-output.net
@@ -0,0 +1,15 @@
+.START
+..refdes	device	value	footprint	quantity
+U1	DIODE-BRIDGE	unknown	unknown	1
+F1	FUSE	unknown	unknown	1
+U2	LM317	unknown	unknown	1
+CONN1	MAINS_CONNECTOR	unknown	unknown	1
+C2	POLARIZED_CAPACITOR	0.1uF	unknown	1
+C4	POLARIZED_CAPACITOR	1uf	unknown	1
+C1	POLARIZED_CAPACITOR	2200uF	unknown	1
+C3	POLARIZED_CAPACITOR	22uF	unknown	1
+R2	RESISTOR	220	unknown	1
+S1	SPST	unknown	unknown	1
+T1	transformer	unknown	unknown	1
+R1	VARIABLE_RESISTOR	5k	unknown	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/powersupply.retcode b/gnetlist/tests/common/outputs/partslist2/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist2/singlenet-output.net b/gnetlist/tests/common/outputs/partslist2/singlenet-output.net
new file mode 100644
index 0000000..68fac3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/singlenet-output.net
@@ -0,0 +1,4 @@
+.START
+..refdes	device	value	footprint	quantity
+U100	7400	unknown	DIP14	1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist2/singlenet.retcode b/gnetlist/tests/common/outputs/partslist2/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist2/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/.gitignore b/gnetlist/tests/common/outputs/partslist3/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/partslist3/JD-output.net b/gnetlist/tests/common/outputs/partslist3/JD-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/JD.retcode b/gnetlist/tests/common/outputs/partslist3/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Include-output.net b/gnetlist/tests/common/outputs/partslist3/JD_Include-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Include-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Include.retcode b/gnetlist/tests/common/outputs/partslist3/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Sort-output.net b/gnetlist/tests/common/outputs/partslist3/JD_Sort-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Sort-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Sort.retcode b/gnetlist/tests/common/outputs/partslist3/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/JD_nomunge-output.net b/gnetlist/tests/common/outputs/partslist3/JD_nomunge-output.net
new file mode 100644
index 0000000..2f7631f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/JD_nomunge-output.net
@@ -0,0 +1,13 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	20p	unknown	2	Cm Cp
+LVD	unknown	unknown	1	X1
+model	unknown	unknown	1	A1
+PMOS_TRANSISTOR	unknown	unknown	1	M1
+RESISTOR	1k	unknown	1	Rt
+RESISTOR	1meg	unknown	1	Rlp
+RESISTOR	5.6k	unknown	1	Rb
+RESISTOR	500k	unknown	1	Rlm
+VOLTAGE_SOURCE	DC 3.3V	none	1	Vdd
+vpulse	pulse 3.3 0 1u 10p 10p 1.25u 2.5u	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/Makefile.am b/gnetlist/tests/common/outputs/partslist3/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/partslist3/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/partslist3/SlottedOpamps-output.net
new file mode 100644
index 0000000..4c9802a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/SlottedOpamps-output.net
@@ -0,0 +1,4 @@
+.START
+..device	value	footprint	quantity	refdes
+LM324	unknown	unknown	1	U1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/partslist3/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp-output.net
new file mode 100644
index 0000000..dbe1e76
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp-output.net
@@ -0,0 +1,19 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	1pF	unknown	2	CE1 CE2
+CAPACITOR	2.2uF	unknown	3	C1 C2 Cout
+directive	.options TEMP=25	unknown	1	A3
+model	unknown	unknown	1	A1
+NPN_TRANSISTOR	unknown	unknown	2	Q1 Q2
+RESISTOR	1	unknown	1	R8
+RESISTOR	10	unknown	1	R5
+RESISTOR	100	unknown	2	RE1 RE2
+RESISTOR	100K	unknown	1	RL
+RESISTOR	1K	unknown	1	RC2
+RESISTOR	2.8K	unknown	1	R4
+RESISTOR	28K	unknown	2	R1 R3
+RESISTOR	2K	unknown	1	R2
+RESISTOR	3.3K	unknown	1	RC1
+VOLTAGE_SOURCE	DC 15V	none	1	VCC
+vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1	Vinput
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..dbe1e76
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include-output.net
@@ -0,0 +1,19 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	1pF	unknown	2	CE1 CE2
+CAPACITOR	2.2uF	unknown	3	C1 C2 Cout
+directive	.options TEMP=25	unknown	1	A3
+model	unknown	unknown	1	A1
+NPN_TRANSISTOR	unknown	unknown	2	Q1 Q2
+RESISTOR	1	unknown	1	R8
+RESISTOR	10	unknown	1	R5
+RESISTOR	100	unknown	2	RE1 RE2
+RESISTOR	100K	unknown	1	RL
+RESISTOR	1K	unknown	1	RC2
+RESISTOR	2.8K	unknown	1	R4
+RESISTOR	28K	unknown	2	R1 R3
+RESISTOR	2K	unknown	1	R2
+RESISTOR	3.3K	unknown	1	RC1
+VOLTAGE_SOURCE	DC 15V	none	1	VCC
+vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1	Vinput
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..dbe1e76
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort-output.net
@@ -0,0 +1,19 @@
+.START
+..device	value	footprint	quantity	refdes
+CAPACITOR	1pF	unknown	2	CE1 CE2
+CAPACITOR	2.2uF	unknown	3	C1 C2 Cout
+directive	.options TEMP=25	unknown	1	A3
+model	unknown	unknown	1	A1
+NPN_TRANSISTOR	unknown	unknown	2	Q1 Q2
+RESISTOR	1	unknown	1	R8
+RESISTOR	10	unknown	1	R5
+RESISTOR	100	unknown	2	RE1 RE2
+RESISTOR	100K	unknown	1	RL
+RESISTOR	1K	unknown	1	RC2
+RESISTOR	2.8K	unknown	1	R4
+RESISTOR	28K	unknown	2	R1 R3
+RESISTOR	2K	unknown	1	R2
+RESISTOR	3.3K	unknown	1	RC1
+VOLTAGE_SOURCE	DC 15V	none	1	VCC
+vsin	DC 1.6V AC 10MV SIN(0 1MV 1KHZ)	none	1	Vinput
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/cascade-output.net b/gnetlist/tests/common/outputs/partslist3/cascade-output.net
new file mode 100644
index 0000000..3d8192d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/cascade-output.net
@@ -0,0 +1,10 @@
+.START
+..device	value	footprint	quantity	refdes
+cascade-amp	unknown	none	2	AMP1 AMP2
+cascade-defaults	unknown	none	1	DEF1
+cascade-defaults-top	unknown	unknown	1	DEFAULTS
+cascade-filter	unknown	none	1	FL1
+cascade-mixer	unknown	none	1	MX1
+cascade-source	unknown	none	1	SOURCE
+cascade-transformer	unknown	none	1	T1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/cascade.retcode b/gnetlist/tests/common/outputs/partslist3/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/multiequal-output.net b/gnetlist/tests/common/outputs/partslist3/multiequal-output.net
new file mode 100644
index 0000000..a3f4703
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/multiequal-output.net
@@ -0,0 +1,6 @@
+.START
+..device	value	footprint	quantity	refdes
+options	abotol=1e-11	unknown	1	A1
+RESISTOR	20	unknown	1	R1
+VOLTAGE_SOURCE	DC 1V	none	1	V1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/multiequal.retcode b/gnetlist/tests/common/outputs/partslist3/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/netattrib-output.net b/gnetlist/tests/common/outputs/partslist3/netattrib-output.net
new file mode 100644
index 0000000..f0d15d7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/netattrib-output.net
@@ -0,0 +1,6 @@
+.START
+..device	value	footprint	quantity	refdes
+7400	unknown	DIP14	1	U100
+7404	unknown	DIP14	2	U200 U300
+FUSE	unknown	unknown	1	F1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/netattrib.retcode b/gnetlist/tests/common/outputs/partslist3/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/powersupply-output.net b/gnetlist/tests/common/outputs/partslist3/powersupply-output.net
new file mode 100644
index 0000000..4ca1bca
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/powersupply-output.net
@@ -0,0 +1,15 @@
+.START
+..device	value	footprint	quantity	refdes
+DIODE-BRIDGE	unknown	unknown	1	U1
+FUSE	unknown	unknown	1	F1
+LM317	unknown	unknown	1	U2
+MAINS_CONNECTOR	unknown	unknown	1	CONN1
+POLARIZED_CAPACITOR	0.1uF	unknown	1	C2
+POLARIZED_CAPACITOR	1uf	unknown	1	C4
+POLARIZED_CAPACITOR	2200uF	unknown	1	C1
+POLARIZED_CAPACITOR	22uF	unknown	1	C3
+RESISTOR	220	unknown	1	R2
+SPST	unknown	unknown	1	S1
+transformer	unknown	unknown	1	T1
+VARIABLE_RESISTOR	5k	unknown	1	R1
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/powersupply.retcode b/gnetlist/tests/common/outputs/partslist3/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/partslist3/singlenet-output.net b/gnetlist/tests/common/outputs/partslist3/singlenet-output.net
new file mode 100644
index 0000000..dfda6c1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/singlenet-output.net
@@ -0,0 +1,4 @@
+.START
+..device	value	footprint	quantity	refdes
+7400	unknown	DIP14	1	U100
+.END
diff --git a/gnetlist/tests/common/outputs/partslist3/singlenet.retcode b/gnetlist/tests/common/outputs/partslist3/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/partslist3/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/.gitignore b/gnetlist/tests/common/outputs/pcbpins/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD-output.net b/gnetlist/tests/common/outputs/pcbpins/JD-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD.retcode b/gnetlist/tests/common/outputs/pcbpins/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include.retcode b/gnetlist/tests/common/outputs/pcbpins/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort.retcode b/gnetlist/tests/common/outputs/pcbpins/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net b/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net
new file mode 100644
index 0000000..c68ad7b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/JD_nomunge-output.net
@@ -0,0 +1,50 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element Cm
+ChangePinName(Cm, 2, 2)
+ChangePinName(Cm, 1, 1)
+
+# Start of element A1
+
+# Start of element Rt
+ChangePinName(Rt, 1, 1)
+ChangePinName(Rt, 2, 2)
+
+# Start of element M1
+ChangePinName(M1, G, G)
+ChangePinName(M1, D, D)
+ChangePinName(M1, B, B)
+ChangePinName(M1, S, S)
+
+# Start of element X1
+ChangePinName(X1, 7, Vss)
+ChangePinName(X1, 6, Vdd1)
+ChangePinName(X1, 2, DGND)
+ChangePinName(X1, 3, VH)
+ChangePinName(X1, 1, D)
+ChangePinName(X1, 5, Y1)
+ChangePinName(X1, 4, Y0)
+
+# Start of element Rlp
+ChangePinName(Rlp, 1, 1)
+ChangePinName(Rlp, 2, 2)
+
+# Start of element Vdd
+ChangePinName(Vdd, 2, -)
+ChangePinName(Vdd, 1, +)
+
+# Start of element Rlm
+ChangePinName(Rlm, 1, 1)
+ChangePinName(Rlm, 2, 2)
+
+# Start of element Cp
+ChangePinName(Cp, 2, 2)
+ChangePinName(Cp, 1, 1)
+
+# Start of element Rb
+ChangePinName(Rb, 1, 1)
+ChangePinName(Rb, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/Makefile.am b/gnetlist/tests/common/outputs/pcbpins/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps-output.net
new file mode 100644
index 0000000..18a4d10
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps-output.net
@@ -0,0 +1,15 @@
+# Pin name action command file
+
+# Start of element U1
+ChangePinName(U1, 14, 14)
+ChangePinName(U1, 13, 13)
+ChangePinName(U1, 12, 12)
+ChangePinName(U1, 8, 8)
+ChangePinName(U1, 9, 9)
+ChangePinName(U1, 10, 10)
+ChangePinName(U1, 7, 7)
+ChangePinName(U1, 6, 6)
+ChangePinName(U1, 5, 5)
+ChangePinName(U1, 1, 1)
+ChangePinName(U1, 2, 2)
+ChangePinName(U1, 3, 3)
diff --git a/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net
new file mode 100644
index 0000000..3674577
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp-output.net
@@ -0,0 +1,89 @@
+# Pin name action command file
+
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element R4
+ChangePinName(R4, 1, 1)
+ChangePinName(R4, 2, 2)
+
+# Start of element RE2
+ChangePinName(RE2, 1, 1)
+ChangePinName(RE2, 2, 2)
+
+# Start of element Q2
+ChangePinName(Q2, 2, 2)
+ChangePinName(Q2, 1, 1)
+ChangePinName(Q2, 3, 3)
+
+# Start of element A3
+
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element A2
+
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
+
+# Start of element A1
+
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element Vinput
+ChangePinName(Vinput, 2, -)
+ChangePinName(Vinput, 1, +)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
+
+# Start of element CE1
+ChangePinName(CE1, 2, 2)
+ChangePinName(CE1, 1, 1)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
+
+# Start of element RC2
+ChangePinName(RC2, 1, 1)
+ChangePinName(RC2, 2, 2)
+
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..3674577
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include-output.net
@@ -0,0 +1,89 @@
+# Pin name action command file
+
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element R4
+ChangePinName(R4, 1, 1)
+ChangePinName(R4, 2, 2)
+
+# Start of element RE2
+ChangePinName(RE2, 1, 1)
+ChangePinName(RE2, 2, 2)
+
+# Start of element Q2
+ChangePinName(Q2, 2, 2)
+ChangePinName(Q2, 1, 1)
+ChangePinName(Q2, 3, 3)
+
+# Start of element A3
+
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element A2
+
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
+
+# Start of element A1
+
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element Vinput
+ChangePinName(Vinput, 2, -)
+ChangePinName(Vinput, 1, +)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
+
+# Start of element CE1
+ChangePinName(CE1, 2, 2)
+ChangePinName(CE1, 1, 1)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
+
+# Start of element RC2
+ChangePinName(RC2, 1, 1)
+ChangePinName(RC2, 2, 2)
+
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..3674577
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort-output.net
@@ -0,0 +1,89 @@
+# Pin name action command file
+
+# Start of element Cout
+ChangePinName(Cout, 2, 2)
+ChangePinName(Cout, 1, 1)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element R4
+ChangePinName(R4, 1, 1)
+ChangePinName(R4, 2, 2)
+
+# Start of element RE2
+ChangePinName(RE2, 1, 1)
+ChangePinName(RE2, 2, 2)
+
+# Start of element Q2
+ChangePinName(Q2, 2, 2)
+ChangePinName(Q2, 1, 1)
+ChangePinName(Q2, 3, 3)
+
+# Start of element A3
+
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element A2
+
+# Start of element RE1
+ChangePinName(RE1, 1, 1)
+ChangePinName(RE1, 2, 2)
+
+# Start of element Q1
+ChangePinName(Q1, 2, 2)
+ChangePinName(Q1, 1, 1)
+ChangePinName(Q1, 3, 3)
+
+# Start of element A1
+
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element Vinput
+ChangePinName(Vinput, 2, -)
+ChangePinName(Vinput, 1, +)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
+
+# Start of element CE2
+ChangePinName(CE2, 2, 2)
+ChangePinName(CE2, 1, 1)
+
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
+
+# Start of element CE1
+ChangePinName(CE1, 2, 2)
+ChangePinName(CE1, 1, 1)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element VCC
+ChangePinName(VCC, 2, -)
+ChangePinName(VCC, 1, +)
+
+# Start of element RC2
+ChangePinName(RC2, 1, 1)
+ChangePinName(RC2, 2, 2)
+
+# Start of element RC1
+ChangePinName(RC1, 1, 1)
+ChangePinName(RC1, 2, 2)
+
+# Start of element RL
+ChangePinName(RL, 1, 1)
+ChangePinName(RL, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/cascade-output.net b/gnetlist/tests/common/outputs/pcbpins/cascade-output.net
new file mode 100644
index 0000000..8105894
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/cascade-output.net
@@ -0,0 +1,31 @@
+# Pin name action command file
+
+# Start of element AMP2
+ChangePinName(AMP2, 2, OUT)
+ChangePinName(AMP2, 1, IN)
+
+# Start of element AMP1
+ChangePinName(AMP1, 2, OUT)
+ChangePinName(AMP1, 1, IN)
+
+# Start of element SOURCE
+ChangePinName(SOURCE, 1, OUT)
+
+# Start of element DEFAULTS
+ChangePinName(DEFAULTS, unknown, unknown)
+
+# Start of element MX1
+ChangePinName(MX1, 2, OUT)
+ChangePinName(MX1, 1, IN)
+
+# Start of element DEF1
+ChangePinName(DEF1, 2, OUT)
+ChangePinName(DEF1, 1, IN)
+
+# Start of element T1
+ChangePinName(T1, 2, 2)
+ChangePinName(T1, 1, 1)
+
+# Start of element FL1
+ChangePinName(FL1, 2, O)
+ChangePinName(FL1, 1, I)
diff --git a/gnetlist/tests/common/outputs/pcbpins/cascade.retcode b/gnetlist/tests/common/outputs/pcbpins/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net b/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net
new file mode 100644
index 0000000..cd11be3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/multiequal-output.net
@@ -0,0 +1,11 @@
+# Pin name action command file
+
+# Start of element V1
+ChangePinName(V1, 2, -)
+ChangePinName(V1, 1, +)
+
+# Start of element A1
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
diff --git a/gnetlist/tests/common/outputs/pcbpins/multiequal.retcode b/gnetlist/tests/common/outputs/pcbpins/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net b/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net
new file mode 100644
index 0000000..8a641ba
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/netattrib-output.net
@@ -0,0 +1,25 @@
+# Pin name action command file
+
+# Start of element F1
+ChangePinName(F1, 2, 2)
+ChangePinName(F1, 1, 1)
+
+# Start of element U100
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, 1, A)
+ChangePinName(U100, 2, B)
+ChangePinName(U100, 3, Y)
+
+# Start of element U300
+ChangePinName(U300, unknown, unknown)
+ChangePinName(U300, unknown, unknown)
+ChangePinName(U300, 2, Y)
+ChangePinName(U300, 1, A)
+
+# Start of element U200
+ChangePinName(U200, unknown, unknown)
+ChangePinName(U200, unknown, unknown)
+ChangePinName(U200, 2, Y)
+ChangePinName(U200, 1, A)
diff --git a/gnetlist/tests/common/outputs/pcbpins/netattrib.retcode b/gnetlist/tests/common/outputs/pcbpins/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net b/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net
new file mode 100644
index 0000000..eef4f52
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/powersupply-output.net
@@ -0,0 +1,56 @@
+# Pin name action command file
+
+# Start of element F1
+ChangePinName(F1, 2, 2)
+ChangePinName(F1, 1, 1)
+
+# Start of element R2
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 2, 2)
+
+# Start of element CONN1
+ChangePinName(CONN1, 3, 3)
+ChangePinName(CONN1, 2, 2)
+ChangePinName(CONN1, 1, 1)
+
+# Start of element C4
+ChangePinName(C4, 2, -)
+ChangePinName(C4, 1, +)
+
+# Start of element R1
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 2, 2)
+ChangePinName(R1, 3, 3)
+
+# Start of element C3
+ChangePinName(C3, 2, -)
+ChangePinName(C3, 1, +)
+
+# Start of element C2
+ChangePinName(C2, 2, -)
+ChangePinName(C2, 1, +)
+
+# Start of element S1
+ChangePinName(S1, 1, 1)
+ChangePinName(S1, 2, 2)
+
+# Start of element C1
+ChangePinName(C1, 2, -)
+ChangePinName(C1, 1, +)
+
+# Start of element T1
+ChangePinName(T1, 3, 3)
+ChangePinName(T1, 4, 4)
+ChangePinName(T1, 1, 1)
+ChangePinName(T1, 2, 2)
+
+# Start of element U2
+ChangePinName(U2, 1, Adjust)
+ChangePinName(U2, 3, Vin)
+ChangePinName(U2, 2, Vout)
+
+# Start of element U1
+ChangePinName(U1, 4, 4)
+ChangePinName(U1, 3, 3)
+ChangePinName(U1, 2, 2)
+ChangePinName(U1, 1, 1)
diff --git a/gnetlist/tests/common/outputs/pcbpins/powersupply.retcode b/gnetlist/tests/common/outputs/pcbpins/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/pcbpins/singlenet-output.net b/gnetlist/tests/common/outputs/pcbpins/singlenet-output.net
new file mode 100644
index 0000000..354731e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/singlenet-output.net
@@ -0,0 +1,18 @@
+# Pin name action command file
+
+# Start of element U100
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, 9, A)
+ChangePinName(U100, 10, B)
+ChangePinName(U100, 8, Y)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, 1, A)
+ChangePinName(U100, 2, B)
+ChangePinName(U100, 3, Y)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, unknown, unknown)
+ChangePinName(U100, 4, A)
+ChangePinName(U100, 5, B)
+ChangePinName(U100, 6, Y)
diff --git a/gnetlist/tests/common/outputs/pcbpins/singlenet.retcode b/gnetlist/tests/common/outputs/pcbpins/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/pcbpins/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/protelII/.gitignore b/gnetlist/tests/common/outputs/protelII/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/protelII/JD-output.net b/gnetlist/tests/common/outputs/protelII/JD-output.net
new file mode 100644
index 0000000..17a4b68
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/JD-output.net
@@ -0,0 +1,684 @@
+PROTEL NETLIST 2.0
+[
+DESIGNATOR
+V1
+FOOTPRINT
+none
+PARTTYPE
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DESCRIPTION
+vpulse
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Cm
+FOOTPRINT
+unknown
+PARTTYPE
+20p
+DESCRIPTION
+CAPACITOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+A1
+FOOTPRINT
+unknown
+PARTTYPE
+model
+DESCRIPTION
+model
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rt
+FOOTPRINT
+unknown
+PARTTYPE
+1k
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+M1
+FOOTPRINT
+unknown
+PARTTYPE
+PMOS_TRANSISTOR
+DESCRIPTION
+PMOS_TRANSISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
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+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+X1
+FOOTPRINT
+unknown
+PARTTYPE
+LVD
+DESCRIPTION
+LVD
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rlp
+FOOTPRINT
+unknown
+PARTTYPE
+1meg
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
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+*
+Part Field 5
+*
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+*
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+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
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+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
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+*
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+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Vdd
+FOOTPRINT
+none
+PARTTYPE
+DC 3.3V
+DESCRIPTION
+VOLTAGE_SOURCE
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rlm
+FOOTPRINT
+unknown
+PARTTYPE
+500k
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Cp
+FOOTPRINT
+unknown
+PARTTYPE
+20p
+DESCRIPTION
+CAPACITOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rb
+FOOTPRINT
+unknown
+PARTTYPE
+5.6k
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+(
+Vdd1
+Rlp-2 RESISTOR-2 PASSIVE
+M1-B PMOS_TRANSISTOR-B PASSIVE
+M1-S PMOS_TRANSISTOR-S PASSIVE
+Vdd-1 VOLTAGE_SOURCE-1 PASSIVE
+X1-6 LVD-6 PASSIVE 
+)
+(
+GND
+Cm-2 CAPACITOR-2 PASSIVE
+Cp-2 CAPACITOR-2 PASSIVE
+Rlm-2 RESISTOR-2 PASSIVE
+Vdd-2 VOLTAGE_SOURCE-2 PASSIVE
+V1-2 vpulse-2 PASSIVE
+Rb-1 RESISTOR-1 PASSIVE
+X1-7 LVD-7 PASSIVE
+X1-2 LVD-2 PASSIVE 
+)
+(
+LVH
+Rb-2 RESISTOR-2 PASSIVE
+M1-D PMOS_TRANSISTOR-D PASSIVE
+M1-G PMOS_TRANSISTOR-G PASSIVE
+X1-3 LVD-3 PASSIVE 
+)
+(
+i
+V1-1 vpulse-1 PASSIVE
+X1-1 LVD-1 PASSIVE 
+)
+(
+p
+Cp-1 CAPACITOR-1 PASSIVE
+Rt-1 RESISTOR-1 PASSIVE
+Rlp-1 RESISTOR-1 PASSIVE
+X1-5 LVD-5 PASSIVE 
+)
+(
+m
+Cm-1 CAPACITOR-1 PASSIVE
+Rlm-1 RESISTOR-1 PASSIVE
+Rt-2 RESISTOR-2 PASSIVE
+X1-4 LVD-4 PASSIVE 
+)
diff --git a/gnetlist/tests/common/outputs/protelII/JD.retcode b/gnetlist/tests/common/outputs/protelII/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include-output.net b/gnetlist/tests/common/outputs/protelII/JD_Include-output.net
new file mode 100644
index 0000000..17a4b68
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/JD_Include-output.net
@@ -0,0 +1,684 @@
+PROTEL NETLIST 2.0
+[
+DESIGNATOR
+V1
+FOOTPRINT
+none
+PARTTYPE
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+DESCRIPTION
+vpulse
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Cm
+FOOTPRINT
+unknown
+PARTTYPE
+20p
+DESCRIPTION
+CAPACITOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+A1
+FOOTPRINT
+unknown
+PARTTYPE
+model
+DESCRIPTION
+model
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
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+DESIGNATOR
+Rt
+FOOTPRINT
+unknown
+PARTTYPE
+1k
+DESCRIPTION
+RESISTOR
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+*
+Part Field 8
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+*
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+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+M1
+FOOTPRINT
+unknown
+PARTTYPE
+PMOS_TRANSISTOR
+DESCRIPTION
+PMOS_TRANSISTOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
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+*
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+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+X1
+FOOTPRINT
+unknown
+PARTTYPE
+LVD
+DESCRIPTION
+LVD
+Part Field 1
+*
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+*
+Part Field 3
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+*
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+Part Field 11
+*
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+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rlp
+FOOTPRINT
+unknown
+PARTTYPE
+1meg
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
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+*
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+*
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+*
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+*
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+*
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+*
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+*
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+*
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+*
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+Part Field 15
+*
+Part Field 16
+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Vdd
+FOOTPRINT
+none
+PARTTYPE
+DC 3.3V
+DESCRIPTION
+VOLTAGE_SOURCE
+Part Field 1
+*
+Part Field 2
+*
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+*
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+*
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+*
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+*
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+*
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+*
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+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Rlm
+FOOTPRINT
+unknown
+PARTTYPE
+500k
+DESCRIPTION
+RESISTOR
+Part Field 1
+*
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+*
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+*
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+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
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+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+Cp
+FOOTPRINT
+unknown
+PARTTYPE
+20p
+DESCRIPTION
+CAPACITOR
+Part Field 1
+*
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include.retcode b/gnetlist/tests/common/outputs/protelII/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/JD_Include.retcode
@@ -0,0 +1 @@
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..17a4b68
--- /dev/null
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/protelII/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net b/gnetlist/tests/common/outputs/protelII/JD_Sort-output.net
new file mode 100644
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort.retcode b/gnetlist/tests/common/outputs/protelII/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge-output.net
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index 0000000..17a4b68
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diff --git a/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/protelII/JD_Sort_nomunge.retcode
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diff --git a/gnetlist/tests/common/outputs/protelII/Makefile.am b/gnetlist/tests/common/outputs/protelII/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/protelII/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/protelII/SlottedOpamps-output.net
new file mode 100644
index 0000000..3b43b09
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/SlottedOpamps-output.net
@@ -0,0 +1,98 @@
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diff --git a/gnetlist/tests/common/outputs/protelII/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/protelII/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/SlottedOpamps.retcode
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diff --git a/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/protelII/TwoStageAmp-output.net
new file mode 100644
index 0000000..b269748
--- /dev/null
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+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+C2
+FOOTPRINT
+unknown
+PARTTYPE
+0.1uF
+DESCRIPTION
+POLARIZED_CAPACITOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+S1
+FOOTPRINT
+unknown
+PARTTYPE
+SPST
+DESCRIPTION
+SPST
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+C1
+FOOTPRINT
+unknown
+PARTTYPE
+2200uF
+DESCRIPTION
+POLARIZED_CAPACITOR
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+T1
+FOOTPRINT
+unknown
+PARTTYPE
+transformer
+DESCRIPTION
+transformer
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+U2
+FOOTPRINT
+unknown
+PARTTYPE
+LM317
+DESCRIPTION
+LM317
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+[
+DESIGNATOR
+U1
+FOOTPRINT
+unknown
+PARTTYPE
+DIODE-BRIDGE
+DESCRIPTION
+DIODE-BRIDGE
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+(
+ten
+U2-1 LM317-1 PASSIVE
+R1-2 VARIABLE_RESISTOR-2 PASSIVE
+C3-1 POLARIZED_CAPACITOR-1 PASSIVE
+R2-1 RESISTOR-1 PASSIVE 
+)
+(
+eleven
+U2-2 LM317-2 PASSIVE
+C4-1 POLARIZED_CAPACITOR-1 PASSIVE
+R2-2 RESISTOR-2 PASSIVE 
+)
+(
+GND
+CONN1-3 MAINS_CONNECTOR-3 PASSIVE 
+)
+(
+one
+S1-1 SPST-1 PASSIVE
+CONN1-1 MAINS_CONNECTOR-1 PASSIVE 
+)
+(
+five
+CONN1-2 MAINS_CONNECTOR-2 PASSIVE
+T1-2 transformer-2 PASSIVE 
+)
+(
+three
+T1-1 transformer-1 PASSIVE
+F1-2 FUSE-2 PASSIVE 
+)
+(
+two
+S1-2 SPST-2 PASSIVE
+F1-1 FUSE-1 PASSIVE 
+)
+(
+six
+T1-3 transformer-3 PASSIVE
+U1-4 DIODE-BRIDGE-4 PASSIVE 
+)
+(
+seven
+T1-4 transformer-4 PASSIVE
+U1-3 DIODE-BRIDGE-3 PASSIVE 
+)
+(
+nine
+C4-2 POLARIZED_CAPACITOR-2 PASSIVE
+C3-2 POLARIZED_CAPACITOR-2 PASSIVE
+R1-3 VARIABLE_RESISTOR-3 PASSIVE
+R1-1 VARIABLE_RESISTOR-1 PASSIVE
+C2-2 POLARIZED_CAPACITOR-2 PASSIVE
+C1-2 POLARIZED_CAPACITOR-2 PASSIVE
+U1-2 DIODE-BRIDGE-2 PASSIVE 
+)
+(
+eight
+U2-3 LM317-3 PASSIVE
+C2-1 POLARIZED_CAPACITOR-1 PASSIVE
+C1-1 POLARIZED_CAPACITOR-1 PASSIVE
+U1-1 DIODE-BRIDGE-1 PASSIVE 
+)
diff --git a/gnetlist/tests/common/outputs/protelII/powersupply.retcode b/gnetlist/tests/common/outputs/protelII/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/protelII/singlenet-output.net b/gnetlist/tests/common/outputs/protelII/singlenet-output.net
new file mode 100644
index 0000000..87bcc9d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/singlenet-output.net
@@ -0,0 +1,81 @@
+PROTEL NETLIST 2.0
+[
+DESIGNATOR
+U100
+FOOTPRINT
+DIP14
+PARTTYPE
+7400
+DESCRIPTION
+7400
+Part Field 1
+*
+Part Field 2
+*
+Part Field 3
+*
+Part Field 4
+*
+Part Field 5
+*
+Part Field 6
+*
+Part Field 7
+*
+Part Field 8
+*
+Part Field 9
+*
+Part Field 10
+*
+Part Field 11
+*
+Part Field 12
+*
+Part Field 13
+*
+Part Field 14
+*
+Part Field 15
+*
+Part Field 16
+*
+LIBRARYFIELD1
+
+LIBRARYFIELD2
+
+LIBRARYFIELD3
+
+LIBRARYFIELD4
+
+LIBRARYFIELD5
+
+LIBRARYFIELD6
+
+LIBRARYFIELD7
+
+LIBRARYFIELD8
+
+]
+(
+SING_N_2
+U100-1 7400-1 PASSIVE
+U100-3 7400-3 PASSIVE 
+)
+(
+GND
+U100-7 7400-7 PASSIVE 
+)
+(
+Vcc
+U100-14 7400-14 PASSIVE 
+)
+(
+SING_N
+U100-4 7400-4 PASSIVE
+U100-5 7400-5 PASSIVE
+U100-10 7400-10 PASSIVE
+U100-8 7400-8 PASSIVE
+U100-9 7400-9 PASSIVE
+U100-6 7400-6 PASSIVE 
+)
diff --git a/gnetlist/tests/common/outputs/protelII/singlenet.retcode b/gnetlist/tests/common/outputs/protelII/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/protelII/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/.gitignore b/gnetlist/tests/common/outputs/redac/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/redac/JD-output.net b/gnetlist/tests/common/outputs/redac/JD-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/JD.retcode b/gnetlist/tests/common/outputs/redac/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/JD_Include-output.net b/gnetlist/tests/common/outputs/redac/JD_Include-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Include-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/JD_Include.retcode b/gnetlist/tests/common/outputs/redac/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/redac/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Include_nomunge-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/redac/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/JD_Sort-output.net b/gnetlist/tests/common/outputs/redac/JD_Sort-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Sort-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/JD_Sort.retcode b/gnetlist/tests/common/outputs/redac/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/JD_nomunge-output.net b/gnetlist/tests/common/outputs/redac/JD_nomunge-output.net
new file mode 100644
index 0000000..8316461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/JD_nomunge-output.net
@@ -0,0 +1,18 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM Vdd1
+Rlp 2 M1 B M1 S Vdd 1 X1 6
+.REM GND
+Cm 2 Cp 2 Rlm 2 Vdd 2 V1 2 Rb 1 X1 7 X1 2
+.REM LVH
+Rb 2 M1 D M1 G X1 3
+.REM i
+V1 1 X1 1
+.REM p
+Cp 1 Rt 1 Rlp 1 X1 5
+.REM m
+Cm 1 Rlm 1 Rt 2 X1 4
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/Makefile.am b/gnetlist/tests/common/outputs/redac/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/redac/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/redac/SlottedOpamps-output.net
new file mode 100644
index 0000000..110388f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/SlottedOpamps-output.net
@@ -0,0 +1,24 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM minusin_slot4_pin13_b
+U1 13
+.REM plusin_slot4_pin12_a
+U1 12
+.REM minusin_slot3_pin_b
+U1 9
+.REM plusin_slot3_pin10_a
+U1 10
+.REM minusin_slot2_pin6_b
+U1 6
+.REM plusin_slot2_pin5_a
+U1 5
+.REM samenet_output_c
+U1 14 U1 8 U1 7 U1 1
+.REM minusin_slot1_pin_b
+U1 2
+.REM plusin_slot1_pin3_a
+U1 3
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/redac/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/redac/TwoStageAmp-output.net
new file mode 100644
index 0000000..45a70d8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp-output.net
@@ -0,0 +1,31 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM unnamed_net2
+C2 1 R8 2
+.REM Vbase2
+R3 1 C2 2 R4 2 Q2 2
+.REM Vem2
+CE2 2 RE2 2 Q2 1
+.REM Vout
+Cout 2 RL 2
+.REM VColl2
+Q2 3 Cout 1 RC2 1
+.REM GND
+R4 1 CE2 1 RE2 1 VCC 2 Vinput 2 CE1 1 RL 1 RE1 1
+RE1 1 R2 1
+.REM Vcc
+R3 2 RC1 2 VCC 1 RC2 2 R1 2
+.REM Vin
+Vinput 1 R5 1
+.REM unnamed_net1
+C1 1 R5 2
+.REM Vbase1
+C1 2 R2 2 R1 1 Q1 2
+.REM Vem1
+CE1 2 RE1 2 Q1 1
+.REM Vcoll1
+R8 1 RC1 1 Q1 3
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/redac/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..45a70d8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include-output.net
@@ -0,0 +1,31 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM unnamed_net2
+C2 1 R8 2
+.REM Vbase2
+R3 1 C2 2 R4 2 Q2 2
+.REM Vem2
+CE2 2 RE2 2 Q2 1
+.REM Vout
+Cout 2 RL 2
+.REM VColl2
+Q2 3 Cout 1 RC2 1
+.REM GND
+R4 1 CE2 1 RE2 1 VCC 2 Vinput 2 CE1 1 RL 1 RE1 1
+RE1 1 R2 1
+.REM Vcc
+R3 2 RC1 2 VCC 1 RC2 2 R1 2
+.REM Vin
+Vinput 1 R5 1
+.REM unnamed_net1
+C1 1 R5 2
+.REM Vbase1
+C1 2 R2 2 R1 1 Q1 2
+.REM Vem1
+CE1 2 RE1 2 Q1 1
+.REM Vcoll1
+R8 1 RC1 1 Q1 3
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..45a70d8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort-output.net
@@ -0,0 +1,31 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM unnamed_net2
+C2 1 R8 2
+.REM Vbase2
+R3 1 C2 2 R4 2 Q2 2
+.REM Vem2
+CE2 2 RE2 2 Q2 1
+.REM Vout
+Cout 2 RL 2
+.REM VColl2
+Q2 3 Cout 1 RC2 1
+.REM GND
+R4 1 CE2 1 RE2 1 VCC 2 Vinput 2 CE1 1 RL 1 RE1 1
+RE1 1 R2 1
+.REM Vcc
+R3 2 RC1 2 VCC 1 RC2 2 R1 2
+.REM Vin
+Vinput 1 R5 1
+.REM unnamed_net1
+C1 1 R5 2
+.REM Vbase1
+C1 2 R2 2 R1 1 Q1 2
+.REM Vem1
+CE1 2 RE1 2 Q1 1
+.REM Vcoll1
+R8 1 RC1 1 Q1 3
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/cascade-output.net b/gnetlist/tests/common/outputs/redac/cascade-output.net
new file mode 100644
index 0000000..3ff6a57
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/cascade-output.net
@@ -0,0 +1,20 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM unnamed_net6
+AMP2 1 T1 2
+.REM unnamed_net5
+T1 1 MX1 2
+.REM unnamed_net4
+MX1 1 FL1 2
+.REM unnamed_net3
+FL1 1 DEF1 2
+.REM unnamed_net2
+DEF1 1 AMP1 2
+.REM unnamed_net1
+AMP1 1 SOURCE 1
+.REM GND
+DEFAULTS 1
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/cascade.retcode b/gnetlist/tests/common/outputs/redac/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/multiequal-output.net b/gnetlist/tests/common/outputs/redac/multiequal-output.net
new file mode 100644
index 0000000..ec50c31
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/multiequal-output.net
@@ -0,0 +1,10 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM GND
+V1 2 R1 1
+.REM unnamed_net1
+V1 1 R1 2
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/multiequal.retcode b/gnetlist/tests/common/outputs/redac/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/netattrib-output.net b/gnetlist/tests/common/outputs/redac/netattrib-output.net
new file mode 100644
index 0000000..df9e5da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/netattrib-output.net
@@ -0,0 +1,16 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM unnamed_net1
+U300 2
+.REM netattrib
+U200 2 U100 5
+.REM GND
+U300 7 U200 7 U100 7
+.REM Vcc
+U300 14 U200 14 U100 14
+.REM one
+F1 1 U300 1 U200 1 U100 3
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/netattrib.retcode b/gnetlist/tests/common/outputs/redac/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/powersupply-output.net b/gnetlist/tests/common/outputs/redac/powersupply-output.net
new file mode 100644
index 0000000..309ce81
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/powersupply-output.net
@@ -0,0 +1,28 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM ten
+U2 1 R1 2 C3 1 R2 1
+.REM eleven
+U2 2 C4 1 R2 2
+.REM GND
+CONN1 3
+.REM one
+S1 1 CONN1 1
+.REM five
+CONN1 2 T1 2
+.REM three
+T1 1 F1 2
+.REM two
+S1 2 F1 1
+.REM six
+T1 3 U1 4
+.REM seven
+T1 4 U1 3
+.REM nine
+C4 2 C3 2 R1 3 R1 1 C2 2 C1 2 U1 2
+.REM eight
+U2 3 C2 1 C1 1 U1 1
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/powersupply.retcode b/gnetlist/tests/common/outputs/redac/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/redac/singlenet-output.net b/gnetlist/tests/common/outputs/redac/singlenet-output.net
new file mode 100644
index 0000000..aeb0d94
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/singlenet-output.net
@@ -0,0 +1,14 @@
+.PCB
+.REM CREATED BY gEDA GNETLIST
+.CON
+.COD 2
+
+.REM SING_N_2
+U100 1 U100 3
+.REM GND
+U100 7
+.REM Vcc
+U100 14
+.REM SING_N
+U100 4 U100 5 U100 10 U100 8 U100 9 U100 6
+.EOD
diff --git a/gnetlist/tests/common/outputs/redac/singlenet.retcode b/gnetlist/tests/common/outputs/redac/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/redac/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/regen_sub_makefile_am.sh b/gnetlist/tests/common/outputs/regen_sub_makefile_am.sh
new file mode 100755
index 0000000..aeca5b7
--- /dev/null
+++ b/gnetlist/tests/common/outputs/regen_sub_makefile_am.sh
@@ -0,0 +1,13 @@
+#!/bin/sh
+
+OUTPUTDIRS=`find . -mindepth 1 -type d`
+
+for DIR in $OUTPUTDIRS; do
+  EXTRADIST=`ls $DIR/*.net $DIR/*.retcode | sort`
+  echo -n "EXTRA_DIST=" > $DIR/Makefile.am
+  for FILE in $EXTRADIST; do
+    BASEFILE=`basename $FILE`
+    echo -n " \\\\\\n\\t$BASEFILE" >> $DIR/Makefile.am
+  done
+  echo >> $DIR/Makefile.am
+done
diff --git a/gnetlist/tests/common/outputs/spice-sdb/.gitignore b/gnetlist/tests/common/outputs/spice-sdb/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD-output.net
new file mode 100644
index 0000000..e1bb285
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD-output.net
@@ -0,0 +1,24 @@
+* ../../../src/gnetlist -g spice-sdb LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
+*
+.model unknown_LVD (stuff)
+*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p  
+Rt p m 1k  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+Rlp p Vdd1 1meg  
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k  
+Cp p 0 20p  
+Rb 0 LVH 5.6k  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD.retcode b/gnetlist/tests/common/outputs/spice-sdb/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
new file mode 100644
index 0000000..647fbff
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include-output.net
@@ -0,0 +1,20 @@
+* ../../../src/gnetlist -g spice-sdb -I LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+.INCLUDE ./models/openIP_5.cir
+*==============  Begin SPICE netlist of main design ============
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p  
+Rt p m 1k  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+Rlp p Vdd1 1meg  
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k  
+Cp p 0 20p  
+Rb 0 LVH 5.6k  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include.retcode b/gnetlist/tests/common/outputs/spice-sdb/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..eec3dd1
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge-output.net
@@ -0,0 +1,20 @@
+* ../../../src/gnetlist -g spice-sdb -I -n LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+.INCLUDE ./models/openIP_5.cir
+*==============  Begin SPICE netlist of main design ============
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p  
+Rt p m 1k  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+X1 i 0 LVH m p Vdd1 0 unknown_LVD
+Rlp p Vdd1 1meg  
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k  
+Cp p 0 20p  
+Rb 0 LVH 5.6k  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Sort-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort-output.net
new file mode 100644
index 0000000..d715184
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort-output.net
@@ -0,0 +1,24 @@
+* ../../../src/gnetlist -g spice-sdb -s LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
+*
+.model unknown_LVD (stuff)
+*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+Cm m 0 20p  
+Cp p 0 20p  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+Rb 0 LVH 5.6k  
+Rlm m 0 500k  
+Rlp p Vdd1 1meg  
+Rt p m 1k  
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Vdd Vdd1 0 DC 3.3V
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Sort.retcode b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..ce92fdf
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge-output.net
@@ -0,0 +1,24 @@
+* ../../../src/gnetlist -g spice-sdb -s -n LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
+*
+.model unknown_LVD (stuff)
+*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+Cm m 0 20p  
+Cp p 0 20p  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+Rb 0 LVH 5.6k  
+Rlm m 0 500k  
+Rlp p Vdd1 1meg  
+Rt p m 1k  
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Vdd Vdd1 0 DC 3.3V
+X1 i 0 LVH m p Vdd1 0 unknown_LVD
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net b/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
new file mode 100644
index 0000000..e1bb285
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/JD_nomunge-output.net
@@ -0,0 +1,24 @@
+* ../../../src/gnetlist -g spice-sdb LVDfoo.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/openIP_5.cir vvvvvvvv
+*
+.model unknown_LVD (stuff)
+*^^^^^^^^  End of included SPICE model from ./models/openIP_5.cir ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p  
+Rt p m 1k  
+M1 LVH LVH Vdd1 Vdd1 pch  l=3u w=3u m=36
+UX1 i 0 LVH m p Vdd1 0 unknown_LVD
+Rlp p Vdd1 1meg  
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k  
+Cp p 0 20p  
+Rb 0 LVH 5.6k  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/Makefile.am b/gnetlist/tests/common/outputs/spice-sdb/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
new file mode 100644
index 0000000..e571f05
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps-output.net
@@ -0,0 +1,13 @@
+* ../../../src/gnetlist -g spice-sdb SlottedOpamps.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+U1.4 samenet_output_c minusin_slot4_pin13_b plusin_slot4_pin12_a unknown
+U1.3 samenet_output_c minusin_slot3_pin_b plusin_slot3_pin10_a unknown
+U1.2 samenet_output_c minusin_slot2_pin6_b plusin_slot2_pin5_a unknown
+U1.1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a unknown
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
new file mode 100644
index 0000000..3fa5a97
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp-output.net
@@ -0,0 +1,38 @@
+* ../../../src/gnetlist -g spice-sdb TwoStageAmp.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
+.model 2N3904   NPN(Stuff
++               More stuff
++               Yet more stuff
++               Final line of stuff)
+*^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+Cout VColl2 Vout 2.2uF  
+R5 Vin 1 10  
+R4 0 Vbase2 2.8K  
+RE2 0 Vem2 100  
+Q2 VColl2 Vbase2 Vem2 2N3904 
+.options TEMP=25
+R3 Vbase2 Vcc 28K  
+.INCLUDE Simulation.cmd
+RE1 0 Vem1 100  
+Q1 Vcoll1 Vbase1 Vem1 2N3904 
+R2 0 Vbase1 2K  
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+R1 Vbase1 Vcc 28K  
+C2 2 Vbase2 2.2uF  
+CE2 0 Vem2 1pF  
+C1 1 Vbase1 2.2uF  
+CE1 0 Vem1 1pF  
+R8 Vcoll1 2 1  
+VCC Vcc 0 DC 15V
+RC2 VColl2 Vcc 1K  
+RC1 Vcoll1 Vcc 3.3K  
+RL 0 Vout 100K  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..6b45461
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include-output.net
@@ -0,0 +1,32 @@
+* ../../../src/gnetlist -g spice-sdb -I TwoStageAmp.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+.INCLUDE ./models/2N3904.mod
+*==============  Begin SPICE netlist of main design ============
+Cout VColl2 Vout 2.2uF  
+R5 Vin 1 10  
+R4 0 Vbase2 2.8K  
+RE2 0 Vem2 100  
+Q2 VColl2 Vbase2 Vem2 2N3904 
+.options TEMP=25
+R3 Vbase2 Vcc 28K  
+.INCLUDE Simulation.cmd
+RE1 0 Vem1 100  
+Q1 Vcoll1 Vbase1 Vem1 2N3904 
+R2 0 Vbase1 2K  
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+R1 Vbase1 Vcc 28K  
+C2 2 Vbase2 2.2uF  
+CE2 0 Vem2 1pF  
+C1 1 Vbase1 2.2uF  
+CE1 0 Vem1 1pF  
+R8 Vcoll1 2 1  
+VCC Vcc 0 DC 15V
+RC2 VColl2 Vcc 1K  
+RC1 Vcoll1 Vcc 3.3K  
+RL 0 Vout 100K  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..ed893be
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort-output.net
@@ -0,0 +1,38 @@
+* ../../../src/gnetlist -g spice-sdb -s TwoStageAmp.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*vvvvvvvv  Included SPICE model from ./models/2N3904.mod vvvvvvvv
+.model 2N3904   NPN(Stuff
++               More stuff
++               Yet more stuff
++               Final line of stuff)
+*^^^^^^^^  End of included SPICE model from ./models/2N3904.mod ^^^^^^^^
+*
+*==============  Begin SPICE netlist of main design ============
+C1 1 Vbase1 2.2uF  
+C2 2 Vbase2 2.2uF  
+CE1 0 Vem1 1pF  
+CE2 0 Vem2 1pF  
+Cout VColl2 Vout 2.2uF  
+Q1 Vcoll1 Vbase1 Vem1 2N3904 
+Q2 VColl2 Vbase2 Vem2 2N3904 
+R1 Vbase1 Vcc 28K  
+R2 0 Vbase1 2K  
+R3 Vbase2 Vcc 28K  
+R4 0 Vbase2 2.8K  
+R5 Vin 1 10  
+R8 Vcoll1 2 1  
+RC1 Vcoll1 Vcc 3.3K  
+RC2 VColl2 Vcc 1K  
+RE1 0 Vem1 100  
+RE2 0 Vem2 100  
+RL 0 Vout 100K  
+VCC Vcc 0 DC 15V
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+.INCLUDE Simulation.cmd
+.options TEMP=25
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net b/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
new file mode 100644
index 0000000..53dbc40
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/cascade-output.net
@@ -0,0 +1,17 @@
+* ../../../src/gnetlist -g spice-sdb cascade.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+AMP2 6 unconnected_pin-1 <No valid value attribute found>
+AMP1 1 2 <No valid value attribute found>
+SOURCE 1 <No valid value attribute found>
+DEFAULTS unknown 
+MX1 4 5 unknown 
+DEF1 2 3 unknown 
+T1 5 6 <No valid value attribute found>
+FL1 3 4 <No valid value attribute found>
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/cascade.retcode b/gnetlist/tests/common/outputs/spice-sdb/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net b/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
new file mode 100644
index 0000000..13f8df9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/multiequal-output.net
@@ -0,0 +1,12 @@
+* ../../../src/gnetlist -g spice-sdb multiequal.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+V1 1 0 DC 1V
+.OPTIONS abotol=1e-11
+R1 0 1 20  
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/multiequal.retcode b/gnetlist/tests/common/outputs/spice-sdb/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
new file mode 100644
index 0000000..775b16e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/netattrib-output.net
@@ -0,0 +1,13 @@
+* ../../../src/gnetlist -g spice-sdb netattrib.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+F1 one unconnected_pin-3 <No valid value attribute found>
+U100 unconnected_pin-2 unconnected_pin-1 one unknown
+U300 one 1 unknown
+U200 one netattrib unknown
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/netattrib.retcode b/gnetlist/tests/common/outputs/spice-sdb/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net b/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
new file mode 100644
index 0000000..8902cec
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/powersupply-output.net
@@ -0,0 +1,21 @@
+* ../../../src/gnetlist -g spice-sdb powersupply.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+F1 two three <No valid value attribute found>
+R2 ten eleven 220  
+CONN1 one five 0 <No valid value attribute found>
+C4 eleven nine 1uf  
+R1 nine ten nine 5k
+C3 ten nine 22uF  
+C2 eight nine 0.1uF  
+S1 one two <No valid value attribute found>
+C1 eight nine 2200uF  
+T1 three five six seven <No valid value attribute found>
+U2 ten eleven eight unknown
+U1 eight nine seven six unknown
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/powersupply.retcode b/gnetlist/tests/common/outputs/spice-sdb/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
new file mode 100644
index 0000000..21adb89
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/singlenet-output.net
@@ -0,0 +1,12 @@
+* ../../../src/gnetlist -g spice-sdb singlenet.sch
+*********************************************************
+* Spice file generated by gnetlist                      *
+* spice-sdb version 4.28.2007 by SDB --                 *
+* provides advanced spice netlisting capability.        *
+* Documentation at http://www.brorson.com/gEDA/SPICE/   *
+*********************************************************
+*==============  Begin SPICE netlist of main design ============
+U100.3 SING_N SING_N SING_N unknown
+U100.2 SING_N SING_N SING_N unknown
+U100.1 SING_N_2 unconnected_pin-1 SING_N_2 unknown
+.end
diff --git a/gnetlist/tests/common/outputs/spice-sdb/singlenet.retcode b/gnetlist/tests/common/outputs/spice-sdb/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice-sdb/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/.gitignore b/gnetlist/tests/common/outputs/spice/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/spice/JD-output.net b/gnetlist/tests/common/outputs/spice/JD-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/JD.retcode b/gnetlist/tests/common/outputs/spice/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include-output.net b/gnetlist/tests/common/outputs/spice/JD_Include-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Include-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include.retcode b/gnetlist/tests/common/outputs/spice/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort-output.net b/gnetlist/tests/common/outputs/spice/JD_Sort-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort.retcode b/gnetlist/tests/common/outputs/spice/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net b/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
new file mode 100644
index 0000000..9c485da
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/JD_nomunge-output.net
@@ -0,0 +1,13 @@
+* Spice netlister for gnetlist
+V1 i 0 pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+Cm m 0 20p
+A1 <No valid value attribute found>
+Rt p m 1k
+M1 LVH LVH Vdd1 Vdd1 <No valid value attribute found> l=3u w=3u
+X1 i 0 LVH m p Vdd1 0 <No valid value attribute found>
+Rlp p Vdd1 1meg
+Vdd Vdd1 0 DC 3.3V
+Rlm m 0 500k
+Cp p 0 20p
+Rb 0 LVH 5.6k
+.END
diff --git a/gnetlist/tests/common/outputs/spice/Makefile.am b/gnetlist/tests/common/outputs/spice/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
new file mode 100644
index 0000000..c73d322
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/SlottedOpamps-output.net
@@ -0,0 +1,3 @@
+* Spice netlister for gnetlist
+U1 samenet_output_c minusin_slot1_pin_b plusin_slot1_pin3_a ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+.END
diff --git a/gnetlist/tests/common/outputs/spice/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/spice/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
new file mode 100644
index 0000000..a91f1a6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp-output.net
@@ -0,0 +1,25 @@
+* Spice netlister for gnetlist
+Cout VColl2 Vout 2.2uF
+R5 Vin 1 10
+R4 0 Vbase2 2.8K
+RE2 0 Vem2 100
+Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+A3 .options TEMP=25
+R3 Vbase2 Vcc 28K
+A2 <No valid value attribute found>
+RE1 0 Vem1 100
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
+A1 <No valid value attribute found>
+R2 0 Vbase1 2K
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+R1 Vbase1 Vcc 28K
+C2 2 Vbase2 2.2uF
+CE2 0 Vem2 1pF
+C1 1 Vbase1 2.2uF
+CE1 0 Vem1 1pF
+R8 Vcoll1 2 1
+VCC Vcc 0 DC 15V
+RC2 VColl2 Vcc 1K
+RC1 Vcoll1 Vcc 3.3K
+RL 0 Vout 100K
+.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/spice/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..a91f1a6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include-output.net
@@ -0,0 +1,25 @@
+* Spice netlister for gnetlist
+Cout VColl2 Vout 2.2uF
+R5 Vin 1 10
+R4 0 Vbase2 2.8K
+RE2 0 Vem2 100
+Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+A3 .options TEMP=25
+R3 Vbase2 Vcc 28K
+A2 <No valid value attribute found>
+RE1 0 Vem1 100
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
+A1 <No valid value attribute found>
+R2 0 Vbase1 2K
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+R1 Vbase1 Vcc 28K
+C2 2 Vbase2 2.2uF
+CE2 0 Vem2 1pF
+C1 1 Vbase1 2.2uF
+CE1 0 Vem1 1pF
+R8 Vcoll1 2 1
+VCC Vcc 0 DC 15V
+RC2 VColl2 Vcc 1K
+RC1 Vcoll1 Vcc 3.3K
+RL 0 Vout 100K
+.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..a91f1a6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort-output.net
@@ -0,0 +1,25 @@
+* Spice netlister for gnetlist
+Cout VColl2 Vout 2.2uF
+R5 Vin 1 10
+R4 0 Vbase2 2.8K
+RE2 0 Vem2 100
+Q2 VColl2 Vbase2 Vem2 <No valid value attribute found>
+A3 .options TEMP=25
+R3 Vbase2 Vcc 28K
+A2 <No valid value attribute found>
+RE1 0 Vem1 100
+Q1 Vcoll1 Vbase1 Vem1 <No valid value attribute found>
+A1 <No valid value attribute found>
+R2 0 Vbase1 2K
+Vinput Vin 0 DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+R1 Vbase1 Vcc 28K
+C2 2 Vbase2 2.2uF
+CE2 0 Vem2 1pF
+C1 1 Vbase1 2.2uF
+CE1 0 Vem1 1pF
+R8 Vcoll1 2 1
+VCC Vcc 0 DC 15V
+RC2 VColl2 Vcc 1K
+RC1 Vcoll1 Vcc 3.3K
+RL 0 Vout 100K
+.END
diff --git a/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/cascade-output.net b/gnetlist/tests/common/outputs/spice/cascade-output.net
new file mode 100644
index 0000000..a578dfa
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/cascade-output.net
@@ -0,0 +1,10 @@
+* Spice netlister for gnetlist
+AMP2 6 unconnected_pin-1 <No valid value attribute found>
+AMP1 1 2 <No valid value attribute found>
+SOURCE 1 <No valid value attribute found>
+DEFAULTS ERROR_INVALID_PIN <No valid value attribute found>
+MX1 4 5 <No valid value attribute found>
+DEF1 2 3 <No valid value attribute found>
+T1 5 6 <No valid value attribute found>
+FL1 3 4 <No valid value attribute found>
+.END
diff --git a/gnetlist/tests/common/outputs/spice/cascade.retcode b/gnetlist/tests/common/outputs/spice/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/multiequal-output.net b/gnetlist/tests/common/outputs/spice/multiequal-output.net
new file mode 100644
index 0000000..0ed4801
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/multiequal-output.net
@@ -0,0 +1,5 @@
+* Spice netlister for gnetlist
+V1 1 0 DC 1V
+A1 abotol=1e-11
+R1 0 1 20
+.END
diff --git a/gnetlist/tests/common/outputs/spice/multiequal.retcode b/gnetlist/tests/common/outputs/spice/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/netattrib-output.net b/gnetlist/tests/common/outputs/spice/netattrib-output.net
new file mode 100644
index 0000000..f2d3500
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/netattrib-output.net
@@ -0,0 +1,6 @@
+* Spice netlister for gnetlist
+F1 one unconnected_pin-3 <No valid value attribute found>
+U100 unconnected_pin-2 unconnected_pin-1 one ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+U300 one 1 ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+U200 one netattrib ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+.END
diff --git a/gnetlist/tests/common/outputs/spice/netattrib.retcode b/gnetlist/tests/common/outputs/spice/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/powersupply-output.net b/gnetlist/tests/common/outputs/spice/powersupply-output.net
new file mode 100644
index 0000000..f52e908
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/powersupply-output.net
@@ -0,0 +1,14 @@
+* Spice netlister for gnetlist
+F1 two three <No valid value attribute found>
+R2 ten eleven 220
+CONN1 one five 0 <No valid value attribute found>
+C4 eleven nine 1uf
+R1 nine ten nine 5k
+C3 ten nine 22uF
+C2 eight nine 0.1uF
+S1 one two <No valid value attribute found>
+C1 eight nine 2200uF
+T1 three five six seven <No valid value attribute found>
+U2 ten eleven eight <No valid value attribute found>
+U1 eight nine seven six <No valid value attribute found>
+.END
diff --git a/gnetlist/tests/common/outputs/spice/powersupply.retcode b/gnetlist/tests/common/outputs/spice/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/spice/singlenet-output.net b/gnetlist/tests/common/outputs/spice/singlenet-output.net
new file mode 100644
index 0000000..4667f91
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/singlenet-output.net
@@ -0,0 +1,3 @@
+* Spice netlister for gnetlist
+U100 SING_N SING_N SING_N ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN ERROR_INVALID_PIN <No valid value attribute found>
+.END
diff --git a/gnetlist/tests/common/outputs/spice/singlenet.retcode b/gnetlist/tests/common/outputs/spice/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/spice/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/.gitignore b/gnetlist/tests/common/outputs/switcap/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/switcap/JD-output.net b/gnetlist/tests/common/outputs/switcap/JD-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/JD.retcode b/gnetlist/tests/common/outputs/switcap/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Include-output.net b/gnetlist/tests/common/outputs/switcap/JD_Include-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Include-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Include.retcode b/gnetlist/tests/common/outputs/switcap/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Sort-output.net b/gnetlist/tests/common/outputs/switcap/JD_Sort-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Sort-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Sort.retcode b/gnetlist/tests/common/outputs/switcap/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/JD_nomunge-output.net b/gnetlist/tests/common/outputs/switcap/JD_nomunge-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/JD_nomunge-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/Makefile.am b/gnetlist/tests/common/outputs/switcap/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/switcap/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/switcap/SlottedOpamps-output.net
new file mode 100644
index 0000000..e69de29
diff --git a/gnetlist/tests/common/outputs/switcap/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/switcap/SlottedOpamps.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/SlottedOpamps.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/switcap/TwoStageAmp-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/switcap/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/cascade-output.net b/gnetlist/tests/common/outputs/switcap/cascade-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/cascade-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/cascade.retcode b/gnetlist/tests/common/outputs/switcap/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/multiequal-output.net b/gnetlist/tests/common/outputs/switcap/multiequal-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/multiequal-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/multiequal.retcode b/gnetlist/tests/common/outputs/switcap/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/netattrib-output.net b/gnetlist/tests/common/outputs/switcap/netattrib-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/netattrib-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/netattrib.retcode b/gnetlist/tests/common/outputs/switcap/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/powersupply-output.net b/gnetlist/tests/common/outputs/switcap/powersupply-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/powersupply-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/powersupply.retcode b/gnetlist/tests/common/outputs/switcap/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/switcap/singlenet-output.net b/gnetlist/tests/common/outputs/switcap/singlenet-output.net
new file mode 100644
index 0000000..03bb317
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/singlenet-output.net
@@ -0,0 +1,15 @@
+/* Switcap netlist produced by gnetlist (part of gEDA) */
+/* See http://www.geda.seul.org for more information.  */
+/* Switcap backend written by Dan McMahill             */
+
+
+TIMING;
+END;
+
+CIRCUIT;
+END;
+
+
+
+/* End of SWITCAP netlist */
+END;
diff --git a/gnetlist/tests/common/outputs/switcap/singlenet.retcode b/gnetlist/tests/common/outputs/switcap/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/switcap/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/systemc/.gitignore b/gnetlist/tests/common/outputs/systemc/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/systemc/JD.retcode b/gnetlist/tests/common/outputs/systemc/JD.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/JD.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Include.retcode b/gnetlist/tests/common/outputs/systemc/JD_Include.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/JD_Include.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Sort.retcode b/gnetlist/tests/common/outputs/systemc/JD_Sort.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/JD_Sort.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/Makefile.am b/gnetlist/tests/common/outputs/systemc/Makefile.am
new file mode 100644
index 0000000..991d090
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/Makefile.am
@@ -0,0 +1,15 @@
+EXTRA_DIST= \
+	cascade.retcode \
+	JD_Include_nomunge.retcode \
+	JD_Include.retcode \
+	JD.retcode \
+	JD_Sort_nomunge.retcode \
+	JD_Sort.retcode \
+	multiequal.retcode \
+	netattrib.retcode \
+	powersupply.retcode \
+	singlenet.retcode \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/systemc/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/systemc/SlottedOpamps.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/SlottedOpamps.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/systemc/TwoStageAmp.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/cascade.retcode b/gnetlist/tests/common/outputs/systemc/cascade.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/cascade.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/multiequal.retcode b/gnetlist/tests/common/outputs/systemc/multiequal.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/multiequal.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/netattrib.retcode b/gnetlist/tests/common/outputs/systemc/netattrib.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/netattrib.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/powersupply.retcode b/gnetlist/tests/common/outputs/systemc/powersupply.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/powersupply.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/systemc/singlenet.retcode b/gnetlist/tests/common/outputs/systemc/singlenet.retcode
new file mode 100644
index 0000000..d00491f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/systemc/singlenet.retcode
@@ -0,0 +1 @@
+1
diff --git a/gnetlist/tests/common/outputs/tango/.gitignore b/gnetlist/tests/common/outputs/tango/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/tango/JD-output.net b/gnetlist/tests/common/outputs/tango/JD-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/JD.retcode b/gnetlist/tests/common/outputs/tango/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include-output.net b/gnetlist/tests/common/outputs/tango/JD_Include-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Include-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include.retcode b/gnetlist/tests/common/outputs/tango/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort-output.net b/gnetlist/tests/common/outputs/tango/JD_Sort-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort.retcode b/gnetlist/tests/common/outputs/tango/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net b/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
new file mode 100644
index 0000000..e4c961a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/JD_nomunge-output.net
@@ -0,0 +1,122 @@
+[
+V1
+none
+vpulse
+pulse 3.3 0 1u 10p 10p 1.25u 2.5u
+
+]
+[
+Cm
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+Rt
+PATTERN
+RESISTOR
+1k
+
+]
+[
+M1
+PATTERN
+PMOS_TRANSISTOR
+
+
+]
+[
+X1
+PATTERN
+LVD
+
+
+]
+[
+Rlp
+PATTERN
+RESISTOR
+1meg
+
+]
+[
+Vdd
+none
+VOLTAGE_SOURCE
+DC 3.3V
+
+]
+[
+Rlm
+PATTERN
+RESISTOR
+500k
+
+]
+[
+Cp
+PATTERN
+CAPACITOR
+20p
+
+]
+[
+Rb
+PATTERN
+RESISTOR
+5.6k
+
+]
+(
+Vdd1
+Rlp-2
+M1-B
+M1-S
+Vdd-1
+X1-6
+)
+(
+GND
+Cm-2
+Cp-2
+Rlm-2
+Vdd-2
+V1-2
+Rb-1
+X1-7
+X1-2
+)
+(
+LVH
+Rb-2
+M1-D
+M1-G
+X1-3
+)
+(
+i
+V1-1
+X1-1
+)
+(
+p
+Cp-1
+Rt-1
+Rlp-1
+X1-5
+)
+(
+m
+Cm-1
+Rlm-1
+Rt-2
+X1-4
+)
diff --git a/gnetlist/tests/common/outputs/tango/Makefile.am b/gnetlist/tests/common/outputs/tango/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/tango/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/tango/SlottedOpamps-output.net
new file mode 100644
index 0000000..49292c0
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/SlottedOpamps-output.net
@@ -0,0 +1,46 @@
+[
+U1
+PATTERN
+LM324
+
+
+]
+(
+minusin_slot4_pin13_b
+U1-13
+)
+(
+plusin_slot4_pin12_a
+U1-12
+)
+(
+minusin_slot3_pin_b
+U1-9
+)
+(
+plusin_slot3_pin10_a
+U1-10
+)
+(
+minusin_slot2_pin6_b
+U1-6
+)
+(
+plusin_slot2_pin5_a
+U1-5
+)
+(
+samenet_output_c
+U1-14
+U1-8
+U1-7
+U1-1
+)
+(
+minusin_slot1_pin_b
+U1-2
+)
+(
+plusin_slot1_pin3_a
+U1-3
+)
diff --git a/gnetlist/tests/common/outputs/tango/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/tango/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
new file mode 100644
index 0000000..42312fd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp-output.net
@@ -0,0 +1,239 @@
+[
+Cout
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+R5
+PATTERN
+RESISTOR
+10
+
+]
+[
+R4
+PATTERN
+RESISTOR
+2.8K
+
+]
+[
+RE2
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q2
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A3
+PATTERN
+directive
+.options TEMP=25
+
+]
+[
+R3
+PATTERN
+RESISTOR
+28K
+
+]
+[
+A2
+PATTERN
+include
+
+
+]
+[
+RE1
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q1
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+R2
+PATTERN
+RESISTOR
+2K
+
+]
+[
+Vinput
+none
+vsin
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+
+]
+[
+R1
+PATTERN
+RESISTOR
+28K
+
+]
+[
+C2
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE2
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+C1
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE1
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+R8
+PATTERN
+RESISTOR
+1
+
+]
+[
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
+
+]
+[
+RC2
+PATTERN
+RESISTOR
+1K
+
+]
+[
+RC1
+PATTERN
+RESISTOR
+3.3K
+
+]
+[
+RL
+PATTERN
+RESISTOR
+100K
+
+]
+(
+unnamed_net2
+C2-1
+R8-2
+)
+(
+Vbase2
+R3-1
+C2-2
+R4-2
+Q2-2
+)
+(
+Vem2
+CE2-2
+RE2-2
+Q2-1
+)
+(
+Vout
+Cout-2
+RL-2
+)
+(
+VColl2
+Q2-3
+Cout-1
+RC2-1
+)
+(
+GND
+R4-1
+CE2-1
+RE2-1
+VCC-2
+Vinput-2
+CE1-1
+RL-1
+RE1-1
+R2-1
+)
+(
+Vcc
+R3-2
+RC1-2
+VCC-1
+RC2-2
+R1-2
+)
+(
+Vin
+Vinput-1
+R5-1
+)
+(
+unnamed_net1
+C1-1
+R5-2
+)
+(
+Vbase1
+C1-2
+R2-2
+R1-1
+Q1-2
+)
+(
+Vem1
+CE1-2
+RE1-2
+Q1-1
+)
+(
+Vcoll1
+R8-1
+RC1-1
+Q1-3
+)
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/tango/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..42312fd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include-output.net
@@ -0,0 +1,239 @@
+[
+Cout
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+R5
+PATTERN
+RESISTOR
+10
+
+]
+[
+R4
+PATTERN
+RESISTOR
+2.8K
+
+]
+[
+RE2
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q2
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A3
+PATTERN
+directive
+.options TEMP=25
+
+]
+[
+R3
+PATTERN
+RESISTOR
+28K
+
+]
+[
+A2
+PATTERN
+include
+
+
+]
+[
+RE1
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q1
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+R2
+PATTERN
+RESISTOR
+2K
+
+]
+[
+Vinput
+none
+vsin
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+
+]
+[
+R1
+PATTERN
+RESISTOR
+28K
+
+]
+[
+C2
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE2
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+C1
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE1
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+R8
+PATTERN
+RESISTOR
+1
+
+]
+[
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
+
+]
+[
+RC2
+PATTERN
+RESISTOR
+1K
+
+]
+[
+RC1
+PATTERN
+RESISTOR
+3.3K
+
+]
+[
+RL
+PATTERN
+RESISTOR
+100K
+
+]
+(
+unnamed_net2
+C2-1
+R8-2
+)
+(
+Vbase2
+R3-1
+C2-2
+R4-2
+Q2-2
+)
+(
+Vem2
+CE2-2
+RE2-2
+Q2-1
+)
+(
+Vout
+Cout-2
+RL-2
+)
+(
+VColl2
+Q2-3
+Cout-1
+RC2-1
+)
+(
+GND
+R4-1
+CE2-1
+RE2-1
+VCC-2
+Vinput-2
+CE1-1
+RL-1
+RE1-1
+R2-1
+)
+(
+Vcc
+R3-2
+RC1-2
+VCC-1
+RC2-2
+R1-2
+)
+(
+Vin
+Vinput-1
+R5-1
+)
+(
+unnamed_net1
+C1-1
+R5-2
+)
+(
+Vbase1
+C1-2
+R2-2
+R1-1
+Q1-2
+)
+(
+Vem1
+CE1-2
+RE1-2
+Q1-1
+)
+(
+Vcoll1
+R8-1
+RC1-1
+Q1-3
+)
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..42312fd
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort-output.net
@@ -0,0 +1,239 @@
+[
+Cout
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+R5
+PATTERN
+RESISTOR
+10
+
+]
+[
+R4
+PATTERN
+RESISTOR
+2.8K
+
+]
+[
+RE2
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q2
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A3
+PATTERN
+directive
+.options TEMP=25
+
+]
+[
+R3
+PATTERN
+RESISTOR
+28K
+
+]
+[
+A2
+PATTERN
+include
+
+
+]
+[
+RE1
+PATTERN
+RESISTOR
+100
+
+]
+[
+Q1
+PATTERN
+NPN_TRANSISTOR
+
+
+]
+[
+A1
+PATTERN
+model
+
+
+]
+[
+R2
+PATTERN
+RESISTOR
+2K
+
+]
+[
+Vinput
+none
+vsin
+DC 1.6V AC 10MV SIN(0 1MV 1KHZ)
+
+]
+[
+R1
+PATTERN
+RESISTOR
+28K
+
+]
+[
+C2
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE2
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+C1
+PATTERN
+CAPACITOR
+2.2uF
+
+]
+[
+CE1
+PATTERN
+CAPACITOR
+1pF
+
+]
+[
+R8
+PATTERN
+RESISTOR
+1
+
+]
+[
+VCC
+none
+VOLTAGE_SOURCE
+DC 15V
+
+]
+[
+RC2
+PATTERN
+RESISTOR
+1K
+
+]
+[
+RC1
+PATTERN
+RESISTOR
+3.3K
+
+]
+[
+RL
+PATTERN
+RESISTOR
+100K
+
+]
+(
+unnamed_net2
+C2-1
+R8-2
+)
+(
+Vbase2
+R3-1
+C2-2
+R4-2
+Q2-2
+)
+(
+Vem2
+CE2-2
+RE2-2
+Q2-1
+)
+(
+Vout
+Cout-2
+RL-2
+)
+(
+VColl2
+Q2-3
+Cout-1
+RC2-1
+)
+(
+GND
+R4-1
+CE2-1
+RE2-1
+VCC-2
+Vinput-2
+CE1-1
+RL-1
+RE1-1
+R2-1
+)
+(
+Vcc
+R3-2
+RC1-2
+VCC-1
+RC2-2
+R1-2
+)
+(
+Vin
+Vinput-1
+R5-1
+)
+(
+unnamed_net1
+C1-1
+R5-2
+)
+(
+Vbase1
+C1-2
+R2-2
+R1-1
+Q1-2
+)
+(
+Vem1
+CE1-2
+RE1-2
+Q1-1
+)
+(
+Vcoll1
+R8-1
+RC1-1
+Q1-3
+)
diff --git a/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/cascade-output.net b/gnetlist/tests/common/outputs/tango/cascade-output.net
new file mode 100644
index 0000000..f21920b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/cascade-output.net
@@ -0,0 +1,90 @@
+[
+AMP2
+none
+cascade-amp
+
+
+]
+[
+AMP1
+none
+cascade-amp
+
+
+]
+[
+SOURCE
+none
+cascade-source
+
+
+]
+[
+DEFAULTS
+PATTERN
+cascade-defaults-top
+
+
+]
+[
+MX1
+none
+cascade-mixer
+
+
+]
+[
+DEF1
+none
+cascade-defaults
+
+
+]
+[
+T1
+none
+cascade-transformer
+
+
+]
+[
+FL1
+none
+cascade-filter
+
+
+]
+(
+unnamed_net6
+AMP2-1
+T1-2
+)
+(
+unnamed_net5
+T1-1
+MX1-2
+)
+(
+unnamed_net4
+MX1-1
+FL1-2
+)
+(
+unnamed_net3
+FL1-1
+DEF1-2
+)
+(
+unnamed_net2
+DEF1-1
+AMP1-2
+)
+(
+unnamed_net1
+AMP1-1
+SOURCE-1
+)
+(
+GND
+DEFAULTS-1
+)
diff --git a/gnetlist/tests/common/outputs/tango/cascade.retcode b/gnetlist/tests/common/outputs/tango/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/multiequal-output.net b/gnetlist/tests/common/outputs/tango/multiequal-output.net
new file mode 100644
index 0000000..96b14bc
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/multiequal-output.net
@@ -0,0 +1,31 @@
+[
+V1
+none
+VOLTAGE_SOURCE
+DC 1V
+
+]
+[
+A1
+PATTERN
+options
+abotol=1e-11
+
+]
+[
+R1
+PATTERN
+RESISTOR
+20
+
+]
+(
+GND
+V1-2
+R1-1
+)
+(
+unnamed_net1
+V1-1
+R1-2
+)
diff --git a/gnetlist/tests/common/outputs/tango/multiequal.retcode b/gnetlist/tests/common/outputs/tango/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/netattrib-output.net b/gnetlist/tests/common/outputs/tango/netattrib-output.net
new file mode 100644
index 0000000..6ef1d9d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/netattrib-output.net
@@ -0,0 +1,56 @@
+[
+F1
+PATTERN
+FUSE
+
+
+]
+[
+U100
+DIP14
+7400
+
+
+]
+[
+U300
+DIP14
+7404
+
+
+]
+[
+U200
+DIP14
+7404
+
+
+]
+(
+unnamed_net1
+U300-2
+)
+(
+netattrib
+U200-2
+U100-5
+)
+(
+GND
+U300-7
+U200-7
+U100-7
+)
+(
+Vcc
+U300-14
+U200-14
+U100-14
+)
+(
+one
+F1-1
+U300-1
+U200-1
+U100-3
+)
diff --git a/gnetlist/tests/common/outputs/tango/netattrib.retcode b/gnetlist/tests/common/outputs/tango/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/powersupply-output.net b/gnetlist/tests/common/outputs/tango/powersupply-output.net
new file mode 100644
index 0000000..96576c4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/powersupply-output.net
@@ -0,0 +1,148 @@
+[
+F1
+PATTERN
+FUSE
+
+
+]
+[
+R2
+PATTERN
+RESISTOR
+220
+
+]
+[
+CONN1
+PATTERN
+MAINS_CONNECTOR
+
+
+]
+[
+C4
+PATTERN
+POLARIZED_CAPACITOR
+1uf
+
+]
+[
+R1
+PATTERN
+VARIABLE_RESISTOR
+5k
+
+]
+[
+C3
+PATTERN
+POLARIZED_CAPACITOR
+22uF
+
+]
+[
+C2
+PATTERN
+POLARIZED_CAPACITOR
+0.1uF
+
+]
+[
+S1
+PATTERN
+SPST
+
+
+]
+[
+C1
+PATTERN
+POLARIZED_CAPACITOR
+2200uF
+
+]
+[
+T1
+PATTERN
+transformer
+
+
+]
+[
+U2
+PATTERN
+LM317
+
+
+]
+[
+U1
+PATTERN
+DIODE-BRIDGE
+
+
+]
+(
+ten
+U2-1
+R1-2
+C3-1
+R2-1
+)
+(
+eleven
+U2-2
+C4-1
+R2-2
+)
+(
+GND
+CONN1-3
+)
+(
+one
+S1-1
+CONN1-1
+)
+(
+five
+CONN1-2
+T1-2
+)
+(
+three
+T1-1
+F1-2
+)
+(
+two
+S1-2
+F1-1
+)
+(
+six
+T1-3
+U1-4
+)
+(
+seven
+T1-4
+U1-3
+)
+(
+nine
+C4-2
+C3-2
+R1-3
+R1-1
+C2-2
+C1-2
+U1-2
+)
+(
+eight
+U2-3
+C2-1
+C1-1
+U1-1
+)
diff --git a/gnetlist/tests/common/outputs/tango/powersupply.retcode b/gnetlist/tests/common/outputs/tango/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/tango/singlenet-output.net b/gnetlist/tests/common/outputs/tango/singlenet-output.net
new file mode 100644
index 0000000..3d94d3e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/singlenet-output.net
@@ -0,0 +1,29 @@
+[
+U100
+DIP14
+7400
+
+
+]
+(
+SING_N_2
+U100-1
+U100-3
+)
+(
+GND
+U100-7
+)
+(
+Vcc
+U100-14
+)
+(
+SING_N
+U100-4
+U100-5
+U100-10
+U100-8
+U100-9
+U100-6
+)
diff --git a/gnetlist/tests/common/outputs/tango/singlenet.retcode b/gnetlist/tests/common/outputs/tango/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/tango/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/.gitignore b/gnetlist/tests/common/outputs/vams/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/vams/JD-output.net b/gnetlist/tests/common/outputs/vams/JD-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD.retcode b/gnetlist/tests/common/outputs/vams/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include-output.net b/gnetlist/tests/common/outputs/vams/JD_Include-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Include-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include.retcode b/gnetlist/tests/common/outputs/vams/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort-output.net b/gnetlist/tests/common/outputs/vams/JD_Sort-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort.retcode b/gnetlist/tests/common/outputs/vams/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
new file mode 100644
index 0000000..103b337
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/JD_nomunge-output.net
@@ -0,0 +1,94 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown Vdd1 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown LVH 	:  unknown;
+	unknown i 	:  unknown;
+	unknown p 	:  unknown;
+	unknown m 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY vpulse
+	GENERIC MAP (
+			value => pulse 3.3 0 1u 10p 10p 1.25u 2.5u)
+	PORT MAP (	1 => i,
+			2 => GND);
+ 
+  Cm : ENTITY CAPACITOR
+	GENERIC MAP (
+			device => CAPACITOR, 
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => m,
+			2 => GND);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			file => ./models/openIP_5.cir, 
+			model-name => unknown_LVD, 
+			device => model)
+;
+ 
+  Rt : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1k)
+	PORT MAP (	2 => m,
+			1 => p);
+ 
+  M1 : ENTITY PMOS_TRANSISTOR
+	GENERIC MAP (
+			m => 36, 
+			l => 3u, 
+			w => 3u, 
+			model-name => pch)
+	PORT MAP (	S => Vdd1,
+			B => Vdd1,
+			D => LVH,
+			G => LVH);
+ 
+  X1 : ENTITY LVD
+	GENERIC MAP (
+			model-name => unknown_LVD)
+	PORT MAP (	4 => m,
+			5 => p,
+			1 => i,
+			3 => LVH,
+			2 => GND,
+			6 => Vdd1,
+			7 => GND);
+ 
+  Rlp : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 1meg)
+	PORT MAP (	2 => Vdd1,
+			1 => p);
+ 
+  Vdd : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 3.3V)
+	PORT MAP (	1 => Vdd1,
+			2 => GND);
+ 
+  Rlm : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 500k)
+	PORT MAP (	2 => GND,
+			1 => m);
+ 
+  Cp : ENTITY CAPACITOR
+	GENERIC MAP (
+			value => 20p, 
+			symversion => 0.1)
+	PORT MAP (	1 => p,
+			2 => GND);
+ 
+  Rb : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 5.6k)
+	PORT MAP (	2 => LVH,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/Makefile.am b/gnetlist/tests/common/outputs/vams/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/vams/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/vams/SlottedOpamps-output.net
new file mode 100644
index 0000000..0d803d8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/SlottedOpamps-output.net
@@ -0,0 +1,33 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown minusin_slot4_pin13_b 	:  unknown;
+	unknown plusin_slot4_pin12_a 	:  unknown;
+	unknown minusin_slot3_pin_b 	:  unknown;
+	unknown plusin_slot3_pin10_a 	:  unknown;
+	unknown minusin_slot2_pin6_b 	:  unknown;
+	unknown plusin_slot2_pin5_a 	:  unknown;
+	unknown samenet_output_c 	:  unknown;
+	unknown minusin_slot1_pin_b 	:  unknown;
+	unknown plusin_slot1_pin3_a 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  U1 : ENTITY LM324
+	GENERIC MAP (
+			slot => 1, 
+			device => LM324)
+	PORT MAP (	3 => plusin_slot1_pin3_a,
+			2 => minusin_slot1_pin_b,
+			1 => samenet_output_c,
+			5 => plusin_slot2_pin5_a,
+			6 => minusin_slot2_pin6_b,
+			7 => samenet_output_c,
+			10 => plusin_slot3_pin10_a,
+			9 => minusin_slot3_pin_b,
+			8 => samenet_output_c,
+			12 => plusin_slot4_pin12_a,
+			13 => minusin_slot4_pin13_b,
+			14 => samenet_output_c);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/vams/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
new file mode 100644
index 0000000..95a10a5
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp-output.net
@@ -0,0 +1,187 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown unnamed_net2 	:  unknown;
+	unknown Vbase2 	:  unknown;
+	unknown Vem2 	:  unknown;
+	unknown Vout 	:  unknown;
+	unknown VColl2 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown Vcc 	:  unknown;
+	unknown Vin 	:  unknown;
+	unknown unnamed_net1 	:  unknown;
+	unknown Vbase1 	:  unknown;
+	unknown Vem1 	:  unknown;
+	unknown Vcoll1 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  Cout : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => VColl2,
+			2 => Vout);
+ 
+  R5 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 10)
+	PORT MAP (	2 => unnamed_net1,
+			1 => Vin);
+ 
+  R4 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2.8K)
+	PORT MAP (	2 => Vbase2,
+			1 => GND);
+ 
+  RE2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem2,
+			1 => GND);
+ 
+  Q2 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => VColl2,
+			1 => Vem2,
+			2 => Vbase2);
+ 
+  A3 : ENTITY directive
+	GENERIC MAP (
+			device => directive, 
+			value => .options TEMP=25)
+;
+ 
+  R3 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase2);
+ 
+  A2 : ENTITY include
+	GENERIC MAP (
+			device => include, 
+			file => Simulation.cmd)
+;
+ 
+  RE1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem1,
+			1 => GND);
+ 
+  Q1 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => Vcoll1,
+			1 => Vem1,
+			2 => Vbase1);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			device => model, 
+			file => ./models/2N3904.mod, 
+			model-name => 2N3904)
+;
+ 
+  R2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2K)
+	PORT MAP (	2 => Vbase1,
+			1 => GND);
+ 
+  Vinput : ENTITY vsin
+	GENERIC MAP (
+			footprint => none, 
+			device => vsin, 
+			value => DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+	PORT MAP (	1 => Vin,
+			2 => GND);
+ 
+  R1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase1);
+ 
+  C2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net2,
+			2 => Vbase2);
+ 
+  CE2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem2);
+ 
+  C1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net1,
+			2 => Vbase1);
+ 
+  CE1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem1);
+ 
+  R8 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1)
+	PORT MAP (	2 => unnamed_net2,
+			1 => Vcoll1);
+ 
+  VCC : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			footprint => none, 
+			device => VOLTAGE_SOURCE, 
+			value => DC 15V)
+	PORT MAP (	1 => Vcc,
+			2 => GND);
+ 
+  RC2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1K)
+	PORT MAP (	2 => Vcc,
+			1 => VColl2);
+ 
+  RC1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 3.3K)
+	PORT MAP (	2 => Vcc,
+			1 => Vcoll1);
+ 
+  RL : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100K)
+	PORT MAP (	2 => Vout,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/vams/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..95a10a5
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include-output.net
@@ -0,0 +1,187 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown unnamed_net2 	:  unknown;
+	unknown Vbase2 	:  unknown;
+	unknown Vem2 	:  unknown;
+	unknown Vout 	:  unknown;
+	unknown VColl2 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown Vcc 	:  unknown;
+	unknown Vin 	:  unknown;
+	unknown unnamed_net1 	:  unknown;
+	unknown Vbase1 	:  unknown;
+	unknown Vem1 	:  unknown;
+	unknown Vcoll1 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  Cout : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => VColl2,
+			2 => Vout);
+ 
+  R5 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 10)
+	PORT MAP (	2 => unnamed_net1,
+			1 => Vin);
+ 
+  R4 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2.8K)
+	PORT MAP (	2 => Vbase2,
+			1 => GND);
+ 
+  RE2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem2,
+			1 => GND);
+ 
+  Q2 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => VColl2,
+			1 => Vem2,
+			2 => Vbase2);
+ 
+  A3 : ENTITY directive
+	GENERIC MAP (
+			device => directive, 
+			value => .options TEMP=25)
+;
+ 
+  R3 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase2);
+ 
+  A2 : ENTITY include
+	GENERIC MAP (
+			device => include, 
+			file => Simulation.cmd)
+;
+ 
+  RE1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem1,
+			1 => GND);
+ 
+  Q1 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => Vcoll1,
+			1 => Vem1,
+			2 => Vbase1);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			device => model, 
+			file => ./models/2N3904.mod, 
+			model-name => 2N3904)
+;
+ 
+  R2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2K)
+	PORT MAP (	2 => Vbase1,
+			1 => GND);
+ 
+  Vinput : ENTITY vsin
+	GENERIC MAP (
+			footprint => none, 
+			device => vsin, 
+			value => DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+	PORT MAP (	1 => Vin,
+			2 => GND);
+ 
+  R1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase1);
+ 
+  C2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net2,
+			2 => Vbase2);
+ 
+  CE2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem2);
+ 
+  C1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net1,
+			2 => Vbase1);
+ 
+  CE1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem1);
+ 
+  R8 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1)
+	PORT MAP (	2 => unnamed_net2,
+			1 => Vcoll1);
+ 
+  VCC : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			footprint => none, 
+			device => VOLTAGE_SOURCE, 
+			value => DC 15V)
+	PORT MAP (	1 => Vcc,
+			2 => GND);
+ 
+  RC2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1K)
+	PORT MAP (	2 => Vcc,
+			1 => VColl2);
+ 
+  RC1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 3.3K)
+	PORT MAP (	2 => Vcc,
+			1 => Vcoll1);
+ 
+  RL : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100K)
+	PORT MAP (	2 => Vout,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..95a10a5
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort-output.net
@@ -0,0 +1,187 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown unnamed_net2 	:  unknown;
+	unknown Vbase2 	:  unknown;
+	unknown Vem2 	:  unknown;
+	unknown Vout 	:  unknown;
+	unknown VColl2 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown Vcc 	:  unknown;
+	unknown Vin 	:  unknown;
+	unknown unnamed_net1 	:  unknown;
+	unknown Vbase1 	:  unknown;
+	unknown Vem1 	:  unknown;
+	unknown Vcoll1 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  Cout : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => VColl2,
+			2 => Vout);
+ 
+  R5 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 10)
+	PORT MAP (	2 => unnamed_net1,
+			1 => Vin);
+ 
+  R4 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2.8K)
+	PORT MAP (	2 => Vbase2,
+			1 => GND);
+ 
+  RE2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem2,
+			1 => GND);
+ 
+  Q2 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => VColl2,
+			1 => Vem2,
+			2 => Vbase2);
+ 
+  A3 : ENTITY directive
+	GENERIC MAP (
+			device => directive, 
+			value => .options TEMP=25)
+;
+ 
+  R3 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase2);
+ 
+  A2 : ENTITY include
+	GENERIC MAP (
+			device => include, 
+			file => Simulation.cmd)
+;
+ 
+  RE1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100)
+	PORT MAP (	2 => Vem1,
+			1 => GND);
+ 
+  Q1 : ENTITY NPN_TRANSISTOR
+	GENERIC MAP (
+			device => NPN_TRANSISTOR, 
+			model-name => 2N3904)
+	PORT MAP (	3 => Vcoll1,
+			1 => Vem1,
+			2 => Vbase1);
+ 
+  A1 : ENTITY model
+	GENERIC MAP (
+			device => model, 
+			file => ./models/2N3904.mod, 
+			model-name => 2N3904)
+;
+ 
+  R2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 2K)
+	PORT MAP (	2 => Vbase1,
+			1 => GND);
+ 
+  Vinput : ENTITY vsin
+	GENERIC MAP (
+			footprint => none, 
+			device => vsin, 
+			value => DC 1.6V AC 10MV SIN(0 1MV 1KHZ))
+	PORT MAP (	1 => Vin,
+			2 => GND);
+ 
+  R1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 28K)
+	PORT MAP (	2 => Vcc,
+			1 => Vbase1);
+ 
+  C2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net2,
+			2 => Vbase2);
+ 
+  CE2 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem2);
+ 
+  C1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 2.2uF)
+	PORT MAP (	1 => unnamed_net1,
+			2 => Vbase1);
+ 
+  CE1 : ENTITY CAPACITOR
+	GENERIC MAP (
+			symversion => 0.1, 
+			device => CAPACITOR, 
+			value => 1pF)
+	PORT MAP (	1 => GND,
+			2 => Vem1);
+ 
+  R8 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1)
+	PORT MAP (	2 => unnamed_net2,
+			1 => Vcoll1);
+ 
+  VCC : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			footprint => none, 
+			device => VOLTAGE_SOURCE, 
+			value => DC 15V)
+	PORT MAP (	1 => Vcc,
+			2 => GND);
+ 
+  RC2 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 1K)
+	PORT MAP (	2 => Vcc,
+			1 => VColl2);
+ 
+  RC1 : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 3.3K)
+	PORT MAP (	2 => Vcc,
+			1 => Vcoll1);
+ 
+  RL : ENTITY RESISTOR
+	GENERIC MAP (
+			device => RESISTOR, 
+			value => 100K)
+	PORT MAP (	2 => Vout,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/cascade-output.net b/gnetlist/tests/common/outputs/vams/cascade-output.net
new file mode 100644
index 0000000..9e52aae
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/cascade-output.net
@@ -0,0 +1,91 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown unnamed_net6 	:  unknown;
+	unknown unnamed_net5 	:  unknown;
+	unknown unnamed_net4 	:  unknown;
+	unknown unnamed_net3 	:  unknown;
+	unknown unnamed_net2 	:  unknown;
+	unknown unnamed_net1 	:  unknown;
+	unknown GND 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  AMP2 : ENTITY cascade-amp
+	GENERIC MAP (
+			IIP3 => 12, 
+			NF => 12, 
+			G => 10, 
+			footprint => none, 
+			device => cascade-amp)
+	PORT MAP (	1 => unnamed_net6,
+			2 => OPEN);
+ 
+  AMP1 : ENTITY cascade-amp
+	GENERIC MAP (
+			IIP3 => -2, 
+			NF => 5, 
+			G => 12, 
+			footprint => none, 
+			device => cascade-amp)
+	PORT MAP (	1 => unnamed_net1,
+			2 => unnamed_net2);
+ 
+  SOURCE : ENTITY cascade-source
+	GENERIC MAP (
+			BW => 1, 
+			CN => 70, 
+			C => 0, 
+			footprint => none, 
+			device => cascade-source)
+	PORT MAP (	1 => unnamed_net1);
+ 
+  DEFAULTS : ENTITY cascade-defaults-top
+	GENERIC MAP (
+			RHO => 0, 
+			ROUT => 50, 
+			RIN => 50, 
+			device => cascade-defaults-top)
+	PORT MAP (	1 => GND);
+ 
+  MX1 : ENTITY cascade-mixer
+	GENERIC MAP (
+			IIP3 => 5, 
+			NF => 15, 
+			G => 12, 
+			device => cascade-mixer, 
+			footprint => none)
+	PORT MAP (	1 => unnamed_net4,
+			2 => unnamed_net5);
+ 
+  DEF1 : ENTITY cascade-defaults
+	GENERIC MAP (
+			footprint => none, 
+			RHO => 0.2, 
+			ROUT => 50, 
+			RIN => 50, 
+			device => cascade-defaults)
+	PORT MAP (	1 => unnamed_net2,
+			2 => unnamed_net3);
+ 
+  T1 : ENTITY cascade-transformer
+	GENERIC MAP (
+			ROUT => 50, 
+			RIN => 50, 
+			NF => 0, 
+			G => 0, 
+			footprint => none, 
+			device => cascade-transformer)
+	PORT MAP (	1 => unnamed_net5,
+			2 => unnamed_net6);
+ 
+  FL1 : ENTITY cascade-filter
+	GENERIC MAP (
+			NF => 5.5, 
+			G => -5.5, 
+			device => cascade-filter, 
+			footprint => none)
+	PORT MAP (	1 => unnamed_net3,
+			2 => unnamed_net4);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/cascade.retcode b/gnetlist/tests/common/outputs/vams/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/multiequal-output.net b/gnetlist/tests/common/outputs/vams/multiequal-output.net
new file mode 100644
index 0000000..52043c4
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/multiequal-output.net
@@ -0,0 +1,26 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown GND 	:  unknown;
+	unknown unnamed_net1 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  V1 : ENTITY VOLTAGE_SOURCE
+	GENERIC MAP (
+			value => DC 1V)
+	PORT MAP (	1 => unnamed_net1,
+			2 => GND);
+ 
+  A1 : ENTITY options
+	GENERIC MAP (
+			value => abotol=1e-11)
+;
+ 
+  R1 : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 20)
+	PORT MAP (	2 => unnamed_net1,
+			1 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/multiequal.retcode b/gnetlist/tests/common/outputs/vams/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/netattrib-output.net b/gnetlist/tests/common/outputs/vams/netattrib-output.net
new file mode 100644
index 0000000..39dc79a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/netattrib-output.net
@@ -0,0 +1,38 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown unnamed_net1 	:  unknown;
+	unknown netattrib 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown Vcc 	:  unknown;
+	unknown one 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  F1 : ENTITY FUSE
+	PORT MAP (	1 => one,
+			2 => OPEN);
+ 
+  U100 : ENTITY 7400
+	GENERIC MAP (
+			net => netattrib:5)
+	PORT MAP (	3 => one,
+			2 => OPEN,
+			1 => OPEN,
+			14 => Vcc,
+			7 => GND,
+			5 => netattrib);
+ 
+  U300 : ENTITY 7404
+	PORT MAP (	1 => one,
+			2 => unnamed_net1,
+			7 => GND,
+			14 => Vcc);
+ 
+  U200 : ENTITY 7404
+	PORT MAP (	1 => one,
+			2 => netattrib,
+			7 => GND,
+			14 => Vcc);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/netattrib.retcode b/gnetlist/tests/common/outputs/vams/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/powersupply-output.net b/gnetlist/tests/common/outputs/vams/powersupply-output.net
new file mode 100644
index 0000000..a90b651
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/powersupply-output.net
@@ -0,0 +1,85 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown ten 	:  unknown;
+	unknown eleven 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown one 	:  unknown;
+	unknown five 	:  unknown;
+	unknown three 	:  unknown;
+	unknown two 	:  unknown;
+	unknown six 	:  unknown;
+	unknown seven 	:  unknown;
+	unknown nine 	:  unknown;
+	unknown eight 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  F1 : ENTITY FUSE
+	PORT MAP (	1 => two,
+			2 => three);
+ 
+  R2 : ENTITY RESISTOR
+	GENERIC MAP (
+			value => 220)
+	PORT MAP (	2 => eleven,
+			1 => ten);
+ 
+  CONN1 : ENTITY MAINS_CONNECTOR
+	PORT MAP (	1 => one,
+			2 => five,
+			3 => GND);
+ 
+  C4 : ENTITY POLARIZED_CAPACITOR
+	GENERIC MAP (
+			value => 1uf)
+	PORT MAP (	1 => eleven,
+			2 => nine);
+ 
+  R1 : ENTITY VARIABLE_RESISTOR
+	GENERIC MAP (
+			value => 5k)
+	PORT MAP (	3 => nine,
+			2 => ten,
+			1 => nine);
+ 
+  C3 : ENTITY POLARIZED_CAPACITOR
+	GENERIC MAP (
+			value => 22uF)
+	PORT MAP (	1 => ten,
+			2 => nine);
+ 
+  C2 : ENTITY POLARIZED_CAPACITOR
+	GENERIC MAP (
+			value => 0.1uF)
+	PORT MAP (	1 => eight,
+			2 => nine);
+ 
+  S1 : ENTITY SPST
+	PORT MAP (	2 => two,
+			1 => one);
+ 
+  C1 : ENTITY POLARIZED_CAPACITOR
+	GENERIC MAP (
+			value => 2200uF)
+	PORT MAP (	1 => eight,
+			2 => nine);
+ 
+  T1 : ENTITY transformer
+	PORT MAP (	2 => five,
+			1 => three,
+			4 => seven,
+			3 => six);
+ 
+  U2 : ENTITY LM317
+	PORT MAP (	2 => eleven,
+			3 => eight,
+			1 => ten);
+ 
+  U1 : ENTITY DIODE-BRIDGE
+	PORT MAP (	1 => eight,
+			2 => nine,
+			3 => seven,
+			4 => six);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/powersupply.retcode b/gnetlist/tests/common/outputs/vams/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vams/singlenet-output.net b/gnetlist/tests/common/outputs/vams/singlenet-output.net
new file mode 100644
index 0000000..c791cd6
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/singlenet-output.net
@@ -0,0 +1,30 @@
+-- Structural VAMS generated by gnetlist
+-- Secondary unit
+
+ARCHITECTURE default_architecture OF default_entity IS
+	unknown SING_N_2 	:  unknown;
+	unknown GND 	:  unknown;
+	unknown Vcc 	:  unknown;
+	unknown SING_N 	:  unknown;
+BEGIN
+-- Architecture statement part
+ 
+  U100 : ENTITY 7400
+	GENERIC MAP (
+			slot => 2)
+	PORT MAP (	6 => SING_N,
+			5 => SING_N,
+			4 => SING_N,
+			14 => Vcc,
+			7 => GND,
+			3 => SING_N_2,
+			2 => OPEN,
+			1 => SING_N_2,
+			14 => Vcc,
+			7 => GND,
+			8 => SING_N,
+			10 => SING_N,
+			9 => SING_N,
+			14 => Vcc,
+			7 => GND);
+END ARCHITECTURE default_architecture;
diff --git a/gnetlist/tests/common/outputs/vams/singlenet.retcode b/gnetlist/tests/common/outputs/vams/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vams/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/.gitignore b/gnetlist/tests/common/outputs/verilog/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/verilog/JD-output.net b/gnetlist/tests/common/outputs/verilog/JD-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD.retcode b/gnetlist/tests/common/outputs/verilog/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include.retcode b/gnetlist/tests/common/outputs/verilog/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort.retcode b/gnetlist/tests/common/outputs/verilog/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
new file mode 100644
index 0000000..0d5313b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/JD_nomunge-output.net
@@ -0,0 +1,87 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire Vdd1 ;
+wire GND ;
+wire LVH ;
+wire i ;
+wire p ;
+wire m ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+vpulse V1 ( 
+    .\1  ( i ),
+    .\2  ( GND )
+    );
+
+CAPACITOR Cm ( 
+    .\1  ( m ),
+    .\2  ( GND )
+    );
+
+model A1 (     );
+
+RESISTOR Rt ( 
+    .\2  ( m ),
+    .\1  ( p )
+    );
+
+PMOS_TRANSISTOR M1 ( 
+    .S ( Vdd1 ),
+    .B ( Vdd1 ),
+    .D ( LVH ),
+    .G ( LVH )
+    );
+
+LVD X1 ( 
+    .\4  ( m ),
+    .\5  ( p ),
+    .\1  ( i ),
+    .\3  ( LVH ),
+    .\2  ( GND ),
+    .\6  ( Vdd1 ),
+    .\7  ( GND )
+    );
+
+RESISTOR Rlp ( 
+    .\2  ( Vdd1 ),
+    .\1  ( p )
+    );
+
+VOLTAGE_SOURCE Vdd ( 
+    .\1  ( Vdd1 ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rlm ( 
+    .\2  ( GND ),
+    .\1  ( m )
+    );
+
+CAPACITOR Cp ( 
+    .\1  ( p ),
+    .\2  ( GND )
+    );
+
+RESISTOR Rb ( 
+    .\2  ( LVH ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/Makefile.am b/gnetlist/tests/common/outputs/verilog/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
new file mode 100644
index 0000000..4522bca
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/SlottedOpamps-output.net
@@ -0,0 +1,46 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire minusin_slot4_pin13_b ;
+wire plusin_slot4_pin12_a ;
+wire minusin_slot3_pin_b ;
+wire plusin_slot3_pin10_a ;
+wire minusin_slot2_pin6_b ;
+wire plusin_slot2_pin5_a ;
+wire samenet_output_c ;
+wire minusin_slot1_pin_b ;
+wire plusin_slot1_pin3_a ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+LM324 U1 ( 
+    .\3  ( plusin_slot1_pin3_a ),
+    .\2  ( minusin_slot1_pin_b ),
+    .\1  ( samenet_output_c ),
+    .\5  ( plusin_slot2_pin5_a ),
+    .\6  ( minusin_slot2_pin6_b ),
+    .\7  ( samenet_output_c ),
+    .\10  ( plusin_slot3_pin10_a ),
+    .\9  ( minusin_slot3_pin_b ),
+    .\8  ( samenet_output_c ),
+    .\12  ( plusin_slot4_pin12_a ),
+    .\13  ( minusin_slot4_pin13_b ),
+    .\14  ( samenet_output_c )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/verilog/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
new file mode 100644
index 0000000..dec17e9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp-output.net
@@ -0,0 +1,142 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire unnamed_net2 ;
+wire Vbase2 ;
+wire Vem2 ;
+wire Vout ;
+wire VColl2 ;
+wire GND ;
+wire Vcc ;
+wire Vin ;
+wire unnamed_net1 ;
+wire Vbase1 ;
+wire Vem1 ;
+wire Vcoll1 ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+CAPACITOR Cout ( 
+    .\1  ( VColl2 ),
+    .\2  ( Vout )
+    );
+
+RESISTOR R5 ( 
+    .\2  ( unnamed_net1 ),
+    .\1  ( Vin )
+    );
+
+RESISTOR R4 ( 
+    .\2  ( Vbase2 ),
+    .\1  ( GND )
+    );
+
+RESISTOR RE2 ( 
+    .\2  ( Vem2 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q2 ( 
+    .\3  ( VColl2 ),
+    .\1  ( Vem2 ),
+    .\2  ( Vbase2 )
+    );
+
+directive A3 (     );
+
+RESISTOR R3 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase2 )
+    );
+
+include A2 (     );
+
+RESISTOR RE1 ( 
+    .\2  ( Vem1 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q1 ( 
+    .\3  ( Vcoll1 ),
+    .\1  ( Vem1 ),
+    .\2  ( Vbase1 )
+    );
+
+model A1 (     );
+
+RESISTOR R2 ( 
+    .\2  ( Vbase1 ),
+    .\1  ( GND )
+    );
+
+vsin Vinput ( 
+    .\1  ( Vin ),
+    .\2  ( GND )
+    );
+
+RESISTOR R1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase1 )
+    );
+
+CAPACITOR C2 ( 
+    .\1  ( unnamed_net2 ),
+    .\2  ( Vbase2 )
+    );
+
+CAPACITOR CE2 ( 
+    .\1  ( GND ),
+    .\2  ( Vem2 )
+    );
+
+CAPACITOR C1 ( 
+    .\1  ( unnamed_net1 ),
+    .\2  ( Vbase1 )
+    );
+
+CAPACITOR CE1 ( 
+    .\1  ( GND ),
+    .\2  ( Vem1 )
+    );
+
+RESISTOR R8 ( 
+    .\2  ( unnamed_net2 ),
+    .\1  ( Vcoll1 )
+    );
+
+VOLTAGE_SOURCE VCC ( 
+    .\1  ( Vcc ),
+    .\2  ( GND )
+    );
+
+RESISTOR RC2 ( 
+    .\2  ( Vcc ),
+    .\1  ( VColl2 )
+    );
+
+RESISTOR RC1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vcoll1 )
+    );
+
+RESISTOR RL ( 
+    .\2  ( Vout ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/verilog/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..dec17e9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include-output.net
@@ -0,0 +1,142 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire unnamed_net2 ;
+wire Vbase2 ;
+wire Vem2 ;
+wire Vout ;
+wire VColl2 ;
+wire GND ;
+wire Vcc ;
+wire Vin ;
+wire unnamed_net1 ;
+wire Vbase1 ;
+wire Vem1 ;
+wire Vcoll1 ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+CAPACITOR Cout ( 
+    .\1  ( VColl2 ),
+    .\2  ( Vout )
+    );
+
+RESISTOR R5 ( 
+    .\2  ( unnamed_net1 ),
+    .\1  ( Vin )
+    );
+
+RESISTOR R4 ( 
+    .\2  ( Vbase2 ),
+    .\1  ( GND )
+    );
+
+RESISTOR RE2 ( 
+    .\2  ( Vem2 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q2 ( 
+    .\3  ( VColl2 ),
+    .\1  ( Vem2 ),
+    .\2  ( Vbase2 )
+    );
+
+directive A3 (     );
+
+RESISTOR R3 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase2 )
+    );
+
+include A2 (     );
+
+RESISTOR RE1 ( 
+    .\2  ( Vem1 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q1 ( 
+    .\3  ( Vcoll1 ),
+    .\1  ( Vem1 ),
+    .\2  ( Vbase1 )
+    );
+
+model A1 (     );
+
+RESISTOR R2 ( 
+    .\2  ( Vbase1 ),
+    .\1  ( GND )
+    );
+
+vsin Vinput ( 
+    .\1  ( Vin ),
+    .\2  ( GND )
+    );
+
+RESISTOR R1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase1 )
+    );
+
+CAPACITOR C2 ( 
+    .\1  ( unnamed_net2 ),
+    .\2  ( Vbase2 )
+    );
+
+CAPACITOR CE2 ( 
+    .\1  ( GND ),
+    .\2  ( Vem2 )
+    );
+
+CAPACITOR C1 ( 
+    .\1  ( unnamed_net1 ),
+    .\2  ( Vbase1 )
+    );
+
+CAPACITOR CE1 ( 
+    .\1  ( GND ),
+    .\2  ( Vem1 )
+    );
+
+RESISTOR R8 ( 
+    .\2  ( unnamed_net2 ),
+    .\1  ( Vcoll1 )
+    );
+
+VOLTAGE_SOURCE VCC ( 
+    .\1  ( Vcc ),
+    .\2  ( GND )
+    );
+
+RESISTOR RC2 ( 
+    .\2  ( Vcc ),
+    .\1  ( VColl2 )
+    );
+
+RESISTOR RC1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vcoll1 )
+    );
+
+RESISTOR RL ( 
+    .\2  ( Vout ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..dec17e9
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort-output.net
@@ -0,0 +1,142 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire unnamed_net2 ;
+wire Vbase2 ;
+wire Vem2 ;
+wire Vout ;
+wire VColl2 ;
+wire GND ;
+wire Vcc ;
+wire Vin ;
+wire unnamed_net1 ;
+wire Vbase1 ;
+wire Vem1 ;
+wire Vcoll1 ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+CAPACITOR Cout ( 
+    .\1  ( VColl2 ),
+    .\2  ( Vout )
+    );
+
+RESISTOR R5 ( 
+    .\2  ( unnamed_net1 ),
+    .\1  ( Vin )
+    );
+
+RESISTOR R4 ( 
+    .\2  ( Vbase2 ),
+    .\1  ( GND )
+    );
+
+RESISTOR RE2 ( 
+    .\2  ( Vem2 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q2 ( 
+    .\3  ( VColl2 ),
+    .\1  ( Vem2 ),
+    .\2  ( Vbase2 )
+    );
+
+directive A3 (     );
+
+RESISTOR R3 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase2 )
+    );
+
+include A2 (     );
+
+RESISTOR RE1 ( 
+    .\2  ( Vem1 ),
+    .\1  ( GND )
+    );
+
+NPN_TRANSISTOR Q1 ( 
+    .\3  ( Vcoll1 ),
+    .\1  ( Vem1 ),
+    .\2  ( Vbase1 )
+    );
+
+model A1 (     );
+
+RESISTOR R2 ( 
+    .\2  ( Vbase1 ),
+    .\1  ( GND )
+    );
+
+vsin Vinput ( 
+    .\1  ( Vin ),
+    .\2  ( GND )
+    );
+
+RESISTOR R1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vbase1 )
+    );
+
+CAPACITOR C2 ( 
+    .\1  ( unnamed_net2 ),
+    .\2  ( Vbase2 )
+    );
+
+CAPACITOR CE2 ( 
+    .\1  ( GND ),
+    .\2  ( Vem2 )
+    );
+
+CAPACITOR C1 ( 
+    .\1  ( unnamed_net1 ),
+    .\2  ( Vbase1 )
+    );
+
+CAPACITOR CE1 ( 
+    .\1  ( GND ),
+    .\2  ( Vem1 )
+    );
+
+RESISTOR R8 ( 
+    .\2  ( unnamed_net2 ),
+    .\1  ( Vcoll1 )
+    );
+
+VOLTAGE_SOURCE VCC ( 
+    .\1  ( Vcc ),
+    .\2  ( GND )
+    );
+
+RESISTOR RC2 ( 
+    .\2  ( Vcc ),
+    .\1  ( VColl2 )
+    );
+
+RESISTOR RC1 ( 
+    .\2  ( Vcc ),
+    .\1  ( Vcoll1 )
+    );
+
+RESISTOR RL ( 
+    .\2  ( Vout ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/cascade-output.net b/gnetlist/tests/common/outputs/verilog/cascade-output.net
new file mode 100644
index 0000000..af96ecc
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/cascade-output.net
@@ -0,0 +1,66 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire unnamed_net6 ;
+wire unnamed_net5 ;
+wire unnamed_net4 ;
+wire unnamed_net3 ;
+wire unnamed_net2 ;
+wire unnamed_net1 ;
+wire GND ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+\cascade-amp  AMP2 ( 
+    .\1  ( unnamed_net6 )
+    );
+
+\cascade-amp  AMP1 ( 
+    .\1  ( unnamed_net1 ),
+    .\2  ( unnamed_net2 )
+    );
+
+\cascade-source  SOURCE ( 
+    .\1  ( unnamed_net1 )
+    );
+
+\cascade-defaults-top  DEFAULTS ( 
+    .\1  ( GND )
+    );
+
+\cascade-mixer  MX1 ( 
+    .\1  ( unnamed_net4 ),
+    .\2  ( unnamed_net5 )
+    );
+
+\cascade-defaults  DEF1 ( 
+    .\1  ( unnamed_net2 ),
+    .\2  ( unnamed_net3 )
+    );
+
+\cascade-transformer  T1 ( 
+    .\1  ( unnamed_net5 ),
+    .\2  ( unnamed_net6 )
+    );
+
+\cascade-filter  FL1 ( 
+    .\1  ( unnamed_net3 ),
+    .\2  ( unnamed_net4 )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/cascade.retcode b/gnetlist/tests/common/outputs/verilog/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/multiequal-output.net b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
new file mode 100644
index 0000000..2d57b47
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/multiequal-output.net
@@ -0,0 +1,36 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire GND ;
+wire unnamed_net1 ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+VOLTAGE_SOURCE V1 ( 
+    .\1  ( unnamed_net1 ),
+    .\2  ( GND )
+    );
+
+options A1 (     );
+
+RESISTOR R1 ( 
+    .\2  ( unnamed_net1 ),
+    .\1  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/multiequal.retcode b/gnetlist/tests/common/outputs/verilog/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/netattrib-output.net b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
new file mode 100644
index 0000000..1e1836c
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/netattrib-output.net
@@ -0,0 +1,52 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire unnamed_net1 ;
+wire netattrib ;
+wire GND ;
+wire Vcc ;
+wire one ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+FUSE F1 ( 
+    .\1  ( one )
+    );
+
+\7400  U100 ( 
+    .\3  ( one ),
+    .\14  ( Vcc ),
+    .\7  ( GND ),
+    .\5  ( netattrib )
+    );
+
+\7404  U300 ( 
+    .\1  ( one ),
+    .\2  ( unnamed_net1 ),
+    .\7  ( GND ),
+    .\14  ( Vcc )
+    );
+
+\7404  U200 ( 
+    .\1  ( one ),
+    .\2  ( netattrib ),
+    .\7  ( GND ),
+    .\14  ( Vcc )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/netattrib.retcode b/gnetlist/tests/common/outputs/verilog/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/powersupply-output.net b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
new file mode 100644
index 0000000..9386f4b
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/powersupply-output.net
@@ -0,0 +1,100 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire ten ;
+wire eleven ;
+wire GND ;
+wire one ;
+wire five ;
+wire three ;
+wire two ;
+wire six ;
+wire seven ;
+wire nine ;
+wire eight ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+FUSE F1 ( 
+    .\1  ( two ),
+    .\2  ( three )
+    );
+
+RESISTOR R2 ( 
+    .\2  ( eleven ),
+    .\1  ( ten )
+    );
+
+MAINS_CONNECTOR CONN1 ( 
+    .\1  ( one ),
+    .\2  ( five ),
+    .\3  ( GND )
+    );
+
+POLARIZED_CAPACITOR C4 ( 
+    .\1  ( eleven ),
+    .\2  ( nine )
+    );
+
+VARIABLE_RESISTOR R1 ( 
+    .\3  ( nine ),
+    .\2  ( ten ),
+    .\1  ( nine )
+    );
+
+POLARIZED_CAPACITOR C3 ( 
+    .\1  ( ten ),
+    .\2  ( nine )
+    );
+
+POLARIZED_CAPACITOR C2 ( 
+    .\1  ( eight ),
+    .\2  ( nine )
+    );
+
+SPST S1 ( 
+    .\2  ( two ),
+    .\1  ( one )
+    );
+
+POLARIZED_CAPACITOR C1 ( 
+    .\1  ( eight ),
+    .\2  ( nine )
+    );
+
+transformer T1 ( 
+    .\2  ( five ),
+    .\1  ( three ),
+    .\4  ( seven ),
+    .\3  ( six )
+    );
+
+LM317 U2 ( 
+    .\2  ( eleven ),
+    .\3  ( eight ),
+    .\1  ( ten )
+    );
+
+\DIODE-BRIDGE  U1 ( 
+    .\1  ( eight ),
+    .\2  ( nine ),
+    .\3  ( seven ),
+    .\4  ( six )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/powersupply.retcode b/gnetlist/tests/common/outputs/verilog/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/verilog/singlenet-output.net b/gnetlist/tests/common/outputs/verilog/singlenet-output.net
new file mode 100644
index 0000000..3790cab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/singlenet-output.net
@@ -0,0 +1,43 @@
+/* structural Verilog generated by gnetlist */
+/* WARNING: This is a generated file, edits */
+/*        made here will be lost next time  */
+/*        you run gnetlist!                 */
+/* Id ..........$Id$ */
+/* Source.......$Source$ */
+/* Revision.....$Revision$ */
+/* Author.......$Author$ */
+
+module \not found  (
+
+      );
+
+/* Port directions begin here */
+
+
+/* Wires from the design */
+wire SING_N_2 ;
+wire GND ;
+wire Vcc ;
+wire SING_N ;
+
+/* continuous assignments */
+
+/* Package instantiations */
+\7400  U100 ( 
+    .\6  ( SING_N ),
+    .\5  ( SING_N ),
+    .\4  ( SING_N ),
+    .\14  ( Vcc ),
+    .\7  ( GND ),
+    .\3  ( SING_N_2 ),
+    .\1  ( SING_N_2 ),
+    .\14  ( Vcc ),
+    .\7  ( GND ),
+    .\8  ( SING_N ),
+    .\10  ( SING_N ),
+    .\9  ( SING_N ),
+    .\14  ( Vcc ),
+    .\7  ( GND )
+    );
+
+endmodule
diff --git a/gnetlist/tests/common/outputs/verilog/singlenet.retcode b/gnetlist/tests/common/outputs/verilog/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/verilog/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/.gitignore b/gnetlist/tests/common/outputs/vhdl/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/vhdl/JD-output.net b/gnetlist/tests/common/outputs/vhdl/JD-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD.retcode b/gnetlist/tests/common/outputs/vhdl/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include.retcode b/gnetlist/tests/common/outputs/vhdl/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort.retcode b/gnetlist/tests/common/outputs/vhdl/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
new file mode 100644
index 0000000..534f455
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/JD_nomunge-output.net
@@ -0,0 +1,103 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT LVD
+    END COMPONENT ;
+
+    COMPONENT PMOS_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT vpulse
+    END COMPONENT ;
+
+    SIGNAL Vdd1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL LVH : Std_Logic;
+    SIGNAL i : Std_Logic;
+    SIGNAL p : Std_Logic;
+    SIGNAL m : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : vpulse
+    PORT MAP (
+        1 => i,
+        2 => GND);
+
+    Cm : CAPACITOR
+    PORT MAP (
+        1 => m,
+        2 => GND);
+
+    A1 : model
+;
+
+    Rt : RESISTOR
+    PORT MAP (
+        2 => m,
+        1 => p);
+
+    M1 : PMOS_TRANSISTOR
+    PORT MAP (
+        S => Vdd1,
+        B => Vdd1,
+        D => LVH,
+        G => LVH);
+
+    X1 : LVD
+    PORT MAP (
+        4 => m,
+        5 => p,
+        1 => i,
+        3 => LVH,
+        2 => GND,
+        6 => Vdd1,
+        7 => GND);
+
+    Rlp : RESISTOR
+    PORT MAP (
+        2 => Vdd1,
+        1 => p);
+
+    Vdd : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vdd1,
+        2 => GND);
+
+    Rlm : RESISTOR
+    PORT MAP (
+        2 => GND,
+        1 => m);
+
+    Cp : CAPACITOR
+    PORT MAP (
+        1 => p,
+        2 => GND);
+
+    Rb : RESISTOR
+    PORT MAP (
+        2 => LVH,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/Makefile.am b/gnetlist/tests/common/outputs/vhdl/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/vhdl/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/vhdl/SlottedOpamps-output.net
new file mode 100644
index 0000000..0cd6b9f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/SlottedOpamps-output.net
@@ -0,0 +1,43 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT LM324
+    END COMPONENT ;
+
+    SIGNAL minusin_slot4_pin13_b : Std_Logic;
+    SIGNAL plusin_slot4_pin12_a : Std_Logic;
+    SIGNAL minusin_slot3_pin_b : Std_Logic;
+    SIGNAL plusin_slot3_pin10_a : Std_Logic;
+    SIGNAL minusin_slot2_pin6_b : Std_Logic;
+    SIGNAL plusin_slot2_pin5_a : Std_Logic;
+    SIGNAL samenet_output_c : Std_Logic;
+    SIGNAL minusin_slot1_pin_b : Std_Logic;
+    SIGNAL plusin_slot1_pin3_a : Std_Logic;
+BEGIN
+-- Architecture statement part
+    U1 : LM324
+    PORT MAP (
+        3 => plusin_slot1_pin3_a,
+        2 => minusin_slot1_pin_b,
+        1 => samenet_output_c,
+        5 => plusin_slot2_pin5_a,
+        6 => minusin_slot2_pin6_b,
+        7 => samenet_output_c,
+        10 => plusin_slot3_pin10_a,
+        9 => minusin_slot3_pin_b,
+        8 => samenet_output_c,
+        12 => plusin_slot4_pin12_a,
+        13 => minusin_slot4_pin13_b,
+        14 => samenet_output_c);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/vhdl/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
new file mode 100644
index 0000000..30a9a84
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp-output.net
@@ -0,0 +1,163 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT vsin
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT NPN_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT include
+    END COMPONENT ;
+
+    COMPONENT directive
+    END COMPONENT ;
+
+    SIGNAL unnamed_net2 : Std_Logic;
+    SIGNAL Vbase2 : Std_Logic;
+    SIGNAL Vem2 : Std_Logic;
+    SIGNAL Vout : Std_Logic;
+    SIGNAL VColl2 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL Vcc : Std_Logic;
+    SIGNAL Vin : Std_Logic;
+    SIGNAL unnamed_net1 : Std_Logic;
+    SIGNAL Vbase1 : Std_Logic;
+    SIGNAL Vem1 : Std_Logic;
+    SIGNAL Vcoll1 : Std_Logic;
+BEGIN
+-- Architecture statement part
+    Cout : CAPACITOR
+    PORT MAP (
+        1 => VColl2,
+        2 => Vout);
+
+    R5 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net1,
+        1 => Vin);
+
+    R4 : RESISTOR
+    PORT MAP (
+        2 => Vbase2,
+        1 => GND);
+
+    RE2 : RESISTOR
+    PORT MAP (
+        2 => Vem2,
+        1 => GND);
+
+    Q2 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => VColl2,
+        1 => Vem2,
+        2 => Vbase2);
+
+    A3 : directive
+;
+
+    R3 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase2);
+
+    A2 : include
+;
+
+    RE1 : RESISTOR
+    PORT MAP (
+        2 => Vem1,
+        1 => GND);
+
+    Q1 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => Vcoll1,
+        1 => Vem1,
+        2 => Vbase1);
+
+    A1 : model
+;
+
+    R2 : RESISTOR
+    PORT MAP (
+        2 => Vbase1,
+        1 => GND);
+
+    Vinput : vsin
+    PORT MAP (
+        1 => Vin,
+        2 => GND);
+
+    R1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase1);
+
+    C2 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net2,
+        2 => Vbase2);
+
+    CE2 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem2);
+
+    C1 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net1,
+        2 => Vbase1);
+
+    CE1 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem1);
+
+    R8 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net2,
+        1 => Vcoll1);
+
+    VCC : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vcc,
+        2 => GND);
+
+    RC2 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => VColl2);
+
+    RC1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vcoll1);
+
+    RL : RESISTOR
+    PORT MAP (
+        2 => Vout,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..30a9a84
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include-output.net
@@ -0,0 +1,163 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT vsin
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT NPN_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT include
+    END COMPONENT ;
+
+    COMPONENT directive
+    END COMPONENT ;
+
+    SIGNAL unnamed_net2 : Std_Logic;
+    SIGNAL Vbase2 : Std_Logic;
+    SIGNAL Vem2 : Std_Logic;
+    SIGNAL Vout : Std_Logic;
+    SIGNAL VColl2 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL Vcc : Std_Logic;
+    SIGNAL Vin : Std_Logic;
+    SIGNAL unnamed_net1 : Std_Logic;
+    SIGNAL Vbase1 : Std_Logic;
+    SIGNAL Vem1 : Std_Logic;
+    SIGNAL Vcoll1 : Std_Logic;
+BEGIN
+-- Architecture statement part
+    Cout : CAPACITOR
+    PORT MAP (
+        1 => VColl2,
+        2 => Vout);
+
+    R5 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net1,
+        1 => Vin);
+
+    R4 : RESISTOR
+    PORT MAP (
+        2 => Vbase2,
+        1 => GND);
+
+    RE2 : RESISTOR
+    PORT MAP (
+        2 => Vem2,
+        1 => GND);
+
+    Q2 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => VColl2,
+        1 => Vem2,
+        2 => Vbase2);
+
+    A3 : directive
+;
+
+    R3 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase2);
+
+    A2 : include
+;
+
+    RE1 : RESISTOR
+    PORT MAP (
+        2 => Vem1,
+        1 => GND);
+
+    Q1 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => Vcoll1,
+        1 => Vem1,
+        2 => Vbase1);
+
+    A1 : model
+;
+
+    R2 : RESISTOR
+    PORT MAP (
+        2 => Vbase1,
+        1 => GND);
+
+    Vinput : vsin
+    PORT MAP (
+        1 => Vin,
+        2 => GND);
+
+    R1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase1);
+
+    C2 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net2,
+        2 => Vbase2);
+
+    CE2 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem2);
+
+    C1 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net1,
+        2 => Vbase1);
+
+    CE1 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem1);
+
+    R8 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net2,
+        1 => Vcoll1);
+
+    VCC : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vcc,
+        2 => GND);
+
+    RC2 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => VColl2);
+
+    RC1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vcoll1);
+
+    RL : RESISTOR
+    PORT MAP (
+        2 => Vout,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..30a9a84
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort-output.net
@@ -0,0 +1,163 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    COMPONENT CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT vsin
+    END COMPONENT ;
+
+    COMPONENT model
+    END COMPONENT ;
+
+    COMPONENT NPN_TRANSISTOR
+    END COMPONENT ;
+
+    COMPONENT include
+    END COMPONENT ;
+
+    COMPONENT directive
+    END COMPONENT ;
+
+    SIGNAL unnamed_net2 : Std_Logic;
+    SIGNAL Vbase2 : Std_Logic;
+    SIGNAL Vem2 : Std_Logic;
+    SIGNAL Vout : Std_Logic;
+    SIGNAL VColl2 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL Vcc : Std_Logic;
+    SIGNAL Vin : Std_Logic;
+    SIGNAL unnamed_net1 : Std_Logic;
+    SIGNAL Vbase1 : Std_Logic;
+    SIGNAL Vem1 : Std_Logic;
+    SIGNAL Vcoll1 : Std_Logic;
+BEGIN
+-- Architecture statement part
+    Cout : CAPACITOR
+    PORT MAP (
+        1 => VColl2,
+        2 => Vout);
+
+    R5 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net1,
+        1 => Vin);
+
+    R4 : RESISTOR
+    PORT MAP (
+        2 => Vbase2,
+        1 => GND);
+
+    RE2 : RESISTOR
+    PORT MAP (
+        2 => Vem2,
+        1 => GND);
+
+    Q2 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => VColl2,
+        1 => Vem2,
+        2 => Vbase2);
+
+    A3 : directive
+;
+
+    R3 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase2);
+
+    A2 : include
+;
+
+    RE1 : RESISTOR
+    PORT MAP (
+        2 => Vem1,
+        1 => GND);
+
+    Q1 : NPN_TRANSISTOR
+    PORT MAP (
+        3 => Vcoll1,
+        1 => Vem1,
+        2 => Vbase1);
+
+    A1 : model
+;
+
+    R2 : RESISTOR
+    PORT MAP (
+        2 => Vbase1,
+        1 => GND);
+
+    Vinput : vsin
+    PORT MAP (
+        1 => Vin,
+        2 => GND);
+
+    R1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vbase1);
+
+    C2 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net2,
+        2 => Vbase2);
+
+    CE2 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem2);
+
+    C1 : CAPACITOR
+    PORT MAP (
+        1 => unnamed_net1,
+        2 => Vbase1);
+
+    CE1 : CAPACITOR
+    PORT MAP (
+        1 => GND,
+        2 => Vem1);
+
+    R8 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net2,
+        1 => Vcoll1);
+
+    VCC : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => Vcc,
+        2 => GND);
+
+    RC2 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => VColl2);
+
+    RC1 : RESISTOR
+    PORT MAP (
+        2 => Vcc,
+        1 => Vcoll1);
+
+    RL : RESISTOR
+    PORT MAP (
+        2 => Vout,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/cascade-output.net b/gnetlist/tests/common/outputs/vhdl/cascade-output.net
new file mode 100644
index 0000000..3ff2e72
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/cascade-output.net
@@ -0,0 +1,82 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT cascade-filter
+    END COMPONENT ;
+
+    COMPONENT cascade-transformer
+    END COMPONENT ;
+
+    COMPONENT cascade-defaults
+    END COMPONENT ;
+
+    COMPONENT cascade-mixer
+    END COMPONENT ;
+
+    COMPONENT cascade-defaults-top
+    END COMPONENT ;
+
+    COMPONENT cascade-source
+    END COMPONENT ;
+
+    COMPONENT cascade-amp
+    END COMPONENT ;
+
+    SIGNAL unnamed_net6 : Std_Logic;
+    SIGNAL unnamed_net5 : Std_Logic;
+    SIGNAL unnamed_net4 : Std_Logic;
+    SIGNAL unnamed_net3 : Std_Logic;
+    SIGNAL unnamed_net2 : Std_Logic;
+    SIGNAL unnamed_net1 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+BEGIN
+-- Architecture statement part
+    AMP2 : cascade-amp
+    PORT MAP (
+        1 => unnamed_net6,
+        2 => OPEN);
+
+    AMP1 : cascade-amp
+    PORT MAP (
+        1 => unnamed_net1,
+        2 => unnamed_net2);
+
+    SOURCE : cascade-source
+    PORT MAP (
+        1 => unnamed_net1);
+
+    DEFAULTS : cascade-defaults-top
+    PORT MAP (
+        1 => GND);
+
+    MX1 : cascade-mixer
+    PORT MAP (
+        1 => unnamed_net4,
+        2 => unnamed_net5);
+
+    DEF1 : cascade-defaults
+    PORT MAP (
+        1 => unnamed_net2,
+        2 => unnamed_net3);
+
+    T1 : cascade-transformer
+    PORT MAP (
+        1 => unnamed_net5,
+        2 => unnamed_net6);
+
+    FL1 : cascade-filter
+    PORT MAP (
+        1 => unnamed_net3,
+        2 => unnamed_net4);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/cascade.retcode b/gnetlist/tests/common/outputs/vhdl/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/multiequal-output.net b/gnetlist/tests/common/outputs/vhdl/multiequal-output.net
new file mode 100644
index 0000000..68da18d
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/multiequal-output.net
@@ -0,0 +1,40 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT options
+    END COMPONENT ;
+
+    COMPONENT VOLTAGE_SOURCE
+    END COMPONENT ;
+
+    SIGNAL GND : Std_Logic;
+    SIGNAL unnamed_net1 : Std_Logic;
+BEGIN
+-- Architecture statement part
+    V1 : VOLTAGE_SOURCE
+    PORT MAP (
+        1 => unnamed_net1,
+        2 => GND);
+
+    A1 : options
+;
+
+    R1 : RESISTOR
+    PORT MAP (
+        2 => unnamed_net1,
+        1 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/multiequal.retcode b/gnetlist/tests/common/outputs/vhdl/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/netattrib-output.net b/gnetlist/tests/common/outputs/vhdl/netattrib-output.net
new file mode 100644
index 0000000..a97e18e
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/netattrib-output.net
@@ -0,0 +1,58 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT 7404
+    END COMPONENT ;
+
+    COMPONENT 7400
+    END COMPONENT ;
+
+    COMPONENT FUSE
+    END COMPONENT ;
+
+    SIGNAL unnamed_net1 : Std_Logic;
+    SIGNAL netattrib : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL Vcc : Std_Logic;
+    SIGNAL one : Std_Logic;
+BEGIN
+-- Architecture statement part
+    F1 : FUSE
+    PORT MAP (
+        1 => one,
+        2 => OPEN);
+
+    U100 : 7400
+    PORT MAP (
+        3 => one,
+        2 => OPEN,
+        1 => OPEN,
+        14 => Vcc,
+        7 => GND,
+        5 => netattrib);
+
+    U300 : 7404
+    PORT MAP (
+        1 => one,
+        2 => unnamed_net1,
+        7 => GND,
+        14 => Vcc);
+
+    U200 : 7404
+    PORT MAP (
+        1 => one,
+        2 => netattrib,
+        7 => GND,
+        14 => Vcc);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/netattrib.retcode b/gnetlist/tests/common/outputs/vhdl/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/powersupply-output.net b/gnetlist/tests/common/outputs/vhdl/powersupply-output.net
new file mode 100644
index 0000000..b815feb
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/powersupply-output.net
@@ -0,0 +1,121 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT DIODE-BRIDGE
+    END COMPONENT ;
+
+    COMPONENT LM317
+    END COMPONENT ;
+
+    COMPONENT transformer
+    END COMPONENT ;
+
+    COMPONENT POLARIZED_CAPACITOR
+    END COMPONENT ;
+
+    COMPONENT SPST
+    END COMPONENT ;
+
+    COMPONENT VARIABLE_RESISTOR
+    END COMPONENT ;
+
+    COMPONENT MAINS_CONNECTOR
+    END COMPONENT ;
+
+    COMPONENT RESISTOR
+    END COMPONENT ;
+
+    COMPONENT FUSE
+    END COMPONENT ;
+
+    SIGNAL ten : Std_Logic;
+    SIGNAL eleven : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL one : Std_Logic;
+    SIGNAL five : Std_Logic;
+    SIGNAL three : Std_Logic;
+    SIGNAL two : Std_Logic;
+    SIGNAL six : Std_Logic;
+    SIGNAL seven : Std_Logic;
+    SIGNAL nine : Std_Logic;
+    SIGNAL eight : Std_Logic;
+BEGIN
+-- Architecture statement part
+    F1 : FUSE
+    PORT MAP (
+        1 => two,
+        2 => three);
+
+    R2 : RESISTOR
+    PORT MAP (
+        2 => eleven,
+        1 => ten);
+
+    CONN1 : MAINS_CONNECTOR
+    PORT MAP (
+        1 => one,
+        2 => five,
+        3 => GND);
+
+    C4 : POLARIZED_CAPACITOR
+    PORT MAP (
+        1 => eleven,
+        2 => nine);
+
+    R1 : VARIABLE_RESISTOR
+    PORT MAP (
+        3 => nine,
+        2 => ten,
+        1 => nine);
+
+    C3 : POLARIZED_CAPACITOR
+    PORT MAP (
+        1 => ten,
+        2 => nine);
+
+    C2 : POLARIZED_CAPACITOR
+    PORT MAP (
+        1 => eight,
+        2 => nine);
+
+    S1 : SPST
+    PORT MAP (
+        2 => two,
+        1 => one);
+
+    C1 : POLARIZED_CAPACITOR
+    PORT MAP (
+        1 => eight,
+        2 => nine);
+
+    T1 : transformer
+    PORT MAP (
+        2 => five,
+        1 => three,
+        4 => seven,
+        3 => six);
+
+    U2 : LM317
+    PORT MAP (
+        2 => eleven,
+        3 => eight,
+        1 => ten);
+
+    U1 : DIODE-BRIDGE
+    PORT MAP (
+        1 => eight,
+        2 => nine,
+        3 => seven,
+        4 => six);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/powersupply.retcode b/gnetlist/tests/common/outputs/vhdl/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vhdl/singlenet-output.net b/gnetlist/tests/common/outputs/vhdl/singlenet-output.net
new file mode 100644
index 0000000..9c09d03
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/singlenet-output.net
@@ -0,0 +1,41 @@
+-- Structural VHDL generated by gnetlist
+-- Context clause
+library IEEE;
+use IEEE.Std_Logic_1164.all;
+-- Entity declaration
+
+ENTITY not found IS
+END not found;
+
+
+-- Secondary unit
+ARCHITECTURE netlist OF not found IS
+    COMPONENT 7400
+    END COMPONENT ;
+
+    SIGNAL SING_N_2 : Std_Logic;
+    SIGNAL GND : Std_Logic;
+    SIGNAL Vcc : Std_Logic;
+    SIGNAL SING_N : Std_Logic;
+BEGIN
+-- Architecture statement part
+    U100 : 7400
+    PORT MAP (
+        6 => SING_N,
+        5 => SING_N,
+        4 => SING_N,
+        14 => Vcc,
+        7 => GND,
+        3 => SING_N_2,
+        2 => OPEN,
+        1 => SING_N_2,
+        14 => Vcc,
+        7 => GND,
+        8 => SING_N,
+        10 => SING_N,
+        9 => SING_N,
+        14 => Vcc,
+        7 => GND);
+
+-- Signal assignment part
+END netlist;
diff --git a/gnetlist/tests/common/outputs/vhdl/singlenet.retcode b/gnetlist/tests/common/outputs/vhdl/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vhdl/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/.gitignore b/gnetlist/tests/common/outputs/vipec/.gitignore
new file mode 100644
index 0000000..23c1897
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/.gitignore
@@ -0,0 +1,3 @@
+Makefile
+Makefile.in
+*~
diff --git a/gnetlist/tests/common/outputs/vipec/JD-output.net b/gnetlist/tests/common/outputs/vipec/JD-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/JD.retcode b/gnetlist/tests/common/outputs/vipec/JD.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include-output.net b/gnetlist/tests/common/outputs/vipec/JD_Include-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include.retcode b/gnetlist/tests/common/outputs/vipec/JD_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge.retcode b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Include_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net b/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort.retcode b/gnetlist/tests/common/outputs/vipec/JD_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge.retcode b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_Sort_nomunge.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net b/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
new file mode 100644
index 0000000..c7cd2ab
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/JD_nomunge-output.net
@@ -0,0 +1,18 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 0 	% V1
+	CAP	5 0 C=20p		% Cm
+	error		% A1
+	RES	4 5 R=1k		% Rt
+	error	2 2 1 1 	% M1
+	error	3 0 2 5 4 1 0 	% X1
+	RES	4 1 R=1meg		% Rlp
+	error	1 0 	% Vdd
+	RES	5 0 R=500k		% Rlm
+	CAP	4 0 C=20p		% Cp
+	RES	0 2 R=5.6k		% Rb
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/Makefile.am b/gnetlist/tests/common/outputs/vipec/Makefile.am
new file mode 100644
index 0000000..bf3dd39
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/Makefile.am
@@ -0,0 +1,30 @@
+EXTRA_DIST= \
+	cascade-output.net \
+	cascade.retcode \
+	JD_Include_nomunge-output.net \
+	JD_Include_nomunge.retcode \
+	JD_Include-output.net \
+	JD_Include.retcode \
+	JD_nomunge-output.net \
+	JD-output.net \
+	JD.retcode \
+	JD_Sort_nomunge-output.net \
+	JD_Sort_nomunge.retcode \
+	JD_Sort-output.net \
+	JD_Sort.retcode \
+	multiequal-output.net \
+	multiequal.retcode \
+	netattrib-output.net \
+	netattrib.retcode \
+	powersupply-output.net \
+	powersupply.retcode \
+	singlenet-output.net \
+	singlenet.retcode \
+	SlottedOpamps-output.net \
+	SlottedOpamps.retcode \
+	TwoStageAmp_Include-output.net \
+	TwoStageAmp_Include.retcode \
+	TwoStageAmp-output.net \
+	TwoStageAmp.retcode \
+	TwoStageAmp_Sort-output.net \
+	TwoStageAmp_Sort.retcode
diff --git a/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
new file mode 100644
index 0000000..663c0e3
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/SlottedOpamps-output.net
@@ -0,0 +1,8 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	7 8 9 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U1
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/SlottedOpamps.retcode b/gnetlist/tests/common/outputs/vipec/SlottedOpamps.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/SlottedOpamps.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
new file mode 100644
index 0000000..a5eda3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp-output.net
@@ -0,0 +1,30 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	CAP	5 4 C=2.2uF		% Cout
+	RES	7 8 R=10		% R5
+	RES	0 2 R=2.8K		% R4
+	RES	0 3 R=100		% RE2
+	error	5 2 3 	% Q2
+	error		% A3
+	RES	2 6 R=28K		% R3
+	error		% A2
+	RES	0 10 R=100		% RE1
+	error	11 9 10 	% Q1
+	error		% A1
+	RES	0 9 R=2K		% R2
+	error	7 0 	% Vinput
+	RES	9 6 R=28K		% R1
+	CAP	1 2 C=2.2uF		% C2
+	CAP	0 3 C=1pF		% CE2
+	CAP	8 9 C=2.2uF		% C1
+	CAP	0 10 C=1pF		% CE1
+	RES	11 1 R=1		% R8
+	error	6 0 	% VCC
+	RES	5 6 R=1K		% RC2
+	RES	11 6 R=3.3K		% RC1
+	RES	0 4 R=100K		% RL
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp.retcode b/gnetlist/tests/common/outputs/vipec/TwoStageAmp.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
new file mode 100644
index 0000000..a5eda3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include-output.net
@@ -0,0 +1,30 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	CAP	5 4 C=2.2uF		% Cout
+	RES	7 8 R=10		% R5
+	RES	0 2 R=2.8K		% R4
+	RES	0 3 R=100		% RE2
+	error	5 2 3 	% Q2
+	error		% A3
+	RES	2 6 R=28K		% R3
+	error		% A2
+	RES	0 10 R=100		% RE1
+	error	11 9 10 	% Q1
+	error		% A1
+	RES	0 9 R=2K		% R2
+	error	7 0 	% Vinput
+	RES	9 6 R=28K		% R1
+	CAP	1 2 C=2.2uF		% C2
+	CAP	0 3 C=1pF		% CE2
+	CAP	8 9 C=2.2uF		% C1
+	CAP	0 10 C=1pF		% CE1
+	RES	11 1 R=1		% R8
+	error	6 0 	% VCC
+	RES	5 6 R=1K		% RC2
+	RES	11 6 R=3.3K		% RC1
+	RES	0 4 R=100K		% RL
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include.retcode b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Include.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
new file mode 100644
index 0000000..a5eda3f
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort-output.net
@@ -0,0 +1,30 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	CAP	5 4 C=2.2uF		% Cout
+	RES	7 8 R=10		% R5
+	RES	0 2 R=2.8K		% R4
+	RES	0 3 R=100		% RE2
+	error	5 2 3 	% Q2
+	error		% A3
+	RES	2 6 R=28K		% R3
+	error		% A2
+	RES	0 10 R=100		% RE1
+	error	11 9 10 	% Q1
+	error		% A1
+	RES	0 9 R=2K		% R2
+	error	7 0 	% Vinput
+	RES	9 6 R=28K		% R1
+	CAP	1 2 C=2.2uF		% C2
+	CAP	0 3 C=1pF		% CE2
+	CAP	8 9 C=2.2uF		% C1
+	CAP	0 10 C=1pF		% CE1
+	RES	11 1 R=1		% R8
+	error	6 0 	% VCC
+	RES	5 6 R=1K		% RC2
+	RES	11 6 R=3.3K		% RC1
+	RES	0 4 R=100K		% RL
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort.retcode b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/TwoStageAmp_Sort.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/cascade-output.net b/gnetlist/tests/common/outputs/vipec/cascade-output.net
new file mode 100644
index 0000000..75b0b79
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/cascade-output.net
@@ -0,0 +1,15 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	1 #<unspecified> 	% AMP2
+	error	6 5 	% AMP1
+	error	6 	% SOURCE
+	error	#<unspecified> 	% DEFAULTS
+	error	3 2 	% MX1
+	error	5 4 	% DEF1
+	error	2 1 	% T1
+	error	4 3 	% FL1
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/cascade.retcode b/gnetlist/tests/common/outputs/vipec/cascade.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/cascade.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/multiequal-output.net b/gnetlist/tests/common/outputs/vipec/multiequal-output.net
new file mode 100644
index 0000000..a800cc8
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/multiequal-output.net
@@ -0,0 +1,10 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	1 0 	% V1
+	error		% A1
+	RES	0 1 R=20		% R1
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/multiequal.retcode b/gnetlist/tests/common/outputs/vipec/multiequal.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/multiequal.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/netattrib-output.net b/gnetlist/tests/common/outputs/vipec/netattrib-output.net
new file mode 100644
index 0000000..9685438
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/netattrib-output.net
@@ -0,0 +1,11 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	4 #<unspecified> 	% F1
+	error	#<unspecified> #<unspecified> 4 #<unspecified> #<unspecified> #<unspecified> 	% U100
+	error	4 1 #<unspecified> #<unspecified> 	% U300
+	error	4 2 #<unspecified> #<unspecified> 	% U200
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/netattrib.retcode b/gnetlist/tests/common/outputs/vipec/netattrib.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/netattrib.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/powersupply-output.net b/gnetlist/tests/common/outputs/vipec/powersupply-output.net
new file mode 100644
index 0000000..6e9bd91
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/powersupply-output.net
@@ -0,0 +1,19 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	6 5 	% F1
+	RES	1 2 R=220		% R2
+	error	3 4 0 	% CONN1
+	error	2 9 	% C4
+	error	9 1 9 	% R1
+	error	1 9 	% C3
+	error	10 9 	% C2
+	error	3 6 	% S1
+	error	10 9 	% C1
+	error	5 4 7 8 	% T1
+	error	1 2 10 	% U2
+	error	10 9 8 7 	% U1
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/powersupply.retcode b/gnetlist/tests/common/outputs/vipec/powersupply.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/powersupply.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/outputs/vipec/singlenet-output.net b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
new file mode 100644
index 0000000..53b7251
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/singlenet-output.net
@@ -0,0 +1,8 @@
+% ViPEC RF Netlister
+% Written by Matthew Ettus
+% Based on code by Bas Gieltjes
+CKT
+	error	3 3 3 #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> #<unspecified> 	% U100
+	DEF2P	#<unspecified>  #<unspecified>
+	TERM	50 50
+
diff --git a/gnetlist/tests/common/outputs/vipec/singlenet.retcode b/gnetlist/tests/common/outputs/vipec/singlenet.retcode
new file mode 100644
index 0000000..573541a
--- /dev/null
+++ b/gnetlist/tests/common/outputs/vipec/singlenet.retcode
@@ -0,0 +1 @@
+0
diff --git a/gnetlist/tests/common/run_backend_tests.sh b/gnetlist/tests/common/run_backend_tests.sh
new file mode 100755
index 0000000..933ce50
--- /dev/null
+++ b/gnetlist/tests/common/run_backend_tests.sh
@@ -0,0 +1,273 @@
+#!/bin/sh
+#
+# This script runs the tests called out for in test.list
+#
+
+regen=no
+
+usage() {
+cat << EOF
+
+$0 -- Testsuite program for various backends
+
+Usage
+
+  $0 [-h | --help]
+  $0 [-r | --regen] <backend> [test1 [test2 [....]]]
+
+Options
+
+  -h | --help     Prints this help message and exits.
+
+  -r | --regen    Regenerates the reference files.  If you use
+                  this option, YOU MUST HAND VERIFY THE RESULTS
+                  BEFORE COMMITTING to the repository.
+
+Description
+
+$0 reads a file, tests.list,  describing tests to run on <backend>.
+If no specific test is specified on the $0 command line, then all 
+tests are run.
+
+Examples
+
+$0 spice-sdb
+$0 --regen new_test spice-sdb
+
+EOF
+}
+while test -n "$1"
+do
+    case "$1"
+    in
+
+    -h|--help)
+	usage
+	exit 0
+	;;
+
+    -r|--regen)
+	# regenerate the 'golden' output files.  Use this with caution.
+	# In particular, all differences should be noted and understood.
+	regen=yes
+	shift
+	;;
+
+    -*)
+	echo "unknown option: $1"
+	usage
+	exit 1
+	;;
+
+    *)
+	break
+	;;
+
+    esac
+done
+
+if [ -f $1 ]; then
+  usage
+  exit 1
+fi
+
+backend=$1
+shift
+
+echo "********USING BACKEND ${backend}*********"
+
+# make sure we have the right paths when running this from inside the
+# source tree and also from outside the source tree.
+here=`pwd`
+srcdir=${srcdir:-$here}
+srcdir=`cd $srcdir && pwd`
+
+GNETLIST=../../../src/gnetlist
+
+rundir=${here}/run
+
+GOLDEN_DIR=${srcdir}/outputs/${backend}
+INPUT_DIR=${srcdir}/inputs
+
+TESTLIST=${srcdir}/tests.list
+ALWAYSCOPYLIST=${srcdir}/always-copy.list
+
+if test ! -f $TESTLIST ; then
+    echo "ERROR: ($0)  Test list $TESTLIST does not exist"
+    exit 1
+fi
+
+# fail/pass/total counts
+fail=0
+pass=0
+skip=0
+tot=0
+
+# here's where we look at the test.list file and extract the names of all
+# the tests we want to run.
+if test -z "$1" ; then
+    all_tests=`awk 'BEGIN{FS="|"} /^#/{next} /^[ \t]*$/{next} {print $1}' $TESTLIST | sed 's; ;;g'`
+else
+    all_tests=$*
+fi
+echo All tests = $all_tests
+
+# here's where we look at always-copy.list file and extract the names of all
+# the extra files we want to copy for every test
+always_copy=`cat $ALWAYSCOPYLIST | sed '/^#/d'`
+
+cat << EOF
+
+Starting tests in $here
+srcdir:     $srcdir
+INPUT_DIR:  ${INPUT_DIR}
+GOLDEN_DIR: ${GOLDEN_DIR}
+GNETLIST:   ${GNETLIST}
+all_tests:
+
+${all_tests}
+
+EOF
+
+# Now run through all tests in test.list, prepare the $rundir,
+# then run the tests. 
+for t in $all_tests ; do
+
+    # strip any leading garbage 
+    t=`echo $t | sed 's;^\*;;g'`
+
+    # figure out what files we need to copy for this test and what
+    # arguments to feed gnetlist 
+    schematics=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $2}'`
+    auxfiles=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $3}'`
+    args=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $4}'`
+    condition=`grep "^[ \t]*${t}[ \t]*|" $TESTLIST | awk 'BEGIN{FS="|"} {print $5}' | sed 's; ;;g'`
+
+    refcode=${GOLDEN_DIR}/${t}.retcode
+    if test -f $refcode; then
+        code=`grep -v "^#" $refcode | sed 's; ;;g;'`
+    else
+        code=0
+    fi
+    if test "X$code" = "X" ; then
+	code=0
+    fi
+
+    echo "Schematics to copy   = $schematics"
+    echo "Args to copy         = $args"
+    echo "Always copying       = $always_copy"
+    echo "Expected return code = \"$code\""
+    if test "X$condition" != "X" ; then
+        eval "ctest=\`echo \$$condition\`"
+        if test X$ctest = "Xyes" ; then
+            echo "Running test because $condition = yes"
+        else
+            echo "Skipping test because $condition = $ctest"
+	    continue
+        fi
+    fi
+
+    tot=`expr $tot + 1`
+
+    # create temporary run directory and required subdirs
+    if test ! -d $rundir ; then
+	mkdir -p $rundir
+	mkdir -p $rundir/sym
+	mkdir -p $rundir/models
+    fi
+
+    # Create the files needed
+    # Note that we need to include not only the .sch files,
+    # but also the contents of the sym and model directories.
+    if test ! -z "$schematics" ; then
+	echo "Copying over schematics to run dir"
+	for f in $schematics ; do
+	    echo "cp ${INPUT_DIR}/${f} ${rundir}/${f}"
+	    cp ${INPUT_DIR}/${f} ${rundir}/${f}
+	    chmod 644 ${rundir}/${f}
+	done
+    fi
+    if test ! -z "$auxfiles" ; then
+	echo "Copying over aux files to run dir"
+	for f in $auxfiles ; do
+	    echo "cp ${INPUT_DIR}/${f} ${rundir}/${f}"
+	    cp ${INPUT_DIR}/${f} ${rundir}/${f}
+	    chmod 644 ${rundir}/${f}
+	done
+    fi
+    if test ! -z "$always_copy" ; then
+	echo "Copying over always copied files to run dir"
+	for f in $always_copy ; do
+	    echo "cp ${INPUT_DIR}/${f} ${rundir}/${f}"
+	    cp ${INPUT_DIR}/${f} ${rundir}/${f}
+	    chmod 644 ${rundir}/${f}
+	done
+    fi
+
+    # run gnetlist -g $backend
+    echo "${GNETLIST} -g $backend $args $schematics"
+    cd ${rundir} && ${GNETLIST} -g $backend $args $schematics 
+    rc=$?
+
+    # OK, now check results of run.
+    good=0
+    bad=0
+    soso=0
+
+    ref=${GOLDEN_DIR}/${t}-output.net
+    out=${rundir}/output.net
+
+    # Hack to help with vams backend
+    if [ -f ${rundir}/default_entity_arc.net ]; then
+      mv ${rundir}/default_entity_arc.net $out
+    fi
+    
+    if test "X$regen" = "Xyes" ; then
+	cp ${out} ${ref}
+	echo "$rc" > $refcode
+	echo "Regenerated ${ref}"
+        good=1
+    elif test $rc -ne $code ; then
+	echo "FAILED:  gnetlist -g $backend returned $rc which did not match the expected $code"
+	bad=1
+    elif test -f ${ref} ; then
+
+	sed '/gnetlist -g/d' ${ref} > ${out}.tmp1
+	sed '/gnetlist -g/d' ${out} > ${out}.tmp2
+
+	if diff -w ${out}.tmp1 ${out}.tmp2 >/dev/null ; then
+	    echo "PASS"
+            good=1
+	else
+	    echo "FAILED:  See diff -w ${ref} ${out}"
+	    bad=1
+	fi
+    elif test ! -f $out ; then
+	# No output file, but this is expected since there was no reference file
+	good=1
+    else
+	echo "No reference file.  Skipping"
+	soso=1
+    fi
+
+    pass=`expr $pass + $good`
+    fail=`expr $fail + $bad`
+    skip=`expr $skip + $soso`
+
+    cd $here
+    
+    # Delete the run directory in prep for the next test
+    rm -fr ${rundir}
+
+done
+
+echo "Passed $pass, failed $fail, skipped $skip out of $tot tests."
+
+rc=0
+if test $pass -ne $tot ; then
+    rc=`expr $tot - $pass`
+
+fi
+
+exit $rc
+
diff --git a/gnetlist/tests/common/run_tests.sh b/gnetlist/tests/common/run_tests.sh
new file mode 100755
index 0000000..495868b
--- /dev/null
+++ b/gnetlist/tests/common/run_tests.sh
@@ -0,0 +1,119 @@
+#!/bin/sh
+#
+# This script runs run_backend_tests.sh on each backend listed in backends.list
+#
+
+regen=no
+
+usage() {
+cat << EOF
+
+$0 -- Testsuite program for various backends
+
+Usage
+
+  $0 [-h | --help]
+
+Options
+
+  -h | --help     Prints this help message and exits.
+  -r | --regen    Regenerates the reference files.  If you use
+                  this option, YOU MUST HAND VERIFY THE RESULTS
+                  BEFORE COMMITTING to the repository.
+
+Description
+
+$0 reads a file, backends.list,  describing backends to run tests on.
+For each backend, run_backend_test.sh is run with that backend name
+as a parameter.
+
+Examples
+
+$0
+$0 --regen
+
+EOF
+}
+while test -n "$1"
+do
+    case "$1"
+    in
+
+    -h|--help)
+	usage
+	exit 0
+	;;
+
+    -r|--regen)
+	# regenerate the 'golden' output files.  Use this with caution.
+	# In particular, all differences should be noted and understood.
+	regen=yes
+	shift
+	;;
+
+    -*)
+	echo "unknown option: $1"
+	usage
+	exit 1
+	;;
+
+    *)
+	break
+	;;
+
+    esac
+done
+
+# make sure we have the right paths when running this from inside the
+# source tree and also from outside the source tree.
+here=`pwd`
+srcdir=${srcdir:-$here}
+srcdir=`cd $srcdir && pwd`
+
+BACKENDSLIST=${srcdir}/backends.list
+
+if test ! -f $BACKENDSLIST ; then
+    echo "ERROR: ($0)  Test list $BACKENDSLIST does not exist"
+    exit 1
+fi
+
+# fail/pass/total counts
+fail=0
+pass=0
+tot=0
+all_tests=`cat $BACKENDSLIST | sed /^#/d`
+echo All backends = $all_tests
+
+# Now run through all backends in backends.list, calling run_backend_tests.sh
+for backend in $all_tests ; do
+
+    tot=`expr $tot + 1`
+
+    if test "X$regen" = "Xyes" ; then
+      echo "Regenerating test results on backend \"$backend\""
+      $srcdir/run_backend_tests.sh --regen $backend 2> $backend.stderr.log > $backend.stdout.log
+      rc=$?
+    else
+      echo "Running tests on backend \"$backend\""
+      $srcdir/run_backend_tests.sh $backend 2> $backend.stderr.log > $backend.stdout.log
+      rc=$?
+    fi
+
+    if test $rc -ne 0 ; then
+        echo "FAILED:  run_backend_test.sh returned $rc failures"
+        fail=`expr $fail + 1`
+        continue
+    fi
+
+    pass=`expr $pass + 1`
+done
+
+echo "Passed $pass, failed $fail, out of $tot tests."
+
+rc=0
+if test $pass -ne $tot ; then
+    rc=`expr $tot - $pass`
+fi
+
+exit $rc
+
diff --git a/gnetlist/tests/common/tests.list b/gnetlist/tests/common/tests.list
new file mode 100644
index 0000000..8607735
--- /dev/null
+++ b/gnetlist/tests/common/tests.list
@@ -0,0 +1,36 @@
+# Format:
+#
+# test_name | input schematics | aux files (gafrc, symbols, etc) | \ 
+# extra flags to pass to gnetlist -g spice-sdb | \
+# variable which must be set for the test to run
+#
+
+
+# -----------------------------------------
+# Simple netlisting tests
+# -----------------------------------------
+
+# Some test schematics copied from the toplevel tests dir
+cascade | cascade.sch | | |
+multiequal | multiequal.sch | | |
+netattrib | netattrib.sch | | |
+powersupply | powersupply.sch | | |
+singlenet | singlenet.sch | | |
+
+# The two stage amp
+TwoStageAmp | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | |
+TwoStageAmp_Include | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | -I
+TwoStageAmp_Sort | TwoStageAmp.sch | Simulation.cmd gafrc models/2N3904.mod sym/transistor.sym | -s
+
+# John Doty's test circuit
+# First test mangling
+JD | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | |
+JD_Include | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -I
+JD_Sort | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -s
+# Now test non-munged version.
+JD_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | | -n
+JD_Include_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -I -n
+JD_Sort_nomunge | LVDfoo.sch | gafrc models/openIP_5.cir sym/LVD.sym | -s -n
+
+# Tests for slotted parts
+SlottedOpamps | SlottedOpamps.sch | gafrc sym/LM324_slotted-1.sym | |




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