gEDA-cvs: pcb.git: branch: master updated (faae5572e9742bd0a8a846a9c94963f486c37b5e)

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       via  faae5572e9742bd0a8a846a9c94963f486c37b5e (commit)
      from  086aa491fae18f1ec72da047b772fa3510f72d0b (commit)

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=========
 Summary
=========

 src/draw.c    |    3 +++
 src/find.c    |   18 ++++++++----------
 src/polygon.c |    4 ++++
 3 files changed, 15 insertions(+), 10 deletions(-)


=================
 Commit Messages
=================

commit faae5572e9742bd0a8a846a9c94963f486c37b5e
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Commit: Peter Clifton <pcjc2@xxxxxxxxx>

    Correct rendering and connectivity checks for zero clearance pads and pins
    
    NB: These areren't technically allowed by PCB, but it is nice that when a
    user hacks zero clearance in their PCB file, that we:
    
    a) Draw polygons without any cleared gaps in the output
    b) Correctly determine that these objects will be connected to the polygon

:100644 100644 3756955... f3bb2cb... M	src/draw.c
:100644 100644 e22d5cc... b24512a... M	src/find.c
:100644 100644 e9fc3df... 71cfd60... M	src/polygon.c

=========
 Changes
=========

commit faae5572e9742bd0a8a846a9c94963f486c37b5e
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Commit: Peter Clifton <pcjc2@xxxxxxxxx>

    Correct rendering and connectivity checks for zero clearance pads and pins
    
    NB: These areren't technically allowed by PCB, but it is nice that when a
    user hacks zero clearance in their PCB file, that we:
    
    a) Draw polygons without any cleared gaps in the output
    b) Correctly determine that these objects will be connected to the polygon

diff --git a/src/draw.c b/src/draw.c
index 3756955..f3bb2cb 100644
--- a/src/draw.c
+++ b/src/draw.c
@@ -1349,6 +1349,9 @@ DrawPadLowLevel (hidGC gc, PadTypePtr Pad, Boolean clear, Boolean mask)
       return;
     }
 
+  if (clear && !mask && Pad->Clearance <= 0)
+    return;
+
   if (TEST_FLAG (THINDRAWFLAG, PCB) ||
       (clear && TEST_FLAG (THINDRAWPOLYFLAG, PCB)))
     {
diff --git a/src/find.c b/src/find.c
index e22d5cc..b24512a 100644
--- a/src/find.c
+++ b/src/find.c
@@ -2287,7 +2287,8 @@ LOCtoPadPoly_callback (const BoxType * b, void *cl)
   struct lo_info *i = (struct lo_info *) cl;
 
 
-  if (!TEST_FLAG (TheFlag, polygon) && !TEST_FLAG (CLEARPOLYFLAG, polygon))
+  if (!TEST_FLAG (TheFlag, polygon) &&
+      (!TEST_FLAG (CLEARPOLYFLAG, polygon) || !i->pad.Clearance))
     {
       if (IsPadInPolygon (&i->pad, polygon) &&
           ADD_POLYGON_TO_LIST (i->layer, polygon))
@@ -2532,15 +2533,12 @@ LookupLOConnectionsToPolygon (PolygonTypePtr Polygon, Cardinal LayerGroup)
         }
       else
         {
-          if (!TEST_FLAG (CLEARPOLYFLAG, Polygon))
-            {
-              info.layer = layer - max_layer;
-              if (setjmp (info.env) == 0)
-                r_search (PCB->Data->pad_tree, (BoxType *) & info.polygon,
-                          NULL, LOCtoPolyPad_callback, &info);
-              else
-                return True;
-            }
+          info.layer = layer - max_layer;
+          if (setjmp (info.env) == 0)
+            r_search (PCB->Data->pad_tree, (BoxType *) & info.polygon,
+                      NULL, LOCtoPolyPad_callback, &info);
+          else
+            return True;
         }
     }
   return (False);
diff --git a/src/polygon.c b/src/polygon.c
index e9fc3df..71cfd60 100644
--- a/src/polygon.c
+++ b/src/polygon.c
@@ -743,6 +743,8 @@ SubtractPad (PadType * pad, PolygonType * p)
 {
   POLYAREA *np = NULL;
 
+  if (pad->Clearance == 0)
+    return 0;
   if (TEST_FLAG (SQUAREFLAG, pad))
     {
       if (!
@@ -812,6 +814,8 @@ pad_sub_callback (const BoxType * b, void *cl)
   /* don't subtract the object that was put back! */
   if (b == info->other)
     return 0;
+  if (pad->Clearance == 0)
+    return 0;
   polygon = info->polygon;
   if (XOR (TEST_FLAG (ONSOLDERFLAG, pad), !info->solder))
     {




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