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gEDA-cvs: branch: master updated (rel_0.1.1-2-g90d72dc)



The branch, master has been updated
       via  90d72dc57a8817d86409473dc2b3db6bc3704c85 (commit)
      from  109620962168516475f49626dc34ad4f5c282bda (commit)

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=========
 Summary
=========

 lib/xgsch2pcb/pcbmanager.py |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


=================
 Commit Messages
=================

commit 90d72dc57a8817d86409473dc2b3db6bc3704c85
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sun Oct 7 20:41:28 2007 +0100

    Pass PCB an absolute path to PCB when editing the layout.
    
    Depending on the lrealpath implementation found at compile time in PCB,
    the path returned by PCB may not be an absolute path (as we require)
    if the file does not yet exist on disk. (e.g. a new project).
    
    Passing a full path on PCB's command line ensures it will return an
    absolute path when queried via D-Bus.

:100644 100644 b7c7ef2... 1314659... M	lib/xgsch2pcb/pcbmanager.py

=========
 Changes
=========

commit 90d72dc57a8817d86409473dc2b3db6bc3704c85
Author: Peter Clifton <pcjc2@xxxxxxxxx>
Date:   Sun Oct 7 20:41:28 2007 +0100

    Pass PCB an absolute path to PCB when editing the layout.
    
    Depending on the lrealpath implementation found at compile time in PCB,
    the path returned by PCB may not be an absolute path (as we require)
    if the file does not yet exist on disk. (e.g. a new project).
    
    Passing a full path on PCB's command line ensures it will return an
    absolute path when queried via D-Bus.

diff --git a/lib/xgsch2pcb/pcbmanager.py b/lib/xgsch2pcb/pcbmanager.py
index b7c7ef2..1314659 100644
--- a/lib/xgsch2pcb/pcbmanager.py
+++ b/lib/xgsch2pcb/pcbmanager.py
@@ -90,7 +90,7 @@ class PCBManager( gobject.GObject ):
             # TODO: Is there some clever way to bring PCB to front?
             # Possibly send it an action which does a window-manager request?
             return
-        Popen([self.toolpath, self.output_name + ".pcb"])
+        Popen([self.toolpath, os.path.abspath( self.output_name + ".pcb" )])
         while not self.is_layout_open():
             time.sleep( 0.1 )
         assert self.is_layout_open()




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