Re: gEDA-user: Keep Out Layer/Line

["Phil Taylor" <phil@xxxxxxxxxxxxxxxxxxxxxxxx>]

Simon,

PCB at present doesn't do this.

In PCB, it's customary to use the silk layer to make mechanical and
geometrical 'keepouts' ... of course though these are not automated for a
keepout function and must be edited manually.

Phil

ST de Feber <stdf23173@xxxxxxxxxxx> wrote:

> Hello,
> 
> I am used, Protel/Eagle, to work with "keep out-line/layers".
> Is it possible to have a similar thing in PCB ?
> 
> grtz
> 
> Simon
> 
> 
>