Re: gEDA-user: A couple o' questions

[Carlos Nieves Ónega <cnieves.mail@xxxxxxxxx>]

El miÃ, 05-04-2006 a las 16:16 -0600, John Doty escribiÃ:
> On Apr 5, 2006, at 3:03 PM, Carlos Nieves Ãnega wrote:
[snip]
> The problem isn't *me*, it's newbies who wander into a hall of  
> mirrors because they are exhorted to use DRC. Telling them they can  
> configure it is just one more burden.

My opinion is like David Logan's: the DRC should report everything by
default. Newbies are expected to learn how to use the tools, and more
advanced users can disable what they want.
If you learn a quick and easy way the first time, you never will do it
right. Design speed is important, but design quality is more important.

Nevertheless, I'm trying to understand your problems and your workflow
to see if there is some way to improve the DRC.

[snip]
> But you've got pwr_in connected to passives only. Should that be OK,  
> or should you insist on one pwr_out per power net?

It is ok right now. A passive pin can be a power source (through a
diode, resistor, or whatever), so DRC won't complain about it.

> >
> >> Then there's GND, what pintype is that? Remember that it's perfectly
> >> sensible to connect this to something other than ground, to get 5V
> >> *relative* to some other potential.
> >
> > GND is pwr. If you are defining an IC which needs to be powered,  
> > and VCC
> > is pwr_in, let me assume for a moment that GND is pwr_in.
> 
> But is it pwr_in for a 7805? Might come from a signal of some sort.  
> It's a low current voltage input.

I don't understand. Do you mean GND is an input??

[snip]
> For boards, the slot checks are potentially useful, but I'm in the  
> habit of reviewing the slotting by eye anyway to avoid unfriendly  
> feedback from the board designer ;-). DRC doesn't complain about  
> logically correct but geometrically insane slotting, does it?

Do you want a program doing all your job? ;-)
It would be easier to do and nice to haver it in the PCB side (slot
changing and backannotation). A schematic know nothing about geometry.

[snip]
> Would be handy to check for value= on components that need it.

Do you mean passives?

> Floating pins are bad, but unconnected pins are normal.

There is no program to substitute the designer's brain.

> In general, there's no substitute for careful checking by eye.

Agree. I don't even trust myself. That's why I want a program doing the
tedious thing, while I am focused on the hard side.

El miÃ, 05-04-2006 a las 17:33 -0600, John Doty escribiÃ: 
> Many components in the libraries don't have pintype attributes, and  
> it isn't even obvious how to fix them.

What components? I worked on this some time ago, and I think that only 
ICs were still without the pintype attribute.

[snip]
>DRC screams about too many non problems. It doesn't understand  
> hierarchy, at least the way spice-sdb does. It thinks unconnected  
> pins and single pin nets are errors. A simple error-free CMOS  
> inverter SPICE subcircuit made with library MOSFET symbols gives 8  
> DRC errors for only two components, correctly connected. 
[snip]

I have to review the hierarchy support. 
I would like to see if there is any solution. 
Can you post this little example as you usually draw your schematics?

Thanks,

Carlos