Re: gEDA-user: Design Flow Roadmap starting point

[al davis <ad136@xxxxxxxxxxxxxxxx>]

On Tuesday 03 April 2007 19:38, Magnus Danielson wrote:
> From: al davis <ad136@xxxxxxxxxxxxxxxx>
> > I was thinking of using the gnucap "CS" parser class, and
> > doing it like everything else in gnucap, as a language
> > plugin.  I am guessing that VHDL will be about 50 lines of
> > code, Verilog will be about 50 lines of code, Spice will be
> > about 2000 lines of code, pcb about 100 lines, not sure
> > about gschem.
>
> Need to look at the gnucap parser class stuff. Otherwise I
> agree.

The line count is a guess.  My point is that VHDL and Verilog 
are about the same.  Spice is the worst one of all.  Others are 
between.  The fact that VHDL and Verilog are so regular makes 
the parsers and generators small.  The Spice parser and 
generator is huge because the language is so irregular.  It 
seems every component is different.

> Certainly, but for a sufficiently complex thing, type
> filtering isn't helping unless you can construct new types
> out of the old and name them as you like. Compound types of
> various sort comes to mind after some time and ka-bang things
> got a bit complex again. Filtering on attribute names is
> probably a better appoach most of the times.

That is way too complicated.  The type is just a name, used to 
group things, so they can be filtered as groups.  Without 
changing anything, it is possible to just use a naming 
convention and partial matching to select.  I am thinking of 
groups like simulation parameters, the hidden attributes that 
make gschem work, layout stuff, data coming back from a 
simulator.  The names cannot be determined in advance.  Strings 
like what we do now for things like spice sources is not the 
way to go long term.  To store it, it would need to be able to 
be encoded as a single string anyway, so it might make sense to 
just do that and forget doing anything special.


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