gEDA-user: Re: BUGS: iverilog reals

[Stephen Williams <steve@xxxxxxxxxx>]

Looks like there are some bug reports in here. I'm pretty busy with
a big task at the moment so I may not get to these right away, so
that makes filing bug reports even more important.

lingwitt@xxxxxxxxxxxxx wrote:

> The following compiles
> (and probably shouldn't, unfortunately):
> 
>     module reals;
>         wire [63:0] blah = $realtobits(6.35e25);
>     endmodule

Why shouldn't it compile?

> but when run produces:
> 
>     ./a.out:7: syntax error

Obviously a bug.

> ///////////// [ 2 ] /////////////
> 
> The following compiles:
> 
>     module reals;
> 
>         SomeModule someModule
>         (
>             $realtobits(3.14+3.15)
>         );
> 
>     endmodule
> 
>     module SomeModule
>     (
>         input  [63:0] in
>     );
> 
>     endmodule
> 
> but when run produces:
> 
>     internal error: 13vvp_arith_sum: recv_real(3.140000) not implemented
>     ../../src/vvp/vvp_net.cc:1386: failed assertion `0'
>     Abort trap

Bug to be reported. Different from above, so make it a different
bug report.

> ///////////// [ 3 ] /////////////
> 
> There was some problem with realtobits/bitstoreal that
> was fixed with the following change:
> 
> Index: vvp/vpi_tasks.cc
> ===================================================================
> RCS file: /home/demon/anoncvs/verilog/vvp/vpi_tasks.cc,v
> retrieving revision 1.35
> diff -u -r1.35 vpi_tasks.cc
> --- vvp/vpi_tasks.cc    12 Apr 2007 04:45:53 -0000      1.35
> +++ vvp/vpi_tasks.cc    28 Apr 2007 03:25:34 -0000
> @@ -577,7 +577,7 @@
>        vpip_cur_task = (struct __vpiSysTaskCall*)ref;
>        if (vpip_cur_task->defn->info.calltf) {
> -           assert(vpi_mode_flag == VPI_MODE_NONE);
> +           /*assert(vpi_mode_flag == VPI_MODE_NONE);*/
>             vpi_mode_flag = VPI_MODE_CALLTF;
>            
> vpip_cur_task->defn->info.calltf(vpip_cur_task->defn->info.user_data);
>             vpi_mode_flag = VPI_MODE_NONE;
>

This "fix" doesn't address the question whether that assertion
is correct and something else bad might be happening. I don't want
to just remove the assert (which is there for a reason) without
addressing the cause.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."



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