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Re: gEDA-user: gattrib
John,
Are you even reading my posts? You comments, even when directly
connected to quotes of my own text seem completely unrelated and non
sequiturs, and often self contradictory.
On Apr 27, 2010, at 5:43 PM, Mike Bushroe wrote:
> John Doty: These refer to the device, not the pattern of
copper on
> the board. The pattern of copper corresponding to a given
device
> footprint should be chosen in the layout process, because it
depends
> (like other layout parameters) on the manufacturing processes.
>
> I am still confused by your continual assertion that the copper
pattern
> should be completely separate from the physical part. As pointed
out
> above, a DIP-16 is a through-hole device in any process, the
pins are
> always 0.100 inches apart, the part number defines if it is a
typical
> 300 mill spacing, or a wide 600 mill. What ever process you use
to
> attach the chip to a circuit board, those things never change
for that
> physical part number.
> The closest I can guess to something that would be 'process
> dependent' would be the size of the copper pads, and possibly
the
> exclusion zone around them. I could see having one version for
hand
> soldered work, with 40 mill pads and only enough room to run one
signal
> line between them; and a professional fab shop version with 15
mill
> pads, 10 mill or smaller traces and and spaces and room for 4 or
more
> signals between pins.
These properties are critical, not trivial at all.
Which properties? What makes them critical? How does these two
sentences relate to to the two paragraphs above? I am more confused
about what you mean after reading this, not less.
> If there was a parameter that could be set by
> gattrib for each part,
Each part? Ugh! Specify the parameters of the *process*, leave the
schematics alone. Aside from the fact that a part by part process is
miserably low productivity, there's no reason to restrict a
schematic to a particular process downstream.
What "process" ? You have used that term many times without giving any
examples. I gave two that proved the point in the opposite direction,
that process has little or no affect on PCB copper patterns (commonly
called footprints). If you can not offer an example of a process that
PCB is used to design for but requires radically different copper
patterns for the same physical part, I might be able to begin to
understand what you point is. I know that PCB footprints are useless
for designing a VLSI part, or and FPGA, or CPLD. But I also doubt very
much that PCB can be used in anyway to design VLSI parts, pr FPGA
arrays, or CPLD devices, so claiming that the *process* selects whether
you use PCB footprints or FPGA blocks is meaningless. If you were using
gschem to design an FPGA, you would not use gsch2pcb, and therefor even
if you ran gattrib to fatten out your schematic symbols, you would not
bother to do anything with PCB footprints. I agree that the *process*
defines the tool chain. But once you have decided on the gschem to PCB
tool chain as being best for your process, PCB footprints, as in copper
traces, pins, pads, holes, silk screen, and solder mask pattern
attached to a specific physical part, is not only needed but required,
and should be as easy to reliably edit to make a good conversion to PCB
as the original schematic designing was in gschem.
"Each part? Ugh!" Emotional baggage rather then stating facts,
observations, or offering arguments tend to convince me that you have
no facts, observations, or arguments to back up your opinions. It is
difficult to carry on a meaningful, informative, instructive discussion
when your chief reply is "Ugh!"
This response of yours also seems to contradict your self again.
You keep calling for flexibility, yet when I mention something that
increases flexibility, you suddenly throw up your arms and cry loose of
flexibility. I have not yet used gattrib, but from what I have read
here and elsewhere, its very purpose is to provide the designer with a
text based interface to change attributes of symbols one at a time, or
possibly in blocks. How can editing a parameter for each symbol to
suggest to gsch2pcb that it use a fat pad and trace based footprint of
a skinning based pad and trace pattern be anything other using exactly
for what it was designed for? And if you do not intend to run PCB, you
can run you own special wizard level too chain and never have to worry
about any additions to gsch2pcb, and even if you use gatrib, you can
easily ignore the portions that relate to PCBs.
> or gsch2pcb for all to pick from fat or skinny
> pads, I could see some use in that. But as far as I know, you
can also
> do all of that in pcb, so there is no range of process variation
that
> still uses a 16 pin dip that could not be edited in pcb. So why
must we
> divorce the copper pattern from the component? How divergent a
process
> are you holding out for that would still be laid out in pcb?
This is exactly the kind of tunnel vision that scares me. I have
never used pcb, but I've designed quite a few printed circuit boards
with gEDA (along with several VLSI chips, where footprint is
irrelevant). This works because gschem is agnostic about what's
downstream. It should stay that way.
John Doty Noqsi Aerospace, Ltd.
[1]http://www.noqsi.com/
[2]jpd@xxxxxxxxx
Please explain how designing a VLSI chip is relevant to using PCB. I
thought that it was not possible to design a VLSI chip using PCB. If
your *process* is designing for a VLSI chip, wouldn't you be using a
tool chain without PCB? And therefor without gsch2pcb? And therefor not
needing to add PCB footprints to the symbols with gattrib, but rather
entering Verilog patterns?
Please explain what constitutes tunnel vision in the above paragraph. I
thought I was making it quite clear that I was not only referring to
one specific tool chain, gschem to PCB, where good engineering is
called staying focused not tunnel vision. And recommending clean,
separate interfaces specific to the task chosen is normally hailed as
good design practice, not called scary. I still fail to understand what
you are scared of! I have made it QUITE CLEAR in my post that I was
recommending NO CHANGES to gschem, other than possibly a few more
attributes at the bottom of the list. There are already enough
attributes for each symbol that it is clear that NO ONE in their right
mind enters values for every single attribute when designing the
circuit with gschem, and I doubt that anyone populates every single one
when using gattrib. In fact, the main entry I am pushing for is a PCB
footprint, which already exists. So that would mean ZERO changes to
gschem. I am still confused about how you turn zero changes to gschem
and discussions of gsch2pcb and gattrib only into scary, emotionally
baggage laden attacks on the very heart of gschem.
So please, I need LOTS more clear, instructive explanation of what
kind of *process* affects the copper patterns used by the gschem -
gattrib - gsch2pcb - PCB tool chain, and how recommending only changes
to gattrib and gsch2pcb results in the complete unraveling of gschem.
Mike
References
1. http://www.noqsi.com/
2. mailto:jpd@xxxxxxxxx
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