gEDA-user: oddball TTL part

[Jim Battle <frustum@pacbell.net>]

attached are two views of a 9602 -- it is very much like the 74123 dual 
monostable, but with a different pinout.
v 20020527
P 0 2300 300 2300 1
{
T 100 2350 5 8 1 1 0 0
pin1=1
}
T 360 1400 9 8 1 0 0 0
TRIG1
P 0 2000 300 2000 1
{
T 100 2050 5 8 1 1 0 0
pin2=2
}
T 360 1100 9 8 1 0 0 0
TRIG1
V 250 1700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 1700 200 1700 1
{
T 100 1750 5 8 1 1 0 0
pin3=3
}
T 360 1700 9 8 1 0 0 0
CLR1
V 250 1100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 1400 300 1400 1
{
T 100 1450 5 8 1 1 0 0
pin4=4
}
T 360 800 9 8 1 0 0 0
Q1
P 0 1100 200 1100 1
{
T 100 1200 5 8 1 1 0 0
pin5=5
}
T 1410 500 9 8 1 0 0 0
Q2
P 0 800 300 800 1
{
T 100 900 5 8 1 1 0 0
pin6=6
}
T 1110 2300 9 8 1 0 0 0
C
T 1240 2222 9 8 1 0 0 0
EXT2 
P 0 500 200 500 1
{
T 100 600 5 8 1 1 0 0
pin7=7
}
T 1060 2000 9 8 1 0 0 0
RC
T 1290 1922 9 8 1 0 0 0
EXT2
P 1700 2300 2000 2300 1
{
T 1785 2350 5 8 1 1 0 0
pin15=15
}
T 380 2000 9 8 1 0 0 0
RC
T 620 1922 9 8 1 0 0 0
EXT1
P 1700 2000 2000 2000 1
{
T 1785 2050 5 8 1 1 0 0
pin14=14
}
T 380 2300 9 8 1 0 0 0
C
T 520 2222 9 8 1 0 0 0
EXT1
P 1800 1700 2000 1700 1
{
T 1785 1750 5 8 1 1 0 0
pin13=13
}
T 350 500 9 8 1 0 0 0
Q1
P 1700 1400 2000 1400 1
{
T 1785 1450 5 8 1 1 0 0
pin12=12
}
T 1400 800 9 8 1 0 0 0
Q2
V 1750 1100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 1800 1100 2000 1100 1
{
T 1785 1150 5 8 1 1 0 0
pin11=11
}
T 1200 1700 9 8 1 0 0 0
CLR2
P 1700 800 2000 800 1
{
T 1785 850 5 8 1 1 0 0
pin10=10
}
T 1200 1400 9 8 1 0 0 0
TRIG2
P 1800 500 2000 500 1
{
T 1785 550 5 8 1 1 0 0
pin9=9
}
T 1200 1100 9 8 1 0 0 0
TRIG2
T 300 2740 9 10 1 0 0 0
9602
B 300 200 1400 2500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 700 300 9 4 1 0 0 0
Symbol Unfinished
T 1700 2800 8 10 1 1 0 6
uref=U?
V 250 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1750 1700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
V 1750 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 400 0 8 10 0 0 0 0
device=9602
v 20020527
P 0 2500 300 2500 1
{
T 100 2550 5 8 1 1 0 0
pin1=1
}
T 360 1400 9 8 1 0 0 0
TRIG
P 0 2100 300 2100 1
{
T 100 2150 5 8 1 1 0 0
pin2=2
}
T 360 1100 9 8 1 0 0 0
TRIG
V 250 1700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 1700 200 1700 1
{
T 100 1750 5 8 1 1 0 0
pin3=3
}
T 360 1700 9 8 1 0 0 0
CLR
V 250 1100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
P 0 1400 300 1400 1
{
T 100 1450 5 8 1 1 0 0
pin4=4
}
P 0 1100 200 1100 1
{
T 100 1200 5 8 1 1 0 0
pin5=5
}
T 1210 1600 9 8 1 0 0 0
Q
T 380 2100 9 8 1 0 0 0
RC
T 620 2022 9 8 1 0 0 0
EXT
T 380 2500 9 8 1 0 0 0
C
T 520 2422 9 8 1 0 0 0
EXT
T 1200 1900 9 8 1 0 0 0
Q
P 1400 1900 1700 1900 1
{
T 1485 1950 5 8 1 1 0 0
pin6=6
}
P 1500 1600 1700 1600 1
{
T 1485 1650 5 8 1 1 0 0
pin7=7
}
T 300 2740 9 10 1 0 0 0
9602
B 300 900 1100 1800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1400 2800 8 10 1 1 0 6
uref=U?
V 1450 1600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 1900 1300 8 10 0 0 0 0
device=9602
T 1900 1500 8 10 0 0 0 0
numslots=2
T 1900 1700 8 10 0 0 0 0
slot=1
T 1900 2100 8 10 0 0 0 0
slot1=1,2,3,4,5,6,7
T 1900 1900 8 10 0 0 0 0
slot2=15,14,13,12,11,10,9
T 1900 2500 8 10 0 0 0 0
net=Vcc:16
T 1900 2300 8 10 0 0 0 0
net=GND:8
-----
Jim Battle == frustum@pacbell.net