Re: gEDA-user: PCB: how to merge polygon and component pads?

[Christoph Lechner <cl0023@xxxxxxx>]

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Kai-Martin Knaak wrote:
> On Sun, 16 Aug 2009 17:38:17 +0200, Christoph Lechner wrote:
> 
>> I'm just doing the artwork for a SMPS power supply and I'm wondering if
>> it is possible to make a polygon and the pads of some component merge
>> completely. So not the usual way with a ring around every pad where you
>> see the tracks hidden under the poly
> 
> total connection is one of the thermal styles. You can cycle through 
> the styles of a via with shift-click.
> 
> http://geda.seul.org/wiki/geda:pcb_tips#what_is_the_easiest_way_to_create_a_thermal_via
> 
> 
>> BTW: How do I set the clearline flag for existing tracks ?
>> SetFlag(Selected, clearline) does not work.
> 
> Perhaps, you mean the join flag.
> 
> http://geda.seul.org/wiki/geda:pcb_tips#the_polygons_are_shorting_my_tracks_what_can_i_do_about_it
OK, so I asked two FAQs at the same time.

The join flag actually was what I was looking for.
But when I select the polygon and press 'S' it floods over tracks from
different nets even if they have the clearline flag set.

But I like DJ's solution, because it's selective: The 'S' changes all
pads in the contour while I only want some (caps, inductors, MOSFET)
connected in that way.

Another question just comes to mind: How do I make sure that the
different polygons (each one connected to a different net) don't short?
The DRC doesn't find them.

CU
- - cl
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