Re: gEDA-user: Compiling MMI (electromagnetic simulator)

[Daniel Nilsson <daniel@xxxxxxxxxxxxxxx>]

On Tue, Dec 14, 2004 at 09:21:28AM -0500, Dan McMahill wrote:
> > >I am trying to determine how wide a trace must be to have impedance of
> > >50, 75, 93, 100 ohm and also how much capacitance per length my ordinary traces
> > >will have.
> 
> both the formulas in the ultracad pdf file and the ones listed there are fairly
> approximate.  For an online tool, http://mcalc.sf.net is the most accurate I
> know of.  Of course I'm a bit biased.  That said, I spent quite a bit of time
> looking for the "best" approximations.
> 
> For mcalc, you'll get Z0 and keff.  From that you can calculate L and C.

Great work on the mcalc tool ! I notice you even dare to include the
topic about surface roughness, we debate that a lot within various SI
forums and there are many opinions whether or not surface roughness
really have a impact on the total loss of a channel on normal
backplanes. I don't think so myself, but there is a lot of discussion
on the topic.

> > I get asked the question about total capacitance on a trace rather often but I have
> > still not heard anyone explain to me how that number can be of any practical use. If
> 
> You may care about capacitive loading.  Also if you have say a 4 layer board
> with gnd and vdd as the inner layers, you may care about parasitic coupling
> from a trace to vdd.

Agreed, you might care about these aspects. What I wanted to point out
it that there are were few real world problem where you actually can
use the trace capacitance for design purposes. In the example with the
trace referencing the vdd plane for example, the return current
flowing on the vdd plane is a function of the driver impedance and the
trace impedance. The return current will find its way back to the
driver through decoupling caps a inter-plane coupling. If you wanted to
calculate the magnitude of this return current you would use the trace
impedance, not the total trace capacitance.

I'm not disagreeing with your examples, what I wanted to highlight is
that in modern electronics you typically have to treat traces as
distributed elements that have impedance and delay. There is some
lingering "old school" thoughts about the "total capacitive loading"
that we used to use back in the days when the slew-rates were so slow
that the PCB traces looked like lumped elements. Then the input
capacitance of the receivers set the performance limits of the
circuit, so we used to sum up all the receivers load by calculating
fan-out and such. When slew-rates got faster, I sometimes hear people
say that we now should add the total trace capacitance to the input
loading of the receiver in order to estimate the delay. What I want to
point out is that this is seldom a valid approach (expect for on-chip
interconnect, but that's a different story). With faster electronics,
PCB interconnect should be simulated and compared against standard
load in order to determine delay. With fast in this case I mean
applications where the electrical length of the interconnect is longer
then 1/10 of the risetime of the signals. If you slower speed
applications, I can see some use of the total trace capacitance but we
seldom worry about delay on those classes of signals any more.


-- 
Daniel Nilsson