Re: gEDA-user: geda-user Digest, Vol 43, Issue 35 on pin mapping

[John Eaton <z3qmtr45@xxxxxxxxx>]

   On Dec 26, 2009, at 7:11 PM, DJ Delorie wrote:
      > I took the time to document my ideas about heavy vs light symbols
   and

     > the pin mapping problem:
     >
     > [1]http://www.delorie.com/pcb/component-dbs.html
     > [2]http://www.delorie.com/pcb/pin-mapping.html
     >
     > I got tired of looking it up in the mail archives or referencing
     it as
     > "some time in the past...".
     >
     > If you remember me saying more about these than I wrote down, and
     can
     > find it in the mail archives, let me know so I can add to them.
     >
     > DJ
     >


   ----------------------------------------------------------------------
   ---------
   So you need to support traditional issues with 7400 style parts as
   well as pld/fpga mappings.
   For 7400's you need:
   Multiple symbols per function ( normal and demorgan)
   Swapping instances within a package of multiple parts
   Swapping between packages.
   Reoptimizing groups of logic into a different group ( not a 1:1
   translation)
   PLD/FPGA is more complex. You could fix a pin out up front and have
   both the pcb and logic design to that pin out but it is likely that
   one or both of these designs would be suboptimal. You really need to
   design both at the same time knowing that pin swaps that help one
   could harm the other.  You want to be able to swap pins on a pcb
   layout and then pass that back to the fpga compiler and have it
   relayout the fpga to see if it still meets timing. The fpga must start
   the process with a file that details what all the options and
   restrictions are what "knobs" the pcb layout can turn.
   John Eaton

References

   1. http://www.delorie.com/pcb/component-dbs.html
   2. http://www.delorie.com/pcb/pin-mapping.html


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