Re: gEDA-user: six-layer stack

[sdb@xxxxxxxxxx (Stuart Brorson)]

[...]
> Which is pretty much what I had in mind when I started.
> 5+5+30+5+5, right?  And I consider my collection of eight
> power supplies as signals, which need to have a high-capacitance
> low-inductance coupling to the nearby ground.

The thicknesses you get are usually determined by the thickness of the
raw materials stocked by your board vendor.  You may or may not have
much flexibility there.

It sounds like you are trying to create a controlled impedance board,
with some traces 50ohms, or somethign like that.  I say that because
you are interested in the dielectric thickness of your materials.  If
so, I suggest that you just spec the impedance of the tracks you need
to control, and let the board house vary the track width and laminate
thickness to match their process while still getting you your desired
impedance.  That's how I usually see it done.  

[ ... ]
> > If you Google around, you can find lots of discussion about good
> > stackups.  Here's one: http://www.ce-mag.com/ARG/Grasso.html
> 
> Good picture, kind of minimal on-topic discussion.

The discussion was about clocks, but hte picture was good which is why
I posted the link.  It also came up early in a Google search.
Finally, one of the authors (Charles Grasso) is a frequent contributor
to the SI-list, which is a good resource for learning about this kind
of stuff.  If you're doing high speed stuff, it pays to subscribe to
that list.

Stuart