From: Mike Jarabek <mjarabek@xxxxxxxxx> Reply-To: geda-user@xxxxxxxx To: geda-user@xxxxxxxx Subject: Re: gEDA-user: iverilog & PALs? Date: Wed, 22 Feb 2006 08:58:08 -0500
Hi,
On Tue, 2006-02-21 at 22:09 -0500, Dave McGuire wrote: > On Feb 21, 2006, at 9:40 PM, Stephen Williams wrote: > >> Hi folks. Can anyone tell me if I can use Icarus Verilog to > >> generate > >> the files required to program PAL/GAL chips like the 16V8 and 22V10? > > > > There is the ipal project intended to do exactly that, right > > down to JEDEC files. It suffers from considerable bit rot, though. > > > > <http://www.icarus.com/eda/ipal/index.html> > > Yes I ran across that, and my eyes lit up until I saw the last dev > snapshot was made five and a half years ago. :-/ > > Well I certainly won't complain too much...I know you've been > spending a lot of time on iverilog itself, with which I find myself > spending more and more time. =) > > So I assume my only option at this point is a DOS emulator and the > old PALASM distribution that's been floating around? (I'd much rather > use Verilog, but I'll take what I can get, as my alternative is to use > an XC9536 where a GAL16V8 will do) > I don't think that this answers your original question, but I have used the tools in the `jedec.tar.gz' tarbal to produce fusemaps for 22V10's. It is pretty basic, you have to give names to the active pins, set the options for the FF's (if used) and then write out the logic equations for each of the outputs. Looking at ftp.funet.fi, there appears to be the source code for `PLPL' which was AMD's PAL compiler from the late 80's, it is capable of a bit of optimization.
You can find the files at: http://www.ftp.funet.fi/index/cae/AMD/
(Although I can't seem to download anything in the upper level directory. If need be I can post the files on my web site.)
Mike