Re: gEDA-user: Polygon clearance around a hole

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Subject: Re: gEDA-user: Polygon clearance around a hole

From: "Justyn Butler" <justynbutler+geda@xxxxxxxxxxxxxx>

Date: Thu, 22 Feb 2007 17:28:54 +0000

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On 22/02/07, DJ Delorie < dj@xxxxxxxxxxx> wrote:

> It doesn't seem to be possible to have polygon clearance around an
> unplated via (a via with the "hole" flag).

What version of pcb? It seems to work ok in cvs.

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