Re: gEDA-user: PCB suggestion

[Karel Kulhavy <clock@xxxxxxxxxxxxx>]

On Wed, Jan 05, 2005 at 07:41:31PM -0500, Stuart Brorson wrote:
> > 
> > to understand that metal layer DRCs are different from the silk layer, or to
> > deal with elements having various "grouped" metal, mask, and silk features
> > if all layers were arbitrary.
> 
> Yeah, I agree.  I wasn't focussed on thinking while writing this
> particular paragraph.  I *do* think a built-in stack-up like that
> which I suggested: 
> 
> silk_top (pos)
> mask_top (neg)
> paste_top (neg)
> metal_top (pos or neg)
> int2 (pos or neg)
> int3 (pos or neg)
> etc. . . . 
> metal_bot (pos or neg)
> paste_bot (neg)
> mask_bot (neg)
> silk_bot (pos)
> Assembly (pos)  (perhaps have top and bottom?)
> Board outline  (or just consolidate with Assy layer?)
> Drill
> 
> makes sense.  Then, the program will know that if I put a pad on teh
> top layer, it will put the right metal_top rectangle down, cut the
> right void in mask_top & paste_top, and so on.  It will also know that
> if I place a via, it should connect to the metal layers where

What about doing it a bit sodipodi-style (http://www.sodipodi.com) where
you can group object together?

A pin would be grouping of it's annuli on the layers, plus mask cutouts.
Element would be a grouping of couple of these groupings etc.

Cl<