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Re: gEDA-user: EDIF standard?
2009/1/5 DJ Delorie <dj@xxxxxxxxxxx>:
> If a standard is not documented with freely available documentation,
> it's unlikely any of us will even be interested in it.
Icarus verilog outputs EDIF for fpga targets...
Of course I would be able to RTFS to figure out the subset it generates,
but in such cases I prefer to implement the standard, not an
interpretation of it.
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