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Re: gEDA-user: taking issue with Symbol creation

Consider a 3x3 BGA chip:

pinseq	 pinnum	   pinlabel

1	 A1	   Vdd
2	 A2	   ENA
3	 A3	   SCLK
4	 B1	   SDI
5	 B2	   SDO
6	 B3	   ENB
7	 C1	   D0
8	 C2	   D1
9	 C3	   Vss

For simulation, pinseq maps the pins to the model's pins, but
otherwise, it's just a sort key.


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