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gEDA-user: suffix for Verilog include files



Friends -

OK, really stupid question: is there a "standard" suffix
to use for Verilog include files?  I need something different
from .v, so my Makefiles and scripts can tell them apart:
include files don't get listed on the Icarus command line,
even though they are a dependency listed in the Makefile.

I have used .vp and .iv myself in the past.  If there is a
consensus I will happily switch to it.  Consistency is good!

   - Larry


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