gEDA-user: Icarus Verilog: Support for Xilinx Virtex Devices

[Ales Hvezda <ahvezda@seul.org>]

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-- Cut here --
From: Terry Barnaby <terry@beam.demon.co.uk>
Hi,

How well developed is the support for Xilinx Virtex devices in Icarus
Verilog ?

I have been trying to build a simple module using Icarus Verilog and the

Xilinx Foundation 2.1tools for a v400bg560-6, under Linux, but have not
been
having much success. Perhaps someone could help ?

I am having problems with constraining module ports to pins. I have a
simple
main module that uses another Adder module.

module main(clk);
input clk;

wire clk;
reg a;
reg b;
wire r;

Adder adder(clk, r, 1, b);

$attribute(clk, "PAD", "17");
//$attribute(r, "PAD", "L31");
endmodule

First problem is that normally in a Foundation 2.i constraint file I
would use the pin
named L17, however Icarus Verilog seems to only take a number and in the
output
EDF file prepends a "P" to the number.

Second if I use just a number, as in the above code, I get an error
durring the map
phase:

ERROR:basmm:172 - Bad format for LOC constraint P17 on U1PAD. To bypass
this
   error set the environment variable 'XIL_MAP_LOCWARN'.

I use the commands:

iverilog -tfpga -parch=virtex -o test1.edf test1.v
edif2ngd -p v400-6-bg560 test1.edf test1.ngo
ngdbuild -p v400-6-bg560 test1.ngo test1.ngd
map -o test1_map.ncd test1.ngd

Any ideas ?

Terry

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