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Re: gEDA-user: Icarus misses unconnected nets?
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Tom Hawkins wrote:
| Stephen Williams wrote:
|
|> Tom Hawkins wrote:
|> | Icarus is not reporting unconnected nets with -Wall. Am I missing
|> | something? I always thought it did.
|> |
|> | 1 module test (x);
|> | 2 output x;
|> | 3 wire b;
|> | 4 assign x = b;
|> | 5 endmodule
|> |
|> | $ iverilog -Wall test.v
|> | $ # Nothing!
|> |
|> | I'm running 0.8.
|>
|> It reports unconnected *inputs* because they affect the behavior
|> of the module. It is common and reasonable (I believe) to have
|> unconnected outputs. Also, it reports on unconnected ports at the
|> instantiation, so ports to a root module are not reported.
|
|
| That makes sense.
|
| I'm trying to debug a large, flat, ugly module -- not mine, of course.
| It has many wires feeding a lot of logic, but nothing is driving them!
| It'd be nice if Icarus reported these dangling nets, but I realize
| linting is not it's primary job.
Actually, it would I think be an interesting feature to be able to
warn about undriven nets actually being used. It should be able to
tell the different between an unconnected net and one that is being
read only. That's bound to be a problem in the Verilog source, eh?
| BTW, How's vectorized iverilog coming?
It's coming. I'm up to 580 tests passed, compare to 680 or so that
are passed by 0.8. I'm not all that far from making a snapshot, actually,
although CVS has been kept up to date.
As a consequence of all this, I've simplified the ivl_target.h API,
and improved its documentation somewhat, including an improved stub.tgt
that is these days actively checking that the ivl_target.h assumptions
are properly asserted.
- --
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."
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