gEDA-user: Re: gEDA-dev: google SOC

[John Griessen <john@xxxxxxxxxxxxxx>]

Dan McMahill wrote:
> Getting back to the critical short term question,  are there interested 
> students and mentors?

After reading the FAQs about google's program, I can probably commit enough time
to do some good work if I get a stipend, since my rent is low...

If interested, I'll  write a student app up they will read and maybe fund -- 
they are funding 600 this year.  Making hooks to use gnetman/datadraw memory 
resident data structures in PCB and gnetlist is the one with the highest value 
to my mind, and my chip A2D D2A and logic design plus layout experience with 
Cadence and Mentor tools helps me understand what is important.

With changes like that, PCB could move up a level of abstraction and just be 
called Layout..or Circuit, and be used for FPGAs and chips.  gschem might not 
need gnetman/datadraw right away to make sense overall, since a lot of the input 
is not schematics at all, just text-processed netlists to be generated directly 
from iverilog code.


From the mentoring viewpoint, gEDA is high value and understandable by 
Googlers...it creates more independent designers in the world by presenting 
tools for them to use life long when they are deciding what to do in school/life.

This seems to be the application in a nutshell:
=============
there is a 7500-character limit to proposals, so be prepared to supplement your 
proposal text with links to an external site. However, you should still plan to 
provide an abstract of your proposal, including a brief list of deliverables, 
via the GSoC web app to ensure that your work receives sufficient review; terse 
applications tend to look like incomplete applications during the review process.
=======================


John Griessen

EE with microcontroller assembly exp. and a burning need to get good at using 
GCC compiled C with the MSP430 for my sensornet project.  I also want to become 
more able to contribute to PCB and gschem.


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