gEDA-user: generate within verilog

[ldoolitt@xxxxxxxxxxxxxxx]

Friends -

I just tried to use a generate loop for the first time
within iverilog (2007-03-07 CVS).  No joy.

At Steve's request, I filed a sourceforge bug, that
you can view at
  https://sourceforge.net/tracker/index.php?func=detail&aid=1676071&group_id=149850&atid=775997
I won't attach the full test here, you can download it
from that bug report.

I humbly request someone on this list to check that my
code actually runs on a non-Icarus simulator, or even
proofread my generate code (which I tried to crib from a
reliable source, and passes Icarus's syntax, even if it
doesn't actually do anything).

module adder(a, b, ci, out, co);
parameter SIZE=8;
input [SIZE-1:0] a;
input [SIZE-1:0] b;
input ci;
output [SIZE-1:0] out;
output co;

wire [SIZE:0] c;
assign c[0] = ci;
assign co = c[SIZE];
genvar i;
generate for(i=0; i<SIZE; i=i+1) begin:addbit
        add1 bit(a[i], b[i], c[i], out[i], c[i+1]);
end endgenerate

endmodule

Also, if anyone out there actually uses Icarus's generate
feature successfully, I'd like to hear about it.

   - Larry

P.S. Apologies if this post is duplicated;  I think the
system ate my first attempt because I wasn't subscribed yet.


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