Re: gEDA-user: What's your way of syncing CPLD design and gschem symbols???

[ldoolitt@xxxxxxxxxxxxxxx]

Friends -

On Thu, Mar 08, 2007 at 10:47:45PM +0100, Christoph Lechner wrote:
> The timing issues following from forcing the Xilinx tool
> to use a user-defined pin-out are non-trivial IMHO, at
> least for CPLDs.

On "modern" (Virtex-1 and better) FPGAs, I have never had
a problem.  Always use latches in the IOB, and for higher
speed designs, devote one clock cycle to moving data to the
fabric.

      - Larry


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user