gEDA-user: Re: Design Flow Roadmap starting point

[Levente <levente.kovacs@xxxxxxxxxxxx>]

DJ Delorie <dj@xxxxxxxxxxx> wrote:
> 
>> While I am at it. PCB should be able to do hidden vias, buried vias
>> and micro vias...
> 
> If we can get the "layer types" project done (this is listed as the
> non-copper layers project in SoC), we'll be able to have a concept of
> a "layer stack" (unless we just assume the physical stack matches the
> GUI layer layout).
> 
> The next project after that is what I call a "multi-pin", which is a
> standard pin, but with a much more intense copper description, one for
> each layer, with drill depth parameters et al.  That would include
> blind and buried vias.  Microvias is just a drill size after that,
> unless you need them called out in a different .cnc file.


I use the CR5000 system at my work, where you can define so called padstack.
With it, you can place any copper, non copper layers, than you can use your
padstack to build elements up. The copper and non-copper layers are totally
independent.

BTW hard drc. With CR5000, you can define so called Ignore areas (as non copper
layers). For example, an area, where you can not place wire, another where you
can not place other components. IMHO, these are very useful features.

Just my HUF 100...

 

-- 
Levente
http://web.interware.hu/lekovacs



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