[Author Prev][Author Next][Thread Prev][Thread Next][Author Index][Thread Index]

Re: gEDA-user: Polygons in PCB

Why is that?

The board house I use (4pcb) requires soldermask clearance for vias.
I'm sure they are not the only ones.

On Mon, Mar 8, 2010 at 9:49 AM, DJ Delorie <dj@xxxxxxxxxxx> wrote:
>
>> Is there anyway to place vias that have a soldermask clearance MORE
>> than 0?
>
> The code for inserting new vias has a zero hard-coded in the function
> call (action.c, look for CreateNewVia).
>
>
> _______________________________________________
> geda-user mailing list
> geda-user@xxxxxxxxxxxxxx
> http://www.seul.org/cgi-bin/mailman/listinfo/geda-user
>


_______________________________________________
geda-user mailing list
geda-user@xxxxxxxxxxxxxx
http://www.seul.org/cgi-bin/mailman/listinfo/geda-user