gEDA-user: PCB+GL Branches: URGENT WARNING

[Peter Clifton <pcjc2@xxxxxxxxx>]

Dear all,

It has come to my attention that my PCB+GL branches (starting from
"polygon_speedup" onwards, contain a flaw which can in some
circumstances result in subtly corrupted polygons - which can in turn
ruin a finished board's connectivity.

It is very important that until this is resolved, all those working with
my experimental branches either:

1. Export their gerbers from git HEAD PCB rather than my branch.
2. Check their gerbers _incredibly_ carefully.
3. Disable some of the polygon speed-up functionality as follows:

In src/polygon.c, you will find two lines:

#define SUBTRACT_PIN_VIA_BATCH_SIZE 100
#define SUBTRACT_LINE_BATCH_SIZE 1

(Older versions of my branches had line batch size > 1, but I cut back
to 1 due to a similar bug).

Change these to read:

#define SUBTRACT_PIN_VIA_BATCH_SIZE 1
#define SUBTRACT_LINE_BATCH_SIZE 1


It appears this will work-around the issue for cases I've encountered,
but unfortunately it will slow down polygon processing.


I discovered this defect the hard way, with two boards on my bench
needing awkward rework due to this problem. One was an obvious polygon
corruption shorting out some tracks which I missed in gerbv.. the other
was a pin which fails to clear its polygon on file-load, resulting in a
short to ground-plane.

I sincerely hope this has not bitten anyone else.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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