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gEDA-user: NOR sr latch does not converge with ngspcie r22
The attached netlist does not converge. Doesn't matter what the inputs
are, you could put a ramping voltage and it will be the same result.
NAND latches work just fine, but nor doesn't.
X1 reset qbar q pwr nor2
************************************************************
* Cell: nor2 *
************************************************************
.SUBCKT nor2 a b out pwr
M3 o a 0 0 n w=4u l=0.5u m=1
M4 o b 0 0 n w=4u l=0.5u m=1
M1 n0 a pwr pwr p w=8u l=0.5u m=1
M2 o b n0 pwr p w=8u l=0.5u m=1
.ENDS nor2
************************************************************
X2 q set qbar pwr nor2
.END
.MODEL n NMOS ( LEVEL = 3
+ TOX = 1.4E-8 NSUB = 1E17 GAMMA = 0.5483559
+ PHI = 0.7 VTO = 0.7640855 DELTA = 3.0541177
+ UO = 662.6984452 ETA = 3.162045E-6 THETA = 0.1013999
+ KP = 1.259355E-4 VMAX = 1.442228E5 KAPPA = 0.3
+ RSH = 7.513418E-3 NFS = 1E12 TPG = 1
+ XJ = 3E-7 LD = 1E-13 WD = 2.334779E-7
+ CGDO = 2.15E-10 CGSO = 2.15E-10 CGBO = 1E-10
+ CJ = 4.258447E-4 PB = 0.9140376 MJ = 0.435903
+ CJSW = 3.147465E-10 MJSW = 0.1977689 )
.MODEL p PMOS ( LEVEL = 3
+ TOX = 1.4E-8 NSUB = 1E17 GAMMA = 0.6243261
+ PHI = 0.7 VTO = -0.7444911 DELTA = 0.1118368
+ UO = 250 ETA = 0 THETA = 0.1633973
+ KP = 3.924644E-5 VMAX = 1E6 KAPPA = 30.1015109
+ RSH = 33.9672594 NFS = 1E12 TPG = -1
+ XJ = 2E-7 LD = 5E-13 WD = 4.11531E-7
+ CGDO = 2.34E-10 CGSO = 2.34E-10 CGBO = 1E-10
+ CJ = 7.285722E-4 PB = 0.96443 MJ = 0.5
+ CJSW = 2.955161E-10 MJSW = 0.3184873 )
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