Re: gEDA-user: draw_binary_real??

["cfk" <cfk@pacbell.net>]

Dear Stephen:
   Sure, just go to http://www.opencores.org and download the ethernet
project, expand it, go to the bench directory, correct the 8'd1 issue in
tb_ethernet.v and compile with iverilog.

    Unfortunately, I have no clue how to go about finding the one line of
verilog in the 30 source code files containing about 50000 lines of verilog
that beget this eval_real error. Is there any way to tell icarus to tell us
the source code file and line number that the error is occurring on??


----- Original Message -----
From: "Stephen Williams" <steve@icarus.com>
To: <geda-user@seul.org>
Sent: Friday, May 23, 2003 3:39 PM
Subject: Re: gEDA-user: draw_binary_real??


>
>   XXXX draw_binary_real(%)
>   ivl: eval_real.c:83: draw_binary_real: Assertion '0' failed.
>
> That is saying that Icarus Verilog encountered a % expression
> in a spot where it thinks it is working in a real expression.
> It's probably legal code, but a gap in Icarus Verilog real valued
> expression support. Shouldn't be hard to fix that one, so if you
> can make a one page example that tickles this bug, I'll fix it.
> --
> Steve Williams                "The woods are lovely, dark and deep.
> steve at icarus.com           But I have promises to keep,
> steve at picturel.com         and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."
>