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Re: gEDA-user: DRC annular ring suggestion

Darrell Harmon wrote: 
From the Sierra proto express design rules:
 Minimum trace & space:  	6 mil
Minimum width of Annular Ring: 	5 mils

When I set the DRC in PCB to these values and create vias with a 5 mil
annular ring, I get:

17: Rules are minspace 6.00, minoverlap 4.0 minwidth 5.99, minsilk 4.99
min drill 14.99, min annular ring 4.99
18: Via annular ring is too small based on minimum copper width
19: near location (748.03,1259.84)
20: Found 1 design rule errors

The via was a 15 mil drill with a 25 mil pad. I think PCB should not
give a DRC error in this case as some pcb manufacturers have a smaller
annular ring size than minimum copper width. For now I have just set
the minimum copper width to 5 mils to solve the problem.


which set of rules? I looked under their "Standard Technology PCB" page and I read it to say 5 mils min trace & space with 7.5 mils annular ring. But perhaps you were looking at a different service from them.

I could probably remove the min width check on pins/vias now that there is an explicit annular ring check though.

-Dan