gEDA-user: [ANN] InFormal 0.1.1 Released

[Tom Hawkins <tom@confluent.org>]

Hello,

I just released InFormal 0.1.1: a new open-source assertion based 
verification tool. InFormal can prove the correctness of Verilog designs 
without using simulation -- otherwise known as formal verification.

With release 0.1.1, InFormal now provides initial support for PSL/Sugar. 
 Currently only a small subset of PSL is supported, but it's PSL never 
the less.

Though InFormal is in very early beta, it has already uncovered bugs in 
real designs -- in part thanks to automatic assertions.  Using 
InFormal's automatic assertions, engineers can find potential design 
issues without having to explicitly define PSL properties.

InFormal leverages the elaboration and synthesis technology of Icarus 
Verilog with the high performance symbolic model checking engine of 
NuSMV.  Many thanks to the Icarus and NuSMV teams for providing their 
awesome open-source technology.

For more information on InFormal, including source code and Linux 
binaries, visit:

  http://www.confluent.org/

Enjoy!

-Tom