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Re: gEDA-user: Thermal overries mask of neighboring via's and holes



Jeff VR wrote:

As I was putting the finishing touches on my board and connecting my mounting holes to the GND plane I noticed what seems to me to be an oddity. I had a neighboring via that was appropriately clearing the GND plane polygon and meeting the DRC clearances. When I added the thermal to the mounting hole one of the thermal fingers went into the mask of the via. I think I'm using the right terminology? This happened again with a pin of one of my connectors. I didn't get an warnings after <key> o about shorts between the Net and GND? Should I create an example schematic? I'm using version 20050609. I realize this is an older version but I'm in a hurry to get my board done before doing a clean install from the CVS trunk or latest release.


This bug was fixed with the polygon clipping code added recently. Only the current CVS code has this bug fixed.

h.



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