Re: gEDA-user: icarus, fork, and recursive tasks

[John Griessen <john@xxxxxxxxxxxxxx>]

On 11/06/2010 06:37 PM, DJ Delorie wrote:
> I'm trying to simulate an MCU's bus processor, which has a couple of
> timing parameters all keyed off the start of a transaction.
>
> Naively, I did this:
>
>        fork
> 	 mcu_cson (address);
> 	 mcu_wron (address);
> 	 mcu_wdon (address);
> 	 mcu_cswwait (address);
>        join

What you want to do is make mcu_cson mcu_wron etc registers.  Then you can add delays to model their
action, their timing.  All those functions in verilog are always acting in parallel and need no
procedure.  The only thing you would want a procedure for in verilog is to calculate something not
available as a primitive, like a huge list of instructions that all cause one wire to be high.
You'd make that as a procedure, feed it to a wire, then connect that with assign statements to make
the logic you want to model timing of.

To model the state of the registers after complicated machine instructions, use a
begin end block like:

begin
 at posedge delay # 40 clock1 assign A + B or C --> mcu_cson
end

It's been a while.  Probably some mistakes.

John G


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