On 11/08/2010 11:02 AM, DJ Delorie wrote:
$ iverilog -o sim -Wall -g1 tasks.v
tasks.v:10: syntax error
sh: line 1: 13425 Done /usr/lib/ivl/ivlpp -L -F"/tmp/ivrlg241f26ea8" -f"/tmp/ivrlg41f26ea8" -p"/tmp/ivrli41f26ea8"
13426 Segmentation fault (core dumped) | /usr/lib/ivl/ivl -C"/tmp/ivrlh41f26ea8" -C"/usr/lib/ivl/vvp.conf" -- -
`timescale 1ns / 1ps
module task_test ();
<snip>
endmodule // task_test
Just for giggles I ran that through my copy of Modelsim. http://imagebin.org/122374 Seems to work fine there. Eric _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user