Re: gEDA-user: powermeter board, with less ground planes :-)

[Joerg <joergsch@xxxxxxxxxxxxxxxxxxxxx>]

DJ Delorie wrote:
> http://www.delorie.com/electronics/powermeter/
> 
> I merged the three ground planes into one, and draw AVdd from DVdd for
> each chip, with a 10R/10uF power filter.
> 
> There's still a big hole in the ground "plane" where the Vdd plane
> goes, as well as all the digital signals to each chip.  There's a
> bunch of bypass caps across the boundary between the ground and power
> planes; six 10u scattered plus 0.1u at each chip.
> 
> All the digital signals have series resistors on them to slow down the
> edges, except for reset which doesn't change once the board is
> running.
> 
> Better?  (or at least, good enough? ;)
> 

Much better. If you want to be extra good provide another 0.1uF parallel 
to the AVDD caps, close to pin 3. C13 in your channel.sch file. However, 
10uF cermamics in SMT are already quite good these days, and cheap. If 
you can get C13 closer to pin 3 that would also help.

Might want to rotate C11 and squeeze it in between R18/C12 so it's 
closer to pin 4. But that really only matters if you expect lot of RF 
from cell phones and stuff.

Some day maybe you could post the whole schematic so folks who are new 
to gEDA like me can test drive a schematic with hierarchical order. 
Somehow I never managed to find the Scandinavian example.


> 495 parts so far!  367 holes, 290 of which are vias.
> 

If it's any comfort my board that is in fab right now has 585 parts :-)

Question: IIUC you haven't had the board produced yet. How did you 
create this nice rendering of a finished circuit board?

-- 
Regards, Joerg

http://www.analogconsultants.com/

"gmail" domain blocked because of excessive spam.
Use another domain or send PM.



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