gEDA-user: Curious Behaviour

[andrewm <andrewm@xxxxxxxxxxxxxxx>]

Guys,

Don't know if this is a bug or not.

I have a PCB that is metric grid of 0.05mm.

I have my 0.45mm pitch QFN package all lined up on the
grid so traces end on the pads.

I make a component get too close to a via (purposefully to
replicate the behavior)

I do a DRC and it pops up the clearance error (highlighting
it blue)

My grid has been messed up and my traces no longer land
on the 0.45mm pitch pads.

I have to set the grid to imperial 0.1mil and select all
components and move then a given amount to realign the
grid.

I googled a bit at http://archives.seul.org/geda/bug/ to see
if anyone else had come across it but came up blank.

Am I doing something wrong?  It is very annoying having
to re line up everything each time a DRC fails. (I am
making a PCB that every 10th of a millimeter counts)






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