Re: gEDA-user: Functional blocks and PCB format changes

["Windell H. Oskay" <windell@xxxxxxxxx>]

On Sep 4, 2010, at 4:30 AM, Ineiev wrote:

> Hello, DJ;
> 
> On 9/4/10, DJ Delorie <dj@xxxxxxxxxxx> wrote:
>> Our DRC engine could use a complete rewrite.  It doesn't get arcs
>> right, for example.
> 
> Could you elaborate on the arcs, please? what it doesn't do?

I've been running into trouble with the DRC and arcs, myself.  I discovered it when doing some simple tests of the toporouter-- certain arcs produce DRC errors when there clearly is none-- says that there isn't 10 mils of clearance when there obviously is much more than that.

Here's a minimal test case that demonstrates the errors:   http://evilmadscientist/source/temp/topo_puzzle.pcb


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