Re: gEDA-user: pcb âOptimize routed tracksâ problems

[Colin D Bennett <colin@xxxxxxxxxxx>]

On Mon, 12 Sep 2011 19:04:35 -0700
Andrew Poelstra <asp11@xxxxxx> wrote:

> On Mon, Sep 12, 2011 at 02:38:20PM -0400, DJ Delorie wrote:
> > 
> > > 1. My board has an LQFP48 footprint rotated 45 degrees.
> > 
> > The ability to rotate parts happened after the optimizer work.  Any
> > math majors want to take this one?
> >
> 
> I'm interested, but time-strapped. Can you give me a quick
> outline of what "Optimize routed tracks" is supposed to do
> and what source files it uses?

I looked back at DJ's page on the pcb trace puller
<http://www.delorie.com/pcb/puller/> and realized that the
instructions there rely on using arcs in the tracks.  Perhaps a
sequence of lines is not pulled properly?

My goal was to do some rough, but not pretty (nor tightly spaced)
routing of traces, then use the puller to pull all my parallel
traces nice and tightly together as they bend around other parts,
and to eliminate all the âjaggiesâ as they stairstep down together
in certain cases.

Anyway, it sounds like in their current state, the
Optimize Tracks tools are not really usable for manually routed
boards.  If they would at least adhere to DRC constraints, that
would make them more of an option.  (Note that my initial traces
before running the optimizer did pass DRC with no errors.)

Regards,
Colin


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