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Re: [tor-talk] FPGA Tor Relay

On Thu, 25 Feb 2016 12:21:42 -0800
Ryan Carboni <ryacko@xxxxxxxxx> wrote:

> http://netfpga.org/site/#/systems/1netfpga-sume/details/
> This is apparently available for an academic price of around two
> thousand dollars.

And then you have a programming job on your hands to adapt Tor into the FPGA,
that could cost one or two magnitudes more than that...

> Such cards will probably have to be used in the near future, at least
> to reduce bandwidth costs per gigabit/s speed.

Maybe I'm missing something, how anything you do inside your server (run Tor
on CPU, GPU, FPGA or magic fairies) will reduce your *bandwidth* costs?

> I imagine infrequent operations and operations likely to be changed
> between Tor versions could be offloaded to the CPU.

- Tor is already sped up immensely if you use a CPU which has the hardware AES
  acceleration, i.e. almost any modern x86 CPU. (Not sure if there are any
  other operations you could offload to FPGA, or if FPGA could be faster than
  an AES-NI CPU at AES.)

- ...then you could optimize Tor to use more than ~1.3-1.5 of a CPU core at
  most as it does currently to scale further, as many modern CPUs easily have
  6-8 cores. (This is likely easier than rewriting it to use FPGA). As a
  stop-gap measure, people with such CPUs currently have to run two instances
  of Tor per each IPv4 address their server has.

In the end, if you could just fully load 8 cores of a humble $170 AES-NI CPU, I
believe this should be already enough to process a full gigabit of traffic, or
even more. And you don't really need much more, since it is rare that you can
reasonably get more than a gigabit of unmetered bandwidth per single server.

With respect,

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