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Hi Mike, Thanks for a quick reply. Maybe its my warped mind that had me consider that the management of timeouts (sliding the timeout up and down - as it appears in the logs) would affect the distribution of timeouts and therefore the pareto distribution around them. I will admit to experimenting with smaller values of CBT_DEFAULT_QUANTILE_CUTOFF. These lead to 'peaks' in the timeout distribution. The smaller the value, the tighter these 'peaks' seem to be. I assumed from this that as the timeout is moved up and time from the management code, that these islands of circuit build timeouts would appear around the current timeout values. I admit this could be conjecture and speculation, apart from the build timeouts I see in the state file. With kind regards, Cav Edwards Mike Perry wrote: Thus spake Cav (cav@xxxxxxxxxxxxx): |