Re: [tor-talk] FPGA Tor Relay

[coderman <coderman@xxxxxxxxx>]

On 2/26/16, Roman Mamedov <rm@xxxxxxxxxxx> wrote:
> ...
> Maybe I'm missing something, how anything you do inside your server (run
> Tor
> on CPU, GPU, FPGA or magic fairies) will reduce your *bandwidth* costs?

more machines to saturate a gig link.
 in theory, future Tor will handle 10GigE at speed on single host :)



> - Tor is already sped up immensely if you use a CPU which has the hardware
> AES
>   acceleration, i.e. almost any modern x86 CPU. (Not sure if there are any
>   other operations you could offload to FPGA, or if FPGA could be faster
> than
>   an AES-NI CPU at AES.)

compression is the other area FPGA offload could assist with Tor as
is. more important is to make Tor concurrent(well threaded), then
focus on the exotic offloads...



> - ...then you could optimize Tor to use more than ~1.3-1.5 of a CPU core at
>   most as it does currently to scale further, as many modern CPUs easily
> have
>   6-8 cores. (This is likely easier than rewriting it to use FPGA).

aha, the thread need stated! carry on,



> In the end, if you could just fully load 8 cores of a humble $170 AES-NI
> CPU, I
> believe this should be already enough to process a full gigabit of traffic,


there used to be someone keeping track of the current node capacity
king pin. i don't recall what a saturated gigabit needed in terms of
HW...


best regards,
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