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Re: [tor-talk] Tor and AES-NI acceleration , and Tor profiling

On Mon, Nov 7, 2011 at 10:28 PM, Jacob Appelbaum <jacob@xxxxxxxxxxxxx> wrote:
> ...
> What chips do you suggest for this? I was thinking of buying a new
> machine and I think it might be nice to put up a wiki page. I know that
> I have one of those HiFn cards and it worked as well as was expected.

my understanding is that HiFn supports only symmetric and digest
acceleration (w/ hw entropy). [0] the only public key accelerated
devices i've used are montmult in VIA Padlock enabled cores (too slow
for fast relay) and SCA6000 devices (too expensive for a relay?)

the padlock montmult uses the "padlock" engine and the sca6000 is
utilized via the "pkcs11" engine.

still waiting for ssl-shader to be released, it could be promising. [1]

for AES acceleration it's hard to beat Intel's native instruction set
for it.  Tor could of course make better use of these interfaces to
improve performance as Nick pointed out earlier.

>> also avoiding nearly all side channel attacks against AES!
> Aren't you really just replacing them with hardware specific side
> channel attacks against their implementation of AES? :)

backdoor != sidechannel  ;P

0. the HiFn
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