Re: [f-cpu] Supported Instructions

[nico <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hi,
> 
> nico wrote:
> > Most instruction are defined as "optional". If a fcpu is release without
> > such instruction it must give an interrupt handler to handel such
> > instruction.
> >
> > Imagine that FMUL r1 r2 r3 are supported. So the instruction trap and ...
> _________________________________|
> 
> "not" supported, i guess...
> 

Yep !

> > - "something" (a register?) point on the faulty instruction.
> in the CMB (the instruction pointer).
> After the instruction is "simulated", the IP must be incremented...
> 
> > - The handler try to extract the register number to emulate the instruction
> use the IP from the CMB, fetch the 4-byte data and extract the fields.
>

So the hardware extract such fields ? Other wise it will be a true
overkill !
 
> >  - by using some others registers ?
> these are in the new "task". SRB is certainly triggered.
> 
> >  - We need to save some of them (slow?)
> why "slow" ?
>

If there is a context switch !
 
> >  - How to access indirectly the register set ? (to extract data)
> fetch them from the CMB.
>

So you must manipulate the instruction world and then manipulate the
CMB.
But it will be really slow !! Is it usefull ?

> > So ?
> as you say :-)
> 
> > I propose to define (later, much later) the subgroup of instructions. It
> > will depend on space used and the impact on performance.
> time to wait ;-)
> 
> read you soon,
> 
> > nicO
> WHYGEE
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