Re: [f-cpu] Register Bank

[Yann Guidon <whygee@f-cpu.org>]

hi !

Juergen Goeritz wrote:
> > > > this may sound silly, but what about using transparent latches,
> > > > and not flip-flop, for the register set ?
> > >
> > > I don't know... I don't like latches very much.  They're hard to
> > > control (and the name reminds me of "glitches" ;).
> >
> > Latches are also problematic from the testability side. In all design the
> > testability should be considered. You can't do an ASIC if your testability
> > sucks. So synchronous logic without latches should be preferred and
> > asynhronous logic should be avoided. Asynch. logic is even more difficult
> > with FPGAs.
> 
> Hi,
> 
> let me remind you that there will be a clock tree in your design
> somehow (otherwise you run into problems of clock skews). With
> transparent latches you will have to implement a self holding
> logic if the register is not written to - another mux. I would
> use transpartent latches only if some setup times, e.g. for a
> certain statemachine input are critical and must be guaranteed
> to avoid metastable conditions.

ok, ok, we'll use flip-flops :-)
i think that my question is answered now :-)
thanks everyone,

> JG
WHYGEE
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