Re: [f-cpu] Register Bank

[Juergen Goeritz <goeritz@oekomm.de>]

On Fri, 3 Aug 2001, Yann Guidon wrote:
> hi,
> 
> > Depends on how long you can wait after reset. Some registers,
> > e.g. of the internal pipeline statemachines have to be reset
> > anyway. If you use 256 registers in some inplementation you
> > would wait 256 clocks before the built-in selftest routines
> > can start or you make the reset a part of these. :-)
> 
> given the 2 write ports, we have to wait during 32 cycles,
> which is still decent, considering the much longer self-test
> routines.
> 
> And if i'm not mistaken, there should be no scheduling or
> priority problem because it uses the scheduler HW directly.
> 
> i'll have to include that in my C sims.

Great, but I think it would make more sense to do a test
of the registers and leave them zeroed after test end.
Thus You can check '1' and '0' before operation starts,
e.g. write a value 0xff, verify, write 0x0, verify.

JG

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