Re: [f-cpu] Re: FC0 XBAR

[Juergen Goeritz <goeritz@oekomm.de>]

On Fri, 3 Aug 2001, Yann Guidon wrote:

> hi,
> 
> Juergen Goeritz wrote:
> > Maybe I didn't get it yet!? Aren't you guys designing synchronous
> > computing units with registered outputs? Handling the transfer
> > back to the register bank in the next clock? Thus having a
> > pipeline of decoding->read_from_reg&exec->write_to_register->...?
> > Could someone point me to my misunderstanding please?
> 
> i'll have to make a "little drawing", now ...
> 
> <2 hours later ...>
> 
> ok i've done a little sketch.

It's good that you made the drawing! ;)

> you will understand why it is called "superpipeline" because execution occurs
> 2 cycles after the register read has started. As i told you one day, F-CPU
> is not your "average CPU core" :-)

Yes, I remember :-) But then I didn't raise the question
of branching, did I? How much delay will the branch issue
bring in when execution is 2 cycles delayed? The longer
the pipeline gets the longer one waits for the result and
the flags that may be input for branch...

Do you continue execution at both (possible) next instructions
to not get a loss in pipeline filling? Am I missing some
information I should read before making such comments? :-)

> Due to the already complex drawing, i have not included the scheduler
> and other control signals. Even the wire names are not acurate.
> I have included 3 execution units only. However it gives a rough
> idea about how it is designed. You can now read the QDCPOC source code
> with the (partial) map under your eyes.

Would be interesting to see the complete picture...

CU
JG

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