Re: [f-cpu] Register Bank

[nicO <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Thu, Aug 02, 2001 at 08:31:10PM +0200, Yann Guidon wrote:
> > hi !
> >
> > Michael Riepe wrote:
> > > To illustrate what I said before, I wrote a little register bank entity.
> > thanks ! now we have something that we can discuss about :-)
> 
> As long as you do it on *this* mailing list... ;)
> 
> > > It's not the real thing (there is no scoreboard interface, it's not
> > > SIMD capable, and register 0 isn't handled either)
> > this can be added rather easily.
> >
> > > but it already has
> > > 3 read and 2 write ports that can be used simultaneously (except for
> > > the special case that both writers try to write to the same register;
> > > in that case, write port 0 has priority).
> > this case doesn't need to be handled at this location.
> > the scheduler takes care to delay the operation if a conflict occurs.
> 
> Being paranoid without a reason is much better than not being paranoid
> and getting caught ;)
> 
> > this may sound silly, but what about using transparent latches,
> > and not flip-flop, for the register set ?
> 
> I don't know... I don't like latches very much.  They're hard to
> control (and the name reminds me of "glitches" ;).


That's not the problem, most of automatic tools didn't know how to
handel them correclty (to implement BIST, pb of testability, pb for
verification,...)

nicO

> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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