Re: [f-cpu] Re: Floating-Point

[nicO <nicolas.boulay@ifrance.com>]

Yann Guidon a écrit :
> 
> hello,
> 
> Michael Riepe wrote:
> > On Mon, Aug 20, 2001 at 11:33:05PM +0200, Yann Guidon wrote:
> > [...]
> > > > > If there is something to say if the outed data is correct or not ?
> > > > Currently not; the scheduler should know.  But we can add a `here is
> > > > the result, take it or I'll throw it away in the next cycle' signal.
> > > currently, only the IDIV has one.
> > No it doesn't, but I can add one :)
> 
> if you use a fixed-latency approach, you don't need one.
> however, you could want to "optimise" one day with a data-dependent
> algorithm (leading MSB strip, etc...) and as long as the latency is
> still higher than the scheduling queue's depth, it is possible to
> have _one_ "ready" flag if it can be reased enough in advance.
> 
> > > > Something is missing: the lines that select the instruction to execute
> > > > (if the unit can handle more than one instruction).
> > > ??
> > Signals like Sub/Saturate in the ASU, or MacH/MacL in the IMU.
> in the ROP2 unit, these are "mode" flags and "function" flags, right ?
> add/substract would be a "function" and "saturation" would be a "mode"
> flag, i guess.
> 
> nicO wrote :
> > whygee wrote :
> > > Michael wrote :
> > > > Make that `chunk size'; I use std_ulogic_vector(2 downto 0) for it.
> > > oh btw, the SIMD flag is useful for an EU _only_ if you optimize for speed
> > > and/or consumption. This flag is forwarded to the units but it is used mainly
> > > for the making of the writeback mask (in the register set).
> > So the SIMD stuff is for the same thing for register bank.
> The SIMD flag, the Opcode and the size flags are mixed to give a 5-bit
> field (the "write back mask") that goes to the register set.
> one can also combine these flags so only one part of the register
> is "computed" but i am still wondering stuffs about "clock gating".
> 
> The Fetcher and the decoder have to "hold" some instructions,
> when a certain signal is asserted. by default, i use a MUX
> that loops the output to the input, under the control of the
> "next instruction" signal. However, the clocking is often not
> defined _inside_ the units but at the top level of the design.
> One year ago (approximately) we have tried to define a "generic"
> Flip-Flop gate but it is not satisfying yet.
> Could you (nicO and Michael) try to make this kind of generic gate ?
> 
> > But we should always take good habit for improving power consumption
> > (speed and blablabla).
> i have been rather impressed by what you told me about it.
> if well-designed clock management is possible, i believe that
> we can synthesise a really competitive CPU.
> 
> i simply wish that it doesn't
> run "too fast" because otherwise the core will stay idle and spend
> all the time waiting for data from memory ...
> 
> Currently i need hints about core generators for the register set.
> i don't know precisely how to handle the partial writes and the speed
> i can get.
> 
> I am also designing the last (i hope) version of the ROP2 unit.
> This will give a rough estimate of the clock speed.
> 

Typically register bank could be seen as multiported SRAM memory. So
it's hard for me to understand why you need 5 flags to write back the
registers. When you write back a none SIMD 8 bit result does the 56
other bits remain unchange or are zeroed ?

nicO

> >  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
> WHYGEE
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