Re: [f-cpu] Scheduler

[nicO <nicolas.boulay@ifrance.com>]

To be even explicit about my proposal :

@ reg # is the the address of the register # inside the instruction
word.
@ (alone) is the 2 (i miss one sorry) address of the register that will
be write, it correspond to a specific place inside the execution
pipeline (ususefull later for write back).
#active is the number of the active unit for a given pipeline stage,
normaly there is only one active unit for a given pipe stage because FC0
is a one way processor, there is here a problem for instruction with low
thoughput (a thoughput of 1, signify that the unit could give a result
every cycle, a thoughput of 2 is a unit that give a result every 2
cycle). The other parameter is the latency of the unit, typically the
number of pipe stage.
eu1..eu2.. is the data bus from each eu if it exist, it's multiplexed
with #active to give the really used bus.

So if there is a hit and if the work is done (it seems that i forget
this 'and'..) i bypass the access to the register bank (there is 3
register read so 3 bypass mux).
If there is a hit and not a done, a 'dead cycle' should be inserted
(off: a counter of dead cycle should be used to better tune the code).
The done could the flag explain by Michael to say "ok, the output data
is valid".

Is it more explicit ?

nicO
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